tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

i40e: remove unused defines

Remove all the unused defines as they are just dead weight.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

authored by

Jesse Brandeburg and committed by
Jeff Kirsher 3c98f9ee fe21b6c3

+1 -5316
-24
drivers/net/ethernet/intel/i40e/i40e.h
··· 60 60 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 61 61 #define I40E_DEFAULT_QUEUES_PER_VF 4 62 62 #define I40E_MAX_VF_QUEUES 16 63 - #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 64 63 #define i40e_pf_get_max_q_per_tc(pf) \ 65 64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 66 - #define I40E_FDIR_RING 0 67 65 #define I40E_FDIR_RING_COUNT 32 68 66 #define I40E_MAX_AQ_BUF_SIZE 4096 69 67 #define I40E_AQ_LEN 256 70 68 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 71 69 #define I40E_MAX_USER_PRIORITY 8 72 70 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 73 - #define I40E_DEFAULT_MSG_ENABLE 4 74 71 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 75 72 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 76 73 ··· 89 92 #define I40E_OEM_SNAP_SHIFT 16 90 93 #define I40E_OEM_RELEASE_MASK 0x0000ffff 91 94 92 - /* The values in here are decimal coded as hex as is the case in the NVM map*/ 93 - #define I40E_CURRENT_NVM_VERSION_HI 0x2 94 - #define I40E_CURRENT_NVM_VERSION_LO 0x40 95 - 96 95 #define I40E_RX_DESC(R, i) \ 97 96 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 98 97 #define I40E_TX_DESC(R, i) \ ··· 97 104 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 98 105 #define I40E_TX_FDIRDESC(R, i) \ 99 106 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 100 - 101 - /* default to trying for four seconds */ 102 - #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 103 107 104 108 /* BW rate limiting */ 105 109 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ ··· 285 295 u8 tunnel_type; 286 296 }; 287 297 288 - #define I40E_DCB_PRIO_TYPE_STRICT 0 289 - #define I40E_DCB_PRIO_TYPE_ETS 1 290 - #define I40E_DCB_STRICT_PRIO_CREDITS 127 291 298 /* DCB per TC information data structure */ 292 299 struct i40e_tc_info { 293 300 u16 qoffset; /* Queue offset from base queue */ ··· 344 357 I40E_FLEX_SET_FSIZE(fsize) | \ 345 358 I40E_FLEX_SET_SRC_WORD(src)) 346 359 347 - #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 348 - I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 349 - I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 350 - #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 351 - I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 352 - I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 353 - #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 354 - I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 355 - I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 356 360 357 361 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 358 362 ··· 368 390 #define I40E_L4_GLQF_ORT_IDX 35 369 391 370 392 /* Flex PIT register index */ 371 - #define I40E_FLEX_PIT_IDX_START_L2 0 372 393 #define I40E_FLEX_PIT_IDX_START_L3 3 373 394 #define I40E_FLEX_PIT_IDX_START_L4 6 374 395 ··· 508 531 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 509 532 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 510 533 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 511 - #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 512 534 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 513 535 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 514 536 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
-495
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
··· 55 55 */ 56 56 57 57 /* command flags and offsets*/ 58 - #define I40E_AQ_FLAG_DD_SHIFT 0 59 - #define I40E_AQ_FLAG_CMP_SHIFT 1 60 58 #define I40E_AQ_FLAG_ERR_SHIFT 2 61 - #define I40E_AQ_FLAG_VFE_SHIFT 3 62 59 #define I40E_AQ_FLAG_LB_SHIFT 9 63 60 #define I40E_AQ_FLAG_RD_SHIFT 10 64 - #define I40E_AQ_FLAG_VFC_SHIFT 11 65 61 #define I40E_AQ_FLAG_BUF_SHIFT 12 66 62 #define I40E_AQ_FLAG_SI_SHIFT 13 67 - #define I40E_AQ_FLAG_EI_SHIFT 14 68 - #define I40E_AQ_FLAG_FE_SHIFT 15 69 63 70 - #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 71 - #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 72 64 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 73 - #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 74 65 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 75 66 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 76 - #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 77 67 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 78 68 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 79 - #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 80 - #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 81 69 82 70 /* error codes */ 83 71 enum i40e_admin_queue_err { ··· 350 362 /* Request resource ownership (direct 0x0008) 351 363 * Release resource ownership (direct 0x0009) 352 364 */ 353 - #define I40E_AQ_RESOURCE_NVM 1 354 - #define I40E_AQ_RESOURCE_SDP 2 355 - #define I40E_AQ_RESOURCE_ACCESS_READ 1 356 - #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 357 - #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 358 - #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 359 - 360 365 struct i40e_aqc_request_resource { 361 366 __le16 resource_id; 362 367 __le16 access_type; ··· 365 384 */ 366 385 struct i40e_aqc_list_capabilites { 367 386 u8 command_flags; 368 - #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 369 387 u8 pf_index; 370 388 u8 reserved[2]; 371 389 __le32 count; ··· 391 411 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 392 412 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 393 413 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 394 - #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 395 - #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 396 414 #define I40E_AQ_CAP_ID_SRIOV 0x0012 397 415 #define I40E_AQ_CAP_ID_VF 0x0013 398 416 #define I40E_AQ_CAP_ID_VMDQ 0x0014 ··· 419 441 /* Set CPPM Configuration (direct 0x0103) */ 420 442 struct i40e_aqc_cppm_configuration { 421 443 __le16 command_flags; 422 - #define I40E_AQ_CPPM_EN_LTRC 0x0800 423 - #define I40E_AQ_CPPM_EN_DMCTH 0x1000 424 - #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 425 - #define I40E_AQ_CPPM_EN_HPTC 0x4000 426 - #define I40E_AQ_CPPM_EN_DMARC 0x8000 427 444 __le16 ttlx; 428 445 __le32 dmacr; 429 446 __le16 dmcth; ··· 432 459 /* Set ARP Proxy command / response (indirect 0x0104) */ 433 460 struct i40e_aqc_arp_proxy_data { 434 461 __le16 command_flags; 435 - #define I40E_AQ_ARP_INIT_IPV4 0x0800 436 - #define I40E_AQ_ARP_UNSUP_CTL 0x1000 437 - #define I40E_AQ_ARP_ENA 0x2000 438 - #define I40E_AQ_ARP_ADD_IPV4 0x4000 439 - #define I40E_AQ_ARP_DEL_IPV4 0x8000 440 462 __le16 table_id; 441 463 __le32 enabled_offloads; 442 - #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 443 - #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 444 464 __le32 ip_addr; 445 465 u8 mac_addr[6]; 446 466 u8 reserved[2]; ··· 448 482 __le16 table_idx_ipv6_0; 449 483 __le16 table_idx_ipv6_1; 450 484 __le16 control; 451 - #define I40E_AQ_NS_PROXY_ADD_0 0x0001 452 - #define I40E_AQ_NS_PROXY_DEL_0 0x0002 453 - #define I40E_AQ_NS_PROXY_ADD_1 0x0004 454 - #define I40E_AQ_NS_PROXY_DEL_1 0x0008 455 - #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 456 - #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 457 - #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 458 - #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 459 - #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 460 - #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 461 - #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 462 - #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 463 - #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 464 485 u8 mac_addr_0[6]; 465 486 u8 mac_addr_1[6]; 466 487 u8 local_mac_addr[6]; ··· 460 507 /* Manage LAA Command (0x0106) - obsolete */ 461 508 struct i40e_aqc_mng_laa { 462 509 __le16 command_flags; 463 - #define I40E_AQ_LAA_FLAG_WR 0x8000 464 510 u8 reserved[2]; 465 511 __le32 sal; 466 512 __le16 sah; ··· 472 520 struct i40e_aqc_mac_address_read { 473 521 __le16 command_flags; 474 522 #define I40E_AQC_LAN_ADDR_VALID 0x10 475 - #define I40E_AQC_SAN_ADDR_VALID 0x20 476 523 #define I40E_AQC_PORT_ADDR_VALID 0x40 477 - #define I40E_AQC_WOL_ADDR_VALID 0x80 478 - #define I40E_AQC_MC_MAG_EN_VALID 0x100 479 - #define I40E_AQC_ADDR_VALID_MASK 0x3F0 480 524 u8 reserved[6]; 481 525 __le32 addr_high; 482 526 __le32 addr_low; ··· 496 548 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 497 549 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 498 550 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 499 - #define I40E_AQC_WRITE_TYPE_PORT 0x8000 500 551 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 501 - #define I40E_AQC_WRITE_TYPE_MASK 0xC000 502 552 503 553 __le16 mac_sah; 504 554 __le32 mac_sal; ··· 519 573 520 574 struct i40e_aqc_set_wol_filter { 521 575 __le16 filter_index; 522 - #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 523 - #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 524 - #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 525 - I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 526 576 527 - #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 528 - #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 529 - I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 530 577 __le16 cmd_flags; 531 - #define I40E_AQC_SET_WOL_FILTER 0x8000 532 - #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 533 - #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 534 - #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 535 578 __le16 valid_flags; 536 - #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 537 - #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 538 579 u8 reserved[2]; 539 580 __le32 address_high; 540 581 __le32 address_low; ··· 541 608 struct i40e_aqc_get_wake_reason_completion { 542 609 u8 reserved_1[2]; 543 610 __le16 wake_reason; 544 - #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 545 - #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 546 - I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 547 - #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 548 - #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 549 - I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 550 611 u8 reserved_2[12]; 551 612 }; 552 613 ··· 573 646 574 647 struct i40e_aqc_switch_config_element_resp { 575 648 u8 element_type; 576 - #define I40E_AQ_SW_ELEM_TYPE_MAC 1 577 - #define I40E_AQ_SW_ELEM_TYPE_PF 2 578 - #define I40E_AQ_SW_ELEM_TYPE_VF 3 579 - #define I40E_AQ_SW_ELEM_TYPE_EMP 4 580 - #define I40E_AQ_SW_ELEM_TYPE_BMC 5 581 - #define I40E_AQ_SW_ELEM_TYPE_PV 16 582 - #define I40E_AQ_SW_ELEM_TYPE_VEB 17 583 - #define I40E_AQ_SW_ELEM_TYPE_PA 18 584 - #define I40E_AQ_SW_ELEM_TYPE_VSI 19 585 649 u8 revision; 586 - #define I40E_AQ_SW_ELEM_REV_1 1 587 650 __le16 seid; 588 651 __le16 uplink_seid; 589 652 __le16 downlink_seid; 590 653 u8 reserved[3]; 591 654 u8 connection_type; 592 - #define I40E_AQ_CONN_TYPE_REGULAR 0x1 593 - #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 594 - #define I40E_AQ_CONN_TYPE_CASCADED 0x3 595 655 __le16 scheduler_id; 596 656 __le16 element_info; 597 657 }; ··· 611 697 /* Set Port Parameters command (direct 0x0203) */ 612 698 struct i40e_aqc_set_port_parameters { 613 699 __le16 command_flags; 614 - #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 615 - #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 616 - #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 617 700 __le16 bad_frame_vsi; 618 - #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 619 - #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 620 701 __le16 default_seid; /* reserved for command */ 621 702 u8 reserved[10]; 622 703 }; ··· 631 722 /* expect an array of these structs in the response buffer */ 632 723 struct i40e_aqc_switch_resource_alloc_element_resp { 633 724 u8 resource_type; 634 - #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 635 - #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 636 - #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 637 - #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 638 - #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 639 - #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 640 - #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 641 - #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 642 - #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 643 - #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 644 - #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 645 - #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 646 - #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 647 - #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 648 - #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 649 - #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 650 - #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 651 - #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 652 - #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 653 725 u8 reserved1; 654 726 __le16 guaranteed; 655 727 __le16 total; ··· 646 756 __le16 flags; 647 757 /* flags used for both fields below */ 648 758 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 649 - #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 650 759 __le16 valid_flags; 651 760 /* The ethertype in switch_tag is dropped on ingress and used 652 761 * internally by the switch. Set this to zero for the default ··· 678 789 */ 679 790 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 680 791 681 - #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 682 792 683 - #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 684 793 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 685 - #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 686 - #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 687 794 688 - #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 689 - #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 690 795 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 691 - #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 692 796 u8 mode; 693 797 u8 rsvd5[5]; 694 798 }; ··· 716 834 __le16 uplink_seid; 717 835 u8 connection_type; 718 836 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 719 - #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 720 - #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 721 837 u8 reserved1; 722 838 u8 vf_id; 723 839 u8 reserved2; 724 840 __le16 vsi_flags; 725 - #define I40E_AQ_VSI_TYPE_SHIFT 0x0 726 - #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 727 841 #define I40E_AQ_VSI_TYPE_VF 0x0 728 842 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 729 843 #define I40E_AQ_VSI_TYPE_PF 0x2 730 - #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 731 - #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 732 844 __le32 addr_high; 733 845 __le32 addr_low; 734 846 }; ··· 746 870 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 747 871 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 748 872 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 749 - #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 750 - #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 751 - #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 752 873 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 753 874 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 754 - #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 755 875 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 756 876 /* switch section */ 757 877 __le16 switch_id; /* 12bit id combined with flags below */ 758 878 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 759 879 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 760 - #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 761 880 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 762 881 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 763 882 u8 sw_reserved[2]; 764 883 /* security section */ 765 884 u8 sec_flags; 766 - #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 767 885 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 768 886 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 769 887 u8 sec_reserved; ··· 769 899 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 770 900 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 771 901 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 772 - #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 773 902 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 774 903 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 775 904 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 776 905 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 777 906 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 778 907 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 779 - #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 780 908 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 781 909 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 782 910 u8 pvlan_reserved[3]; 783 911 /* ingress egress up sections */ 784 912 __le32 ingress_table; /* bitmap, 3 bits per up */ 785 - #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 786 - #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 787 - I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 788 - #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 789 - #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 790 - I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 791 - #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 792 - #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 793 - I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 794 - #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 795 - #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 796 - I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 797 - #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 798 - #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 799 - I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 800 - #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 801 - #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 802 - I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 803 - #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 804 - #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 805 - I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 806 - #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 807 - #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 808 - I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 809 913 __le32 egress_table; /* same defines as for ingress table */ 810 914 /* cascaded PV section */ 811 915 __le16 cas_pv_tag; 812 916 u8 cas_pv_flags; 813 - #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 814 - #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 815 - I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 816 - #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 817 - #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 818 - #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 819 - #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 820 - #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 821 - #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 822 917 u8 cas_pv_reserved; 823 918 /* queue mapping section */ 824 919 __le16 mapping_flags; 825 920 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 826 921 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 827 922 __le16 queue_mapping[16]; 828 - #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 829 - #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 830 923 __le16 tc_mapping[8]; 831 924 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 832 - #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 833 - I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 834 925 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 835 - #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 836 - I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 837 926 /* queueing option section */ 838 927 u8 queueing_opt_flags; 839 - #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 840 - #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 841 928 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 842 - #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 843 - #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 844 929 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 845 930 u8 queueing_opt_reserved[3]; 846 931 /* scheduler section */ ··· 820 995 */ 821 996 struct i40e_aqc_add_update_pv { 822 997 __le16 command_flags; 823 - #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 824 - #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 825 - #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 826 - #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 827 998 __le16 uplink_seid; 828 999 __le16 connected_seid; 829 1000 u8 reserved[10]; ··· 830 1009 struct i40e_aqc_add_update_pv_completion { 831 1010 /* reserved for update; for add also encodes error if rc == ENOSPC */ 832 1011 __le16 pv_seid; 833 - #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 834 - #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 835 - #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 836 - #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 837 1012 u8 reserved[14]; 838 1013 }; 839 1014 ··· 843 1026 __le16 seid; 844 1027 __le16 default_stag; 845 1028 __le16 pv_flags; /* same flags as add_pv */ 846 - #define I40E_AQC_GET_PV_PV_TYPE 0x1 847 - #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 848 - #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 849 1029 u8 reserved[8]; 850 1030 __le16 default_port_seid; 851 1031 }; ··· 855 1041 __le16 downlink_seid; 856 1042 __le16 veb_flags; 857 1043 #define I40E_AQC_ADD_VEB_FLOATING 0x1 858 - #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 859 - #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 860 - I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 861 1044 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 862 1045 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 863 - #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 864 1046 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 865 1047 u8 enable_tcs; 866 1048 u8 reserved[9]; ··· 869 1059 __le16 switch_seid; 870 1060 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 871 1061 __le16 veb_seid; 872 - #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 873 - #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 874 - #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 875 - #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 876 1062 __le16 statistic_index; 877 1063 __le16 vebs_used; 878 1064 __le16 vebs_free; ··· 901 1095 struct i40e_aqc_macvlan { 902 1096 __le16 num_addresses; 903 1097 __le16 seid[3]; 904 - #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 905 - #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 906 - I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 907 1098 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 908 1099 __le32 addr_high; 909 1100 __le32 addr_low; ··· 914 1111 __le16 vlan_tag; 915 1112 __le16 flags; 916 1113 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 917 - #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 918 1114 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 919 - #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 920 1115 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 921 1116 __le16 queue_number; 922 - #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 923 - #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 924 - I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 925 1117 /* response section */ 926 1118 u8 match_method; 927 - #define I40E_AQC_MM_PERFECT_MATCH 0x01 928 - #define I40E_AQC_MM_HASH_MATCH 0x02 929 1119 #define I40E_AQC_MM_ERR_NO_RES 0xFF 930 1120 u8 reserved1[3]; 931 1121 }; ··· 944 1148 __le16 vlan_tag; 945 1149 u8 flags; 946 1150 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 947 - #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 948 1151 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 949 - #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 950 1152 u8 reserved[3]; 951 1153 /* reply section */ 952 1154 u8 error_code; 953 - #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 954 - #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 955 1155 u8 reply_reserved[3]; 956 1156 }; 957 1157 ··· 958 1166 struct i40e_aqc_add_remove_vlan_element_data { 959 1167 __le16 vlan_tag; 960 1168 u8 vlan_flags; 961 - /* flags for add VLAN */ 962 - #define I40E_AQC_ADD_VLAN_LOCAL 0x1 963 - #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 964 - #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 965 - #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 966 - #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 967 - #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 968 - #define I40E_AQC_VLAN_PTYPE_SHIFT 3 969 - #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 970 - #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 971 - #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 972 - #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 973 - #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 974 - /* flags for remove VLAN */ 975 - #define I40E_AQC_REMOVE_VLAN_ALL 0x1 976 1169 u8 reserved; 977 1170 u8 result; 978 - /* flags for add VLAN */ 979 - #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 980 - #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 981 - #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 982 - /* flags for remove VLAN */ 983 - #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 984 - #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 985 1171 u8 reserved1[3]; 986 1172 }; 987 1173 ··· 983 1213 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 984 1214 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 985 1215 __le16 seid; 986 - #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 987 1216 __le16 vlan_tag; 988 - #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 989 1217 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 990 1218 u8 reserved[8]; 991 1219 }; ··· 995 1227 */ 996 1228 struct i40e_aqc_add_tag { 997 1229 __le16 flags; 998 - #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 999 1230 __le16 seid; 1000 - #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1001 - #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1002 - I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1003 1231 __le16 tag; 1004 1232 __le16 queue_number; 1005 1233 u8 reserved[8]; ··· 1016 1252 */ 1017 1253 struct i40e_aqc_remove_tag { 1018 1254 __le16 seid; 1019 - #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1020 - #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1021 - I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1022 1255 __le16 tag; 1023 1256 u8 reserved[12]; 1024 1257 }; ··· 1051 1290 /* Update S/E-Tag (direct 0x0259) */ 1052 1291 struct i40e_aqc_update_tag { 1053 1292 __le16 seid; 1054 - #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1055 - #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1056 - I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1057 1293 __le16 old_tag; 1058 1294 __le16 new_tag; 1059 1295 u8 reserved[10]; ··· 1077 1319 __le16 flags; 1078 1320 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1079 1321 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1080 - #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1081 1322 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1082 - #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1083 1323 __le16 seid; 1084 - #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1085 - #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1086 - I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1087 1324 __le16 queue; 1088 1325 u8 reserved[2]; 1089 1326 }; ··· 1104 1351 u8 num_filters; 1105 1352 u8 reserved; 1106 1353 __le16 seid; 1107 - #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1108 - #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1109 - I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1110 1354 u8 big_buffer_flag; 1111 1355 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1112 1356 u8 reserved2[3]; ··· 1130 1380 } raw_v6; 1131 1381 } ipaddr; 1132 1382 __le16 flags; 1133 - #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1134 - #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1135 - I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1136 1383 /* 0x0000 reserved */ 1137 1384 /* 0x0001 reserved */ 1138 1385 /* 0x0002 reserved */ ··· 1151 1404 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1152 1405 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1153 1406 1154 - #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1155 - #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1156 - #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1157 1407 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1158 1408 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1159 1409 1160 1410 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1161 1411 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1162 - #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1163 - #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1164 1412 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1165 - #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1166 - #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1167 - #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1168 1413 1169 - #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1170 - #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1171 - #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1172 1414 1173 1415 __le32 tenant_id; 1174 1416 u8 reserved[4]; 1175 1417 __le16 queue_number; 1176 - #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1177 - #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1178 - I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1179 1418 u8 reserved2[14]; 1180 1419 /* response section */ 1181 1420 u8 allocation_result; 1182 - #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1183 - #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1184 1421 u8 response_reserved[7]; 1185 1422 }; 1186 1423 ··· 1176 1445 struct i40e_aqc_cloud_filters_element_bb { 1177 1446 struct i40e_aqc_cloud_filters_element_data element; 1178 1447 u16 general_fields[32]; 1179 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1180 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1181 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1182 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1183 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1184 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1185 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1186 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1187 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1188 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1189 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1190 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1191 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1192 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1193 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1194 1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1195 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1196 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1197 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1198 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1199 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1200 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1201 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1202 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1203 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1204 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1205 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1206 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1207 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1208 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1209 - #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1210 1449 }; 1211 1450 1212 1451 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); ··· 1205 1504 1206 1505 struct i40e_aqc_replace_cloud_filters_cmd { 1207 1506 u8 valid_flags; 1208 - #define I40E_AQC_REPLACE_L1_FILTER 0x0 1209 - #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1210 - #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1211 - #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1212 - #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1213 1507 u8 old_filter_type; 1214 1508 u8 new_filter_type; 1215 1509 u8 tr_bit; ··· 1217 1521 1218 1522 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1219 1523 u8 data[32]; 1220 - /* Filter type INPUT codes*/ 1221 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1222 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1223 - 1224 - /* Field Vector offsets */ 1225 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1226 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1227 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1228 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1229 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1230 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1231 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1232 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1233 - /* big FLU */ 1234 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1235 - /* big FLU */ 1236 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1237 - 1238 - #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1239 1524 struct i40e_filter_data filters[8]; 1240 1525 }; 1241 1526 ··· 1233 1556 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1234 1557 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1235 1558 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1236 - #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1237 - #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1238 1559 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1239 1560 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1240 1561 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 ··· 1275 1600 1276 1601 struct i40e_aqc_get_applied_profiles { 1277 1602 u8 flags; 1278 - #define I40E_AQC_GET_DDP_GET_CONF 0x1 1279 - #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1280 1603 u8 rsv[3]; 1281 1604 __le32 reserved; 1282 1605 __le32 addr_high; ··· 1291 1618 struct i40e_aqc_pfc_ignore { 1292 1619 u8 tc_bitmap; 1293 1620 u8 command_flags; /* unused on response */ 1294 - #define I40E_AQC_PFC_IGNORE_SET 0x80 1295 - #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1296 1621 u8 reserved[14]; 1297 1622 }; 1298 1623 ··· 1407 1736 u8 reserved[4]; 1408 1737 u8 tc_valid_bits; 1409 1738 u8 seepage; 1410 - #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1411 1739 u8 tc_strict_priority_flags; 1412 1740 u8 reserved1[17]; 1413 1741 u8 tc_bw_share_credits[8]; ··· 1647 1977 u8 abilities; 1648 1978 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1649 1979 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1650 - #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1651 - #define I40E_AQ_PHY_LINK_ENABLED 0x08 1652 - #define I40E_AQ_PHY_AN_ENABLED 0x10 1653 - #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1654 - #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1655 - #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1656 1980 __le16 eee_capability; 1657 - #define I40E_AQ_EEE_100BASE_TX 0x0002 1658 - #define I40E_AQ_EEE_1000BASE_T 0x0004 1659 - #define I40E_AQ_EEE_10GBASE_T 0x0008 1660 - #define I40E_AQ_EEE_1000BASE_KX 0x0010 1661 - #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1662 - #define I40E_AQ_EEE_10GBASE_KR 0x0040 1663 1981 __le32 eeer_val; 1664 1982 u8 d3_lpan; 1665 - #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1666 1983 u8 phy_type_ext; 1667 1984 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1668 1985 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1669 1986 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1670 1987 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1671 - #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1672 - #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1673 - #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 1674 - #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 1675 1988 u8 fec_cfg_curr_mod_ext_info; 1676 - #define I40E_AQ_ENABLE_FEC_KR 0x01 1677 - #define I40E_AQ_ENABLE_FEC_RS 0x02 1678 1989 #define I40E_AQ_REQUEST_FEC_KR 0x04 1679 1990 #define I40E_AQ_REQUEST_FEC_RS 0x08 1680 1991 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1681 - #define I40E_AQ_FEC 1682 - #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1683 - #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1684 1992 1685 1993 u8 ext_comp_code; 1686 1994 u8 phy_id[4]; ··· 1676 2028 u8 link_speed; 1677 2029 u8 abilities; 1678 2030 /* bits 0-2 use the values from get_phy_abilities_resp */ 1679 - #define I40E_AQ_PHY_ENABLE_LINK 0x08 1680 2031 #define I40E_AQ_PHY_ENABLE_AN 0x10 1681 2032 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1682 2033 __le16 eee_capability; ··· 1703 2056 struct i40e_aq_set_mac_config { 1704 2057 __le16 max_frame_size; 1705 2058 u8 params; 1706 - #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1707 - #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1708 - #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1709 - #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1710 - #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1711 - #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1712 - #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1713 - #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1714 - #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1715 - #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1716 - #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1717 - #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1718 - #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1719 - #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1720 - #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 1721 2059 u8 tx_timer_priority; /* bitmap */ 1722 2060 __le16 tx_timer_value; 1723 2061 __le16 fc_refresh_threshold; ··· 1724 2092 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1725 2093 struct i40e_aqc_get_link_status { 1726 2094 __le16 command_flags; /* only field set on command */ 1727 - #define I40E_AQ_LSE_MASK 0x3 1728 - #define I40E_AQ_LSE_NOP 0x0 1729 2095 #define I40E_AQ_LSE_DISABLE 0x2 1730 2096 #define I40E_AQ_LSE_ENABLE 0x3 1731 2097 /* only response uses this flag */ ··· 1732 2102 u8 link_speed; /* i40e_aq_link_speed */ 1733 2103 u8 link_info; 1734 2104 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1735 - #define I40E_AQ_LINK_UP_FUNCTION 0x01 1736 - #define I40E_AQ_LINK_FAULT 0x02 1737 - #define I40E_AQ_LINK_FAULT_TX 0x04 1738 - #define I40E_AQ_LINK_FAULT_RX 0x08 1739 - #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1740 - #define I40E_AQ_LINK_UP_PORT 0x20 1741 2105 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1742 - #define I40E_AQ_SIGNAL_DETECT 0x80 1743 2106 u8 an_info; 1744 2107 #define I40E_AQ_AN_COMPLETED 0x01 1745 - #define I40E_AQ_LP_AN_ABILITY 0x02 1746 - #define I40E_AQ_PD_FAULT 0x04 1747 - #define I40E_AQ_FEC_EN 0x08 1748 - #define I40E_AQ_PHY_LOW_POWER 0x10 1749 2108 #define I40E_AQ_LINK_PAUSE_TX 0x20 1750 2109 #define I40E_AQ_LINK_PAUSE_RX 0x40 1751 2110 #define I40E_AQ_QUALIFIED_MODULE 0x80 1752 2111 u8 ext_info; 1753 - #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1754 - #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1755 - #define I40E_AQ_LINK_TX_SHIFT 0x02 1756 - #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1757 - #define I40E_AQ_LINK_TX_ACTIVE 0x00 1758 - #define I40E_AQ_LINK_TX_DRAINED 0x01 1759 - #define I40E_AQ_LINK_TX_FLUSHED 0x03 1760 - #define I40E_AQ_LINK_FORCED_40G 0x10 1761 - /* 25G Error Codes */ 1762 - #define I40E_AQ_25G_NO_ERR 0X00 1763 - #define I40E_AQ_25G_NOT_PRESENT 0X01 1764 - #define I40E_AQ_25G_NVM_CRC_ERR 0X02 1765 - #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1766 - #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1767 - #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1768 2112 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1769 2113 /* Since firmware API 1.7 loopback field keeps power class info as well */ 1770 2114 #define I40E_AQ_LOOPBACK_MASK 0x07 1771 - #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 1772 - #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 1773 2115 __le16 max_frame_size; 1774 2116 u8 config; 1775 2117 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 ··· 1751 2149 union { 1752 2150 struct { 1753 2151 u8 power_desc; 1754 - #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1755 - #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1756 - #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1757 - #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1758 - #define I40E_AQ_PWR_CLASS_MASK 0x03 1759 2152 u8 reserved[4]; 1760 2153 }; 1761 2154 struct { ··· 1768 2171 __le16 event_mask; 1769 2172 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1770 2173 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1771 - #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1772 - #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1773 - #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1774 - #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1775 - #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1776 2174 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1777 - #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1778 2175 u8 reserved1[6]; 1779 2176 }; 1780 2177 ··· 1800 2209 /* Set PHY Debug command (0x0622) */ 1801 2210 struct i40e_aqc_set_phy_debug { 1802 2211 u8 command_flags; 1803 - #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1804 - #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1805 - #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1806 - I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1807 - #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1808 - #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1809 - #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1810 2212 /* Disable link manageability on a single port */ 1811 2213 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1812 2214 /* Disable link manageability on all ports */ ··· 1831 2247 /* Get PHY Register command (0x0629) */ 1832 2248 struct i40e_aqc_phy_register_access { 1833 2249 u8 phy_interface; 1834 - #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 1835 2250 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 1836 2251 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 1837 2252 u8 dev_address; ··· 1857 2274 #define I40E_AQ_NVM_LAST_CMD 0x01 1858 2275 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 1859 2276 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 1860 - #define I40E_AQ_NVM_FLASH_ONLY 0x80 1861 2277 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 1862 - #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 1863 2278 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 1864 2279 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 1865 2280 u8 module_pointer; ··· 1872 2291 /* NVM Config Read (indirect 0x0704) */ 1873 2292 struct i40e_aqc_nvm_config_read { 1874 2293 __le16 cmd_flags; 1875 - #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1876 - #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1877 - #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1878 2294 __le16 element_count; 1879 2295 __le16 element_id; /* Feature/field ID */ 1880 2296 __le16 element_id_msw; /* MSWord of field ID */ ··· 1893 2315 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1894 2316 1895 2317 /* Used for 0x0704 as well as for 0x0705 commands */ 1896 - #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1897 - #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1898 - BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1899 - #define I40E_AQ_ANVM_FEATURE 0 1900 - #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 1901 2318 struct i40e_aqc_nvm_config_data_feature { 1902 2319 __le16 feature_id; 1903 - #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1904 - #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1905 - #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1906 2320 __le16 feature_options; 1907 2321 __le16 feature_selection; 1908 2322 }; ··· 1914 2344 * no command data struct used 1915 2345 */ 1916 2346 struct i40e_aqc_nvm_oem_post_update { 1917 - #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1918 2347 u8 sel_data; 1919 2348 u8 reserved[7]; 1920 2349 }; ··· 1935 2366 */ 1936 2367 struct i40e_aqc_thermal_sensor { 1937 2368 u8 sensor_action; 1938 - #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 1939 - #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 1940 - #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 1941 2369 u8 reserved[7]; 1942 2370 __le32 addr_high; 1943 2371 __le32 addr_low; ··· 1987 2421 */ 1988 2422 struct i40e_aqc_alternate_write_done { 1989 2423 __le16 cmd_flags; 1990 - #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1991 - #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1992 - #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1993 - #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1994 2424 u8 reserved[14]; 1995 2425 }; 1996 2426 ··· 1995 2433 /* Set OEM mode (direct 0x0905) */ 1996 2434 struct i40e_aqc_alternate_set_mode { 1997 2435 __le32 mode; 1998 - #define I40E_AQ_ALTERNATE_MODE_NONE 0 1999 - #define I40E_AQ_ALTERNATE_MODE_OEM 1 2000 2436 u8 reserved[12]; 2001 2437 }; 2002 2438 ··· 2020 2460 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2021 2461 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2022 2462 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2023 - #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2024 2463 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2025 2464 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2026 2465 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2027 - #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2028 - #define I40E_AQ_LLDP_TX_SHIFT 0x4 2029 - #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2030 2466 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2031 2467 __le16 local_len; 2032 2468 __le16 remote_len; ··· 2038 2482 */ 2039 2483 struct i40e_aqc_lldp_update_mib { 2040 2484 u8 command; 2041 - #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2042 2485 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2043 2486 u8 reserved[7]; 2044 2487 __le32 addr_high; ··· 2076 2521 /* Stop LLDP (direct 0x0A05) */ 2077 2522 struct i40e_aqc_lldp_stop { 2078 2523 u8 command; 2079 - #define I40E_AQ_LLDP_AGENT_STOP 0x0 2080 2524 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2081 2525 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2082 2526 u8 reserved[15]; ··· 2181 2627 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2182 2628 */ 2183 2629 struct i40e_aqc_lldp_set_local_mib { 2184 - #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2185 - #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2186 - #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2187 - #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2188 - #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2189 - BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2190 - #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2191 2630 u8 type; 2192 2631 u8 reserved0; 2193 2632 __le16 length; ··· 2195 2648 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2196 2649 */ 2197 2650 struct i40e_aqc_lldp_stop_start_specific_agent { 2198 - #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2199 - #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2200 - BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2201 2651 u8 command; 2202 2652 u8 reserved[15]; 2203 2653 }; ··· 2204 2660 /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2205 2661 struct i40e_aqc_lldp_restore { 2206 2662 u8 command; 2207 - #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2208 2663 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2209 2664 u8 reserved[15]; 2210 2665 }; ··· 2217 2674 u8 protocol_type; 2218 2675 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2219 2676 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2220 - #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2221 - #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2222 2677 u8 reserved1[10]; 2223 2678 }; 2224 2679 ··· 2226 2685 __le16 udp_port; 2227 2686 u8 filter_entry_index; 2228 2687 u8 multiple_pfs; 2229 - #define I40E_AQC_SINGLE_PF 0x0 2230 - #define I40E_AQC_MULTIPLE_PFS 0x1 2231 2688 u8 total_filters; 2232 2689 u8 reserved[11]; 2233 2690 }; ··· 2298 2759 u8 key1_len; /* 0 to 15 */ 2299 2760 u8 key2_len; /* 0 to 15 */ 2300 2761 u8 flags; 2301 - #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2302 - /* response flags */ 2303 - #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2304 - #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2305 - #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2306 2762 u8 network_key_index; 2307 - #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2308 - #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2309 - #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2310 - #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2311 2763 u8 reserved[10]; 2312 2764 }; 2313 2765 ··· 2307 2777 /* OEM mode commands (direct 0xFE0x) */ 2308 2778 struct i40e_aqc_oem_param_change { 2309 2779 __le32 param_type; 2310 - #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2311 - #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2312 - #define I40E_AQ_OEM_PARAM_MAC 2 2313 2780 __le32 param_value1; 2314 2781 __le16 param_value2; 2315 2782 u8 reserved[6]; ··· 2316 2789 2317 2790 struct i40e_aqc_oem_state_change { 2318 2791 __le32 state; 2319 - #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2320 - #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2321 2792 u8 reserved[12]; 2322 2793 }; 2323 2794 ··· 2351 2826 2352 2827 struct i40e_acq_set_test_mode { 2353 2828 u8 mode; 2354 - #define I40E_AQ_TEST_PARTIAL 0 2355 - #define I40E_AQ_TEST_FULL 1 2356 - #define I40E_AQ_TEST_NVM 2 2357 2829 u8 reserved[3]; 2358 2830 u8 command; 2359 - #define I40E_AQ_TEST_OPEN 0 2360 - #define I40E_AQ_TEST_CLOSE 1 2361 - #define I40E_AQ_TEST_INC 2 2362 2831 u8 reserved2[3]; 2363 2832 __le32 address_high; 2364 2833 __le32 address_low; ··· 2393 2874 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2394 2875 2395 2876 /* dump internal data (0xFF08, indirect) */ 2396 - 2397 - #define I40E_AQ_CLUSTER_ID_AUX 0 2398 - #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2399 - #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2400 - #define I40E_AQ_CLUSTER_ID_HMC 3 2401 - #define I40E_AQ_CLUSTER_ID_MAC0 4 2402 - #define I40E_AQ_CLUSTER_ID_MAC1 5 2403 - #define I40E_AQ_CLUSTER_ID_MAC2 6 2404 - #define I40E_AQ_CLUSTER_ID_MAC3 7 2405 - #define I40E_AQ_CLUSTER_ID_DCB 8 2406 - #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2407 - #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2408 - #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2409 - 2410 2877 struct i40e_aqc_debug_dump_internals { 2411 2878 u8 cluster_id; 2412 2879 u8 table_id;
-4
drivers/net/ethernet/intel/i40e/i40e_common.c
··· 1455 1455 return gpio_val; 1456 1456 } 1457 1457 1458 - #define I40E_COMBINED_ACTIVITY 0xA 1459 - #define I40E_FILTER_ACTIVITY 0xE 1460 - #define I40E_LINK_ACTIVITY 0xC 1461 - #define I40E_MAC_ACTIVITY 0xD 1462 1458 #define I40E_FW_LED BIT(4) 1463 1459 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 1464 1460 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
-5
drivers/net/ethernet/intel/i40e/i40e_dcb.h
··· 6 6 7 7 #include "i40e_type.h" 8 8 9 - #define I40E_DCBX_STATUS_NOT_STARTED 0 10 9 #define I40E_DCBX_STATUS_IN_PROGRESS 1 11 10 #define I40E_DCBX_STATUS_DONE 2 12 - #define I40E_DCBX_STATUS_MULTIPLE_PEERS 3 13 11 #define I40E_DCBX_STATUS_DISABLED 7 14 12 15 13 #define I40E_TLV_TYPE_END 0 ··· 22 24 #define I40E_CEE_DCBX_OUI 0x001b21 23 25 #define I40E_CEE_DCBX_TYPE 2 24 26 25 - #define I40E_CEE_SUBTYPE_CTRL 1 26 27 #define I40E_CEE_SUBTYPE_PG_CFG 2 27 28 #define I40E_CEE_SUBTYPE_PFC_CFG 3 28 29 #define I40E_CEE_SUBTYPE_APP_PRI 4 ··· 102 105 struct i40e_cee_feat_tlv { 103 106 struct i40e_cee_tlv_hdr hdr; 104 107 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */ 105 - #define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80 106 108 #define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40 107 - #define I40E_CEE_FEAT_TLV_ERR_MASK 0x20 108 109 u8 subtype; 109 110 u8 tlvinfo[1]; 110 111 };
-1
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
··· 688 688 i40e_dbg_dump_vf(pf, i); 689 689 } 690 690 691 - #define I40E_MAX_DEBUG_OUT_BUFFER (4096*4) 692 691 /** 693 692 * i40e_dbg_command_write - write into command datum 694 693 * @filp: the opened file
-3
drivers/net/ethernet/intel/i40e/i40e_devids.h
··· 32 32 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2 33 33 #define I40E_DEV_ID_SFP_I_X722 0x37D3 34 34 35 - #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \ 36 - (d) == I40E_DEV_ID_QSFP_B || \ 37 - (d) == I40E_DEV_ID_QSFP_C) 38 35 39 36 #endif /* _I40E_DEVIDS_H_ */
-1
drivers/net/ethernet/intel/i40e/i40e_hmc.h
··· 14 14 #define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */ 15 15 #define I40E_HMC_PAGED_BP_SIZE 4096 16 16 #define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096 17 - #define I40E_FIRST_VF_FPM_ID 16 18 17 19 18 struct i40e_hmc_obj_info { 20 19 u64 base; /* base addr in FPM */
+1 -9
drivers/net/ethernet/intel/i40e/i40e_main.c
··· 6492 6492 return err; 6493 6493 } 6494 6494 #endif /* CONFIG_I40E_DCB */ 6495 - #define SPEED_SIZE 14 6496 - #define FC_SIZE 8 6495 + 6497 6496 /** 6498 6497 * i40e_print_link_message - print link up or down 6499 6498 * @vsi: the VSI for which link needs a message ··· 8948 8949 { 8949 8950 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; 8950 8951 } 8951 - 8952 - /* We can see up to 256 filter programming desc in transit if the filters are 8953 - * being applied really fast; before we see the first 8954 - * filter miss error on Rx queue 0. Accumulating enough error messages before 8955 - * reacting will make sure we don't cause flush too often. 8956 - */ 8957 - #define I40E_MAX_FD_PROGRAM_ERROR 256 8958 8952 8959 8953 /** 8960 8954 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
-1
drivers/net/ethernet/intel/i40e/i40e_osdep.h
··· 26 26 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) 27 27 #define rd32(a, reg) readl((a)->hw_addr + (reg)) 28 28 29 - #define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) 30 29 #define rd64(a, reg) readq((a)->hw_addr + (reg)) 31 30 #define i40e_flush(a) readl((a)->hw_addr + I40E_GLGEN_STAT) 32 31
-4656
drivers/net/ethernet/intel/i40e/i40e_register.h
··· 4 4 #ifndef _I40E_REGISTER_H_ 5 5 #define _I40E_REGISTER_H_ 6 6 7 - #define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */ 8 - #define I40E_GL_ARQBAH_ARQBAH_SHIFT 0 9 - #define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT) 10 - #define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */ 11 - #define I40E_GL_ARQBAL_ARQBAL_SHIFT 0 12 - #define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT) 13 - #define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */ 14 - #define I40E_GL_ARQH_ARQH_SHIFT 0 15 - #define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT) 16 - #define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */ 17 - #define I40E_GL_ARQT_ARQT_SHIFT 0 18 - #define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT) 19 - #define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */ 20 - #define I40E_GL_ATQBAH_ATQBAH_SHIFT 0 21 - #define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT) 22 - #define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */ 23 - #define I40E_GL_ATQBAL_ATQBAL_SHIFT 0 24 - #define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT) 25 - #define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */ 26 - #define I40E_GL_ATQH_ATQH_SHIFT 0 27 - #define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT) 28 - #define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */ 29 - #define I40E_GL_ATQLEN_ATQLEN_SHIFT 0 30 - #define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT) 31 - #define I40E_GL_ATQLEN_ATQVFE_SHIFT 28 32 - #define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT) 33 - #define I40E_GL_ATQLEN_ATQOVFL_SHIFT 29 34 - #define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT) 35 7 #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30 36 8 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT) 37 - #define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31 38 - #define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT) 39 - #define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */ 40 - #define I40E_GL_ATQT_ATQT_SHIFT 0 41 - #define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT) 42 9 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 43 - #define I40E_PF_ARQBAH_ARQBAH_SHIFT 0 44 - #define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT) 45 10 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 46 - #define I40E_PF_ARQBAL_ARQBAL_SHIFT 0 47 - #define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT) 48 11 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 49 12 #define I40E_PF_ARQH_ARQH_SHIFT 0 50 13 #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT) 51 14 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 52 - #define I40E_PF_ARQLEN_ARQLEN_SHIFT 0 53 - #define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT) 54 15 #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 55 16 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 56 17 #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 ··· 21 60 #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 22 61 #define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) 23 62 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 24 - #define I40E_PF_ARQT_ARQT_SHIFT 0 25 - #define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT) 26 63 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 27 - #define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 28 - #define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT) 29 64 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 30 - #define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 31 - #define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT) 32 65 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 33 - #define I40E_PF_ATQH_ATQH_SHIFT 0 34 - #define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT) 35 66 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 36 - #define I40E_PF_ATQLEN_ATQLEN_SHIFT 0 37 - #define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT) 38 67 #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 39 68 #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 40 69 #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 ··· 34 83 #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 35 84 #define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) 36 85 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 37 - #define I40E_PF_ATQT_ATQT_SHIFT 0 38 - #define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT) 39 - #define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 40 - #define I40E_VF_ARQBAH_MAX_INDEX 127 41 - #define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 42 - #define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT) 43 - #define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 44 - #define I40E_VF_ARQBAL_MAX_INDEX 127 45 - #define I40E_VF_ARQBAL_ARQBAL_SHIFT 0 46 - #define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT) 47 - #define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 48 - #define I40E_VF_ARQH_MAX_INDEX 127 49 - #define I40E_VF_ARQH_ARQH_SHIFT 0 50 - #define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT) 51 - #define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 52 - #define I40E_VF_ARQLEN_MAX_INDEX 127 53 - #define I40E_VF_ARQLEN_ARQLEN_SHIFT 0 54 - #define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT) 55 - #define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 56 - #define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT) 57 - #define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 58 - #define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT) 59 - #define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 60 - #define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT) 61 - #define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 62 - #define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT) 63 - #define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 64 - #define I40E_VF_ARQT_MAX_INDEX 127 65 - #define I40E_VF_ARQT_ARQT_SHIFT 0 66 - #define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT) 67 - #define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 68 - #define I40E_VF_ATQBAH_MAX_INDEX 127 69 - #define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 70 - #define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT) 71 - #define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 72 - #define I40E_VF_ATQBAL_MAX_INDEX 127 73 - #define I40E_VF_ATQBAL_ATQBAL_SHIFT 0 74 - #define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT) 75 - #define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 76 - #define I40E_VF_ATQH_MAX_INDEX 127 77 - #define I40E_VF_ATQH_ATQH_SHIFT 0 78 - #define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT) 79 - #define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 80 - #define I40E_VF_ATQLEN_MAX_INDEX 127 81 - #define I40E_VF_ATQLEN_ATQLEN_SHIFT 0 82 - #define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT) 83 - #define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 84 - #define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT) 85 - #define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 86 - #define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT) 87 - #define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 88 - #define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT) 89 - #define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 90 - #define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT) 91 - #define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 92 - #define I40E_VF_ATQT_MAX_INDEX 127 93 - #define I40E_VF_ATQT_ATQT_SHIFT 0 94 - #define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT) 95 - #define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 96 - #define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 97 - #define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 98 - #define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ 99 - #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0 100 - #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT) 101 - #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4 102 - #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT) 103 - #define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8 104 - #define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT) 105 - #define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */ 106 - #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0 107 - #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT) 108 - #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4 109 - #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT) 110 - #define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8 111 - #define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT) 112 - #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16 113 - #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT) 114 - #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24 115 - #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT) 116 - #define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */ 117 - #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0 118 - #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT) 119 - #define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12 120 - #define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT) 121 - #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15 122 - #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT) 123 - #define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17 124 - #define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT) 125 - #define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */ 126 - #define I40E_PFCM_LANCTXDATA_MAX_INDEX 3 127 - #define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0 128 - #define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT) 129 - #define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */ 130 - #define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0 131 - #define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT) 132 - #define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1 133 - #define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT) 134 - #define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 135 - #define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127 136 - #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0 137 - #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT) 138 - #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4 139 - #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT) 140 - #define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8 141 - #define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT) 142 - #define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 143 - #define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127 144 - #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0 145 - #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT) 146 - #define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 147 - #define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) 148 - #define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 149 - #define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) 150 - #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 151 - #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) 152 - #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 153 - #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) 154 - #define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ 155 - #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 156 - #define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT) 157 - #define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */ 158 - #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 159 - #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) 160 - #define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 161 - #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 162 - #define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT) 163 - #define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */ 164 - #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0 165 - #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT) 166 - #define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */ 167 - #define I40E_PRTDCB_FCTTVN_MAX_INDEX 3 168 - #define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0 169 - #define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT) 170 - #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16 171 - #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT) 172 86 #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 173 - #define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0 174 - #define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT) 175 - #define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 176 - #define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT) 177 - #define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6 178 - #define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT) 179 - #define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9 180 - #define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT) 181 87 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 182 88 #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT) 183 89 #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 184 90 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 185 91 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 186 - #define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */ 187 - #define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 188 - #define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT) 189 - #define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 190 - #define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT) 191 - #define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 192 - #define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT) 193 - #define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 194 - #define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT) 195 - #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 196 - #define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT) 197 - #define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */ 198 - #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 199 - #define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) 200 - #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 201 - #define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) 202 - #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 203 - #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) 204 - #define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 205 - #define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 206 - #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 207 - #define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 208 - #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 209 - #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 210 - #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 211 - #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 212 - #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 213 - #define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) 214 - #define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 215 - #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 216 - #define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 217 - #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 218 - #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 219 - #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 220 - #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 221 - #define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ 222 - #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 223 - #define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT) 224 - #define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */ 225 - #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 226 - #define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) 227 - #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 228 - #define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) 229 - #define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 230 - #define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) 231 - #define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 232 - #define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) 233 - #define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 234 - #define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 235 - #define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 236 - #define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 237 - #define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 238 - #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 239 - #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 240 - #define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) 241 - #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 242 - #define I40E_PRTDCB_RUPTQ_MAX_INDEX 7 243 - #define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 244 - #define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT) 245 - #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 246 - #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 247 - #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 248 - #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 249 - #define I40E_PRTDCB_TCMSTC_MAX_INDEX 7 250 - #define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0 251 - #define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT) 252 - #define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ 253 - #define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 254 - #define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT) 255 - #define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 256 - #define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT) 257 - #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 258 - #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) 259 - #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 260 - #define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 261 - #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 262 - #define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT) 263 - #define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */ 264 - #define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 265 - #define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT) 266 - #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 267 - #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) 268 - #define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */ 269 - #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 270 - #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) 271 - #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 272 - #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) 273 - #define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */ 274 - #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 275 - #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) 276 - #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 277 - #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) 278 - #define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */ 279 - #define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 280 - #define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT) 281 - #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 282 - #define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT) 283 - #define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 284 - #define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT) 285 - #define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 286 - #define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT) 287 - #define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 288 - #define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT) 289 - #define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 290 - #define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT) 291 - #define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 292 - #define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT) 293 - #define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 294 - #define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT) 295 - #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 296 - #define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT) 297 - #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ 298 - #define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 299 - #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 300 - #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) 301 - #define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */ 302 - #define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0 303 - #define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT) 304 - #define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4 305 - #define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT) 306 - #define I40E_GLFCOE_RCTL_ICRC_SHIFT 5 307 - #define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT) 308 - #define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16 309 - #define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 310 92 #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 311 - #define I40E_GL_FWSTS_FWS0B_SHIFT 0 312 - #define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) 313 - #define I40E_GL_FWSTS_FWRI_SHIFT 9 314 - #define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT) 315 93 #define I40E_GL_FWSTS_FWS1B_SHIFT 16 316 94 #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) 317 95 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) ··· 49 369 #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 50 370 #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 51 371 #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) 52 - #define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 53 - #define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 54 - #define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 55 - #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 56 - #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 57 - #define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 58 - #define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 59 - #define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 60 - #define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT) 61 - #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16 62 - #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT) 63 - #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20 64 - #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT) 65 372 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 66 373 #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 67 374 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 68 375 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 69 376 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 70 377 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 71 - #define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 72 - #define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 73 - #define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 74 - #define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 75 - #define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 76 - #define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 77 378 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 78 379 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 79 - #define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10 80 - #define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT) 81 380 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 82 - #define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT) 83 381 #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 84 382 #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 85 - #define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 86 - #define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) 87 - #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 88 - #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 89 - #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 90 - #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 91 - #define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26 92 - #define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT) 93 - #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 94 - #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 95 - #define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) 96 - #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 97 - #define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 98 - #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 99 - #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 100 - #define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */ 101 - #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0 102 - #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT) 103 - #define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */ 104 - #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0 105 - #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT) 106 - #define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 107 - #define I40E_GLGEN_I2CCMD_MAX_INDEX 3 108 - #define I40E_GLGEN_I2CCMD_DATA_SHIFT 0 109 - #define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT) 110 - #define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16 111 - #define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT) 112 - #define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24 113 - #define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT) 114 - #define I40E_GLGEN_I2CCMD_OP_SHIFT 27 115 - #define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT) 116 - #define I40E_GLGEN_I2CCMD_RESET_SHIFT 28 117 - #define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT) 118 - #define I40E_GLGEN_I2CCMD_R_SHIFT 29 119 - #define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT) 120 - #define I40E_GLGEN_I2CCMD_E_SHIFT 31 121 - #define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT) 122 - #define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 123 - #define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3 124 - #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0 125 - #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT) 126 - #define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5 127 - #define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT) 128 - #define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8 129 - #define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT) 130 - #define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9 131 - #define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT) 132 - #define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10 133 - #define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT) 134 - #define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11 135 - #define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT) 136 - #define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12 137 - #define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT) 138 - #define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13 139 - #define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT) 140 - #define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14 141 - #define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT) 142 - #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15 143 - #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT) 144 - #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31 145 - #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT) 146 - #define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */ 147 - #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0 148 - #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) 149 - #define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 150 - #define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 151 - #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 152 - #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) 153 - #define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 154 - #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) 155 - #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 156 - #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) 157 - #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29 158 - #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT) 159 383 #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 160 - #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 161 - #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 162 - #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) 163 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 164 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) 165 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 166 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) 167 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10 168 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT) 169 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15 170 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT) 171 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20 172 - #define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT) 173 - #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25 174 - #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT) 175 - #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31 176 - #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT) 177 384 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 178 - #define I40E_GLGEN_MSCA_MAX_INDEX 3 179 385 #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 180 - #define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT) 181 386 #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 182 - #define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT) 183 387 #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 184 - #define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT) 185 388 #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 186 - #define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT) 187 389 #define I40E_GLGEN_MSCA_STCODE_SHIFT 28 188 - #define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT) 189 390 #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 190 391 #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 191 392 #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 192 393 #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 193 394 #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 194 - #define I40E_GLGEN_MSRWD_MAX_INDEX 3 195 395 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 196 - #define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 197 396 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 198 397 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 199 - #define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 200 - #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 201 - #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 202 - #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 203 - #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 204 398 #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 205 399 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 206 400 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 207 401 #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 208 402 #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 209 - #define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4 210 - #define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT) 211 - #define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6 212 - #define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT) 213 - #define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8 214 - #define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) 215 - #define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 216 - #define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) 217 403 #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 218 404 #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 219 405 #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 220 - #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 221 - #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) 222 406 #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 223 407 #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 224 408 #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 225 409 #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 226 410 #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 227 - #define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 228 - #define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT) 229 411 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 230 - #define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0 231 - #define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT) 232 - #define I40E_GLGEN_STAT_DCBEN_SHIFT 2 233 - #define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT) 234 - #define I40E_GLGEN_STAT_VTEN_SHIFT 3 235 - #define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT) 236 - #define I40E_GLGEN_STAT_FCOEN_SHIFT 4 237 - #define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT) 238 - #define I40E_GLGEN_STAT_EVBEN_SHIFT 5 239 - #define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT) 240 - #define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6 241 - #define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT) 242 412 #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 243 - #define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3 244 - #define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0 245 - #define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT) 246 413 #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 247 - #define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0 248 - #define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT) 249 414 #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 250 415 #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 251 416 #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT) 252 - #define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */ 253 - #define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0 254 - #define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT) 255 417 #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 256 418 #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 257 419 #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 258 - #define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */ 259 - #define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0 260 - #define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT) 261 - #define I40E_PFGEN_STATE_PFFCEN_SHIFT 1 262 - #define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT) 263 - #define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2 264 - #define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT) 265 - #define I40E_PFGEN_STATE_PFSCEN_SHIFT 3 266 - #define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT) 267 420 #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 268 421 #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 269 422 #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 270 - #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1 271 - #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT) 272 - #define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2 273 - #define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT) 274 - #define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */ 275 - #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0 276 - #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT) 277 423 #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 278 - #define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0 279 - #define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT) 280 - #define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1 281 - #define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT) 282 424 #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 283 - #define I40E_VFGEN_RSTAT1_MAX_INDEX 127 284 - #define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0 285 - #define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT) 286 425 #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 287 - #define I40E_VPGEN_VFRSTAT_MAX_INDEX 127 288 426 #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 289 427 #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 290 428 #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 291 - #define I40E_VPGEN_VFRTRIG_MAX_INDEX 127 292 429 #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 293 430 #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 294 - #define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 295 - #define I40E_VSIGEN_RSTAT_MAX_INDEX 383 296 - #define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0 297 - #define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT) 298 - #define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 299 - #define I40E_VSIGEN_RTRIG_MAX_INDEX 383 300 - #define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0 301 - #define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT) 302 431 #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 303 - #define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15 304 432 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 305 433 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 306 434 #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 307 - #define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15 308 - #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0 309 - #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT) 310 435 #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 311 - #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0 312 - #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT) 313 436 #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 314 - #define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15 315 437 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 316 438 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 317 439 #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 318 - #define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15 319 - #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0 320 - #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT) 321 440 #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 322 441 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 323 442 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 324 443 #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 325 - #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0 326 - #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT) 327 444 #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 328 - #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0 329 - #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT) 330 - #define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 331 - #define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15 332 - #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0 333 - #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT) 334 - #define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 335 - #define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15 336 - #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0 337 - #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT) 338 - #define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29 339 - #define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT) 340 - #define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */ 341 - #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0 342 - #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT) 343 - #define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */ 344 - #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0 345 - #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT) 346 - #define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 347 - #define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15 348 - #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0 349 - #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT) 350 - #define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 351 - #define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15 352 - #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0 353 - #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT) 354 - #define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */ 355 - #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0 356 - #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT) 357 - #define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */ 358 - #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0 359 - #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT) 360 445 #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 361 - #define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0 362 - #define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT) 363 446 #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 364 - #define I40E_GLHMC_LANRXBASE_MAX_INDEX 15 365 447 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 366 448 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 367 449 #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 368 - #define I40E_GLHMC_LANRXCNT_MAX_INDEX 15 369 - #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0 370 - #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT) 371 450 #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 372 - #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0 373 - #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT) 374 451 #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 375 - #define I40E_GLHMC_LANTXBASE_MAX_INDEX 15 376 452 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 377 453 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 378 - #define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24 379 - #define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT) 380 454 #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 381 - #define I40E_GLHMC_LANTXCNT_MAX_INDEX 15 382 - #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0 383 - #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT) 384 455 #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 385 - #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0 386 - #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT) 387 - #define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 388 - #define I40E_GLHMC_PFASSIGN_MAX_INDEX 15 389 - #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0 390 - #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT) 391 - #define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 392 - #define I40E_GLHMC_SDPART_MAX_INDEX 15 393 - #define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0 394 - #define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT) 395 - #define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16 396 - #define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT) 397 456 #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 398 - #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0 399 - #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT) 400 457 #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 401 - #define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0 402 - #define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT) 403 - #define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7 404 - #define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT) 405 - #define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8 406 - #define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT) 407 - #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16 408 - #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT) 409 - #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31 410 - #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT) 411 458 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 412 459 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 413 - #define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT) 414 460 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 415 - #define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT) 416 461 #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 417 - #define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0 418 - #define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT) 419 462 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 420 - #define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT) 421 463 #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 422 - #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0 423 - #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT) 424 464 #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 425 465 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 426 - #define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT) 427 466 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 428 - #define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) 429 467 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 430 - #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) 431 - #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12 432 - #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) 433 - #define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */ 434 - #define I40E_GL_GP_FUSE_MAX_INDEX 28 435 - #define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0 436 - #define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT) 437 - #define I40E_GL_UFUSE 0x00094008 /* Reset: POR */ 438 - #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1 439 - #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT) 440 - #define I40E_GL_UFUSE_NIC_ID_SHIFT 2 441 - #define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT) 442 - #define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10 443 - #define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT) 444 - #define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11 445 - #define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT) 446 - #define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */ 447 - #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 448 - #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT) 449 - #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 450 - #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT) 451 - #define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 452 - #define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT) 453 - #define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 454 - #define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT) 455 - #define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 456 - #define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT) 457 - #define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 458 - #define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT) 459 - #define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 460 - #define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT) 461 - #define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 462 - #define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT) 463 - #define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 464 - #define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT) 465 - #define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 466 - #define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT) 467 - #define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 468 - #define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT) 469 - #define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 470 - #define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT) 471 - #define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 472 - #define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT) 473 - #define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 474 - #define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT) 475 - #define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 476 - #define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT) 477 - #define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 478 - #define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT) 479 - #define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 480 - #define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT) 481 - #define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 482 - #define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT) 483 - #define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 484 - #define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT) 485 - #define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 486 - #define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT) 487 - #define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 488 - #define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT) 489 - #define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 490 - #define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT) 491 - #define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 492 - #define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT) 493 - #define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 494 - #define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT) 495 - #define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 496 - #define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT) 497 - #define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 498 - #define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT) 499 - #define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 500 - #define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT) 501 - #define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 502 - #define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT) 503 - #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 504 - #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT) 505 - #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 506 - #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT) 507 468 #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 508 - #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0 509 - #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT) 510 469 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 511 470 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 512 471 #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 513 472 #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 514 - #define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT) 515 473 #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 516 - #define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT) 517 - #define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13 518 - #define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT) 519 474 #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 520 475 #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 521 - #define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31 522 - #define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT) 523 476 #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 524 - #define I40E_PFINT_CEQCTL_MAX_INDEX 511 525 477 #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 526 - #define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT) 527 478 #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 528 - #define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT) 529 - #define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13 530 - #define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT) 531 479 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 532 - #define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) 533 - #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 534 - #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) 535 480 #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 536 481 #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 537 - #define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 538 - #define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT) 539 482 #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 540 - #define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT 0 541 - #define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT) 542 483 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1 543 484 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT) 544 - #define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT 2 545 - #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT) 546 485 #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 547 486 #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 548 487 #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) ··· 171 872 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 172 873 #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 173 874 #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 174 - #define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5 175 - #define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT) 176 875 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 177 876 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 178 877 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 ··· 178 881 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 179 882 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 180 883 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 181 - #define I40E_PFINT_DYN_CTLN_MAX_INDEX 511 182 884 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 183 885 #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 184 886 #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 ··· 187 891 #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 188 892 #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 189 893 #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 190 - #define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) 191 894 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 192 895 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 193 - #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 194 - #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 195 - #define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 196 - #define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT) 197 - #define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */ 198 - #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 199 - #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT) 200 - #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 201 - #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT) 202 - #define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 203 - #define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT) 204 - #define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 205 - #define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT) 206 - #define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 207 - #define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT) 208 - #define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 209 - #define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT) 210 - #define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 211 - #define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT) 212 - #define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 213 - #define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT) 214 - #define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 215 - #define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT) 216 - #define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 217 - #define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT) 218 - #define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 219 - #define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT) 220 - #define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 221 - #define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT) 222 - #define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 223 - #define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT) 224 - #define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 225 - #define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT) 226 - #define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 227 - #define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT) 228 - #define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 229 - #define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT) 230 - #define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 231 - #define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT) 232 - #define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 233 - #define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT) 234 - #define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 235 - #define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT) 236 - #define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 237 - #define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT) 238 - #define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 239 - #define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT) 240 - #define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 241 - #define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT) 242 - #define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 243 - #define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT) 244 - #define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 245 - #define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT) 246 - #define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 247 - #define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT) 248 - #define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 249 - #define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT) 250 - #define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 251 - #define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT) 252 - #define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 253 - #define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT) 254 - #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 255 - #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT) 256 - #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 257 - #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT) 258 896 #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 259 897 #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 260 898 #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT) 261 899 #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 262 900 #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT) 263 - #define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2 264 - #define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT) 265 - #define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3 266 - #define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT) 267 - #define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4 268 - #define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT) 269 - #define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5 270 - #define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT) 271 - #define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6 272 - #define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT) 273 - #define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7 274 - #define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT) 275 - #define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8 276 - #define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT) 277 901 #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 278 902 #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT) 279 903 #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 ··· 202 986 #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT) 203 987 #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 204 988 #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 205 - #define I40E_PFINT_ICR0_GPIO_SHIFT 22 206 - #define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT) 207 989 #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 208 990 #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT) 209 - #define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24 210 - #define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT) 211 - #define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 212 - #define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 213 991 #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 214 992 #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT) 215 993 #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 ··· 227 1017 #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 228 1018 #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 229 1019 #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 230 - #define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24 231 - #define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT) 232 - #define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 233 - #define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 234 1020 #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 235 1021 #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 236 1022 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 ··· 235 1029 #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 236 1030 #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 237 1031 #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 238 - #define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31 239 - #define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT) 240 1032 #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 241 - #define I40E_PFINT_ITR0_MAX_INDEX 2 242 - #define I40E_PFINT_ITR0_INTERVAL_SHIFT 0 243 - #define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT) 244 1033 #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 245 - #define I40E_PFINT_ITRN_MAX_INDEX 2 246 - #define I40E_PFINT_ITRN_INTERVAL_SHIFT 0 247 - #define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT) 248 1034 #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 249 1035 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 250 - #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) 251 - #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 252 - #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 253 1036 #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 254 - #define I40E_PFINT_LNKLSTN_MAX_INDEX 511 255 1037 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 256 1038 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 257 1039 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 258 - #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 259 - #define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */ 260 - #define I40E_PFINT_RATE0_INTERVAL_SHIFT 0 261 - #define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT) 262 - #define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 263 - #define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT) 264 1040 #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 265 - #define I40E_PFINT_RATEN_MAX_INDEX 511 266 - #define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 267 - #define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT) 268 - #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 269 - #define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT) 270 1041 #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 271 - #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 272 - #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 273 1042 #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 274 - #define I40E_QINT_RQCTL_MAX_INDEX 1535 275 1043 #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 276 1044 #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 277 1045 #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 ··· 255 1075 #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 256 1076 #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 257 1077 #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 258 - #define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) 259 1078 #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 260 1079 #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 261 1080 #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 262 1081 #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT) 263 1082 #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 264 - #define I40E_QINT_TQCTL_MAX_INDEX 1535 265 1083 #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 266 1084 #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 267 1085 #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 ··· 269 1091 #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 270 1092 #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 271 1093 #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 272 - #define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) 273 1094 #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 274 1095 #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 275 1096 #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 276 1097 #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT) 277 1098 #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 278 - #define I40E_VFINT_DYN_CTL0_MAX_INDEX 127 279 - #define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0 280 - #define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT) 281 - #define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1 282 - #define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT) 283 - #define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 284 - #define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 285 - #define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3 286 - #define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) 287 - #define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5 288 - #define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT) 289 - #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 290 - #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 291 - #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 292 - #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 293 - #define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 294 - #define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT) 295 1099 #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 296 - #define I40E_VFINT_DYN_CTLN_MAX_INDEX 511 297 - #define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0 298 - #define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT) 299 1100 #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 300 1101 #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 301 - #define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 302 - #define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 303 - #define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3 304 - #define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) 305 - #define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5 306 - #define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT) 307 - #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 308 - #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 309 - #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 310 - #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 311 - #define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 312 - #define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT) 313 - #define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 314 - #define I40E_VFINT_ICR0_MAX_INDEX 127 315 - #define I40E_VFINT_ICR0_INTEVENT_SHIFT 0 316 - #define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT) 317 - #define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1 318 - #define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT) 319 - #define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2 320 - #define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT) 321 - #define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3 322 - #define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT) 323 - #define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4 324 - #define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT) 325 - #define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 326 - #define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 327 - #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 328 - #define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT) 329 - #define I40E_VFINT_ICR0_SWINT_SHIFT 31 330 - #define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT) 331 - #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 332 - #define I40E_VFINT_ICR0_ENA_MAX_INDEX 127 333 - #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 334 - #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 335 - #define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30 336 - #define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT) 337 - #define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31 338 - #define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT) 339 - #define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */ 340 - #define I40E_VFINT_ITR0_MAX_INDEX 2 341 - #define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 342 - #define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT) 343 - #define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */ 344 - #define I40E_VFINT_ITRN_MAX_INDEX 2 345 - #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 346 - #define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT) 347 - #define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 348 - #define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 349 - #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 350 - #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 351 1102 #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 352 - #define I40E_VPINT_AEQCTL_MAX_INDEX 127 353 1103 #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 354 - #define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) 355 1104 #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 356 - #define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT) 357 - #define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13 358 - #define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT) 359 1105 #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 360 1106 #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 361 - #define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31 362 - #define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT) 363 1107 #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 364 - #define I40E_VPINT_CEQCTL_MAX_INDEX 511 365 1108 #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 366 - #define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) 367 1109 #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 368 - #define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) 369 - #define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13 370 - #define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT) 371 1110 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 372 1111 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 373 1112 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 374 1113 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 375 1114 #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 376 1115 #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 377 - #define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31 378 - #define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT) 379 1116 #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 380 - #define I40E_VPINT_LNKLST0_MAX_INDEX 127 381 1117 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 382 1118 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 383 - #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 384 - #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 385 1119 #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 386 - #define I40E_VPINT_LNKLSTN_MAX_INDEX 511 387 1120 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 388 1121 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 389 1122 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 390 1123 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 391 - #define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 392 - #define I40E_VPINT_RATE0_MAX_INDEX 127 393 - #define I40E_VPINT_RATE0_INTERVAL_SHIFT 0 394 - #define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT) 395 - #define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6 396 - #define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT) 397 - #define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 398 - #define I40E_VPINT_RATEN_MAX_INDEX 511 399 - #define I40E_VPINT_RATEN_INTERVAL_SHIFT 0 400 - #define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT) 401 - #define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6 402 - #define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT) 403 - #define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */ 404 - #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0 405 - #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT) 406 - #define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1 407 - #define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT) 408 1124 #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 409 1125 #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 410 1126 #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 411 1127 #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 412 - #define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0 413 - #define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT) 414 1128 #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 415 - #define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0 416 - #define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT) 417 1129 #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 418 - #define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0 419 - #define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT) 420 1130 #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 421 - #define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11 422 1131 #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 423 1132 #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 424 - #define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16 425 - #define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT) 426 1133 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 427 1134 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 428 1135 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 ··· 320 1257 #define I40E_PFLAN_QALLOC_VALID_SHIFT 31 321 1258 #define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) 322 1259 #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 323 - #define I40E_QRX_ENA_MAX_INDEX 1535 324 1260 #define I40E_QRX_ENA_QENA_REQ_SHIFT 0 325 1261 #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 326 - #define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 327 - #define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT) 328 1262 #define I40E_QRX_ENA_QENA_STAT_SHIFT 2 329 1263 #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) 330 1264 #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 331 - #define I40E_QRX_TAIL_MAX_INDEX 1535 332 - #define I40E_QRX_TAIL_TAIL_SHIFT 0 333 - #define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT) 334 1265 #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 335 - #define I40E_QTX_CTL_MAX_INDEX 1535 336 1266 #define I40E_QTX_CTL_PFVF_Q_SHIFT 0 337 1267 #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT) 338 1268 #define I40E_QTX_CTL_PF_INDX_SHIFT 2 ··· 333 1277 #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 334 1278 #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT) 335 1279 #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 336 - #define I40E_QTX_ENA_MAX_INDEX 1535 337 1280 #define I40E_QTX_ENA_QENA_REQ_SHIFT 0 338 1281 #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT) 339 - #define I40E_QTX_ENA_FAST_QDIS_SHIFT 1 340 - #define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT) 341 1282 #define I40E_QTX_ENA_QENA_STAT_SHIFT 2 342 1283 #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT) 343 1284 #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 344 - #define I40E_QTX_HEAD_MAX_INDEX 1535 345 - #define I40E_QTX_HEAD_HEAD_SHIFT 0 346 - #define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT) 347 - #define I40E_QTX_HEAD_RS_PENDING_SHIFT 16 348 - #define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT) 349 1285 #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 350 - #define I40E_QTX_TAIL_MAX_INDEX 1535 351 - #define I40E_QTX_TAIL_TAIL_SHIFT 0 352 - #define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT) 353 1286 #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 354 - #define I40E_VPLAN_MAPENA_MAX_INDEX 127 355 1287 #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 356 1288 #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 357 1289 #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 358 - #define I40E_VPLAN_QTABLE_MAX_INDEX 15 359 1290 #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 360 1291 #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT) 361 1292 #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 362 - #define I40E_VSILAN_QBASE_MAX_INDEX 383 363 - #define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0 364 - #define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT) 365 1293 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 366 1294 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 367 1295 #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 368 - #define I40E_VSILAN_QTABLE_MAX_INDEX 7 369 - #define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0 370 - #define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT) 371 - #define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16 372 - #define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) 373 1296 #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 374 1297 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 375 1298 #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT) ··· 357 1322 #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 358 1323 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 359 1324 #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT) 360 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */ 361 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0 362 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT) 363 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */ 364 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 365 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT) 366 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */ 367 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 368 - #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) 369 - #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */ 370 - #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0 371 - #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT) 372 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */ 373 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0 374 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT) 375 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */ 376 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0 377 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT) 378 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */ 379 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 380 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) 381 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */ 382 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0 383 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT) 384 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */ 385 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0 386 - #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT) 387 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */ 388 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 389 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) 390 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */ 391 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 392 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0 393 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT) 394 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */ 395 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 396 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 397 - #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) 398 - #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */ 399 - #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0 400 - #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT) 401 - #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */ 402 - #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0 403 - #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT) 404 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */ 405 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0 406 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT) 407 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2 408 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT) 409 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4 410 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT) 411 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6 412 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT) 413 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8 414 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT) 415 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10 416 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT) 417 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12 418 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT) 419 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14 420 - #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT) 421 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */ 422 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0 423 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT) 424 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2 425 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT) 426 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4 427 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT) 428 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6 429 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT) 430 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8 431 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT) 432 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10 433 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT) 434 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12 435 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT) 436 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14 437 - #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT) 438 - #define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */ 439 - #define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0 440 - #define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT) 441 - #define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */ 442 - #define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0 443 - #define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT) 444 - #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10 445 - #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT) 446 - #define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11 447 - #define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT) 448 - #define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15 449 - #define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT) 450 - #define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16 451 - #define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT) 452 - #define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19 453 - #define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT) 454 - #define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26 455 - #define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT) 456 - #define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27 457 - #define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT) 458 - #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28 459 - #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT) 460 - #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29 461 - #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT) 462 - #define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */ 463 - #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0 464 - #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT) 465 - #define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */ 466 - #define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31 467 - #define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0 468 - #define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT) 469 - #define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */ 470 - #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0 471 - #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT) 472 - #define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 473 - #define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7 474 - #define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0 475 - #define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT) 476 - #define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */ 477 - #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0 478 - #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT) 479 - #define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1 480 - #define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT) 481 - #define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17 482 - #define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT) 483 - #define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19 484 - #define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT) 485 - #define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25 486 - #define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT) 487 - #define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26 488 - #define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT) 489 - #define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28 490 - #define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT) 491 - #define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29 492 - #define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT) 493 - #define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 494 - #define I40E_PRT_MNG_MAVTV_MAX_INDEX 7 495 - #define I40E_PRT_MNG_MAVTV_VID_SHIFT 0 496 - #define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT) 497 - #define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 498 - #define I40E_PRT_MNG_MDEF_MAX_INDEX 7 499 - #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0 500 - #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT) 501 - #define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4 502 - #define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT) 503 - #define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5 504 - #define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT) 505 - #define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13 506 - #define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT) 507 - #define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17 508 - #define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT) 509 - #define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21 510 - #define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT) 511 - #define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25 512 - #define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT) 513 - #define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26 514 - #define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT) 515 - #define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27 516 - #define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT) 517 - #define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28 518 - #define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT) 519 - #define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29 520 - #define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT) 521 - #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30 522 - #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT) 523 - #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31 524 - #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT) 525 - #define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 526 - #define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7 527 - #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0 528 - #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT) 529 - #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4 530 - #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT) 531 - #define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8 532 - #define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT) 533 - #define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24 534 - #define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT) 535 - #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25 536 - #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT) 537 - #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26 538 - #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT) 539 - #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27 540 - #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT) 541 - #define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28 542 - #define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT) 543 - #define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29 544 - #define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT) 545 - #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30 546 - #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT) 547 - #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31 548 - #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT) 549 - #define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 550 - #define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3 551 - #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0 552 - #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT) 553 - #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16 554 - #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT) 555 - #define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 556 - #define I40E_PRT_MNG_METF_MAX_INDEX 3 557 - #define I40E_PRT_MNG_METF_ETYPE_SHIFT 0 558 - #define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT) 559 - #define I40E_PRT_MNG_METF_POLARITY_SHIFT 30 560 - #define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT) 561 - #define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */ 562 - #define I40E_PRT_MNG_MFUTP_MAX_INDEX 15 563 - #define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0 564 - #define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT) 565 - #define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16 566 - #define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT) 567 - #define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17 568 - #define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT) 569 - #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18 570 - #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT) 571 - #define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 572 - #define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3 573 - #define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0 574 - #define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT) 575 - #define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */ 576 - #define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15 577 - #define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0 578 - #define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT) 579 - #define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 580 - #define I40E_PRT_MNG_MMAH_MAX_INDEX 3 581 - #define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0 582 - #define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT) 583 - #define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 584 - #define I40E_PRT_MNG_MMAL_MAX_INDEX 3 585 - #define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0 586 - #define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT) 587 - #define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */ 588 - #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0 589 - #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT) 590 - #define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */ 591 - #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0 592 - #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT) 593 - #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1 594 - #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT) 595 - #define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2 596 - #define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT) 597 - #define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3 598 - #define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT) 599 - #define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4 600 - #define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT) 601 - #define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5 602 - #define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT) 603 - #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6 604 - #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT) 605 - #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7 606 - #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT) 607 - #define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */ 608 - #define I40E_MSIX_PBA_MAX_INDEX 5 609 - #define I40E_MSIX_PBA_PENBIT_SHIFT 0 610 - #define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT) 611 - #define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 612 - #define I40E_MSIX_TADD_MAX_INDEX 128 613 - #define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0 614 - #define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT) 615 - #define I40E_MSIX_TADD_MSIXTADD_SHIFT 2 616 - #define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT) 617 - #define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 618 - #define I40E_MSIX_TMSG_MAX_INDEX 128 619 - #define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0 620 - #define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT) 621 - #define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 622 - #define I40E_MSIX_TUADD_MAX_INDEX 128 623 - #define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0 624 - #define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT) 625 - #define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 626 - #define I40E_MSIX_TVCTRL_MAX_INDEX 128 627 - #define I40E_MSIX_TVCTRL_MASK_SHIFT 0 628 - #define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT) 629 - #define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ 630 - #define I40E_VFMSIX_PBA1_MAX_INDEX 19 631 - #define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 632 - #define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT) 633 - #define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 634 - #define I40E_VFMSIX_TADD1_MAX_INDEX 639 635 - #define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 636 - #define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) 637 - #define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 638 - #define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) 639 - #define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 640 - #define I40E_VFMSIX_TMSG1_MAX_INDEX 639 641 - #define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 642 - #define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) 643 - #define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 644 - #define I40E_VFMSIX_TUADD1_MAX_INDEX 639 645 - #define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 646 - #define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) 647 - #define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 648 - #define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 649 - #define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 650 - #define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT) 651 1325 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 652 - #define I40E_GLNVM_FLA_FL_SCK_SHIFT 0 653 - #define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT) 654 - #define I40E_GLNVM_FLA_FL_CE_SHIFT 1 655 - #define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT) 656 - #define I40E_GLNVM_FLA_FL_SI_SHIFT 2 657 - #define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT) 658 - #define I40E_GLNVM_FLA_FL_SO_SHIFT 3 659 - #define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT) 660 - #define I40E_GLNVM_FLA_FL_REQ_SHIFT 4 661 - #define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT) 662 - #define I40E_GLNVM_FLA_FL_GNT_SHIFT 5 663 - #define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT) 664 1326 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 665 1327 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 666 - #define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18 667 - #define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT) 668 - #define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30 669 - #define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT) 670 - #define I40E_GLNVM_FLA_FL_DER_SHIFT 31 671 - #define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT) 672 - #define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */ 673 - #define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0 674 - #define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT) 675 - #define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31 676 - #define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT) 677 1328 #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 678 - #define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0 679 - #define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT) 680 1329 #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 681 1330 #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT) 682 - #define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8 683 - #define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT) 684 - #define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23 685 - #define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT) 686 - #define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25 687 - #define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT) 688 - #define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */ 689 - #define I40E_GLNVM_PROTCSR_MAX_INDEX 59 690 - #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0 691 - #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT) 692 1331 #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 693 - #define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0 694 - #define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 695 1332 #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 696 - #define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT) 697 - #define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 698 - #define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT) 699 1333 #define I40E_GLNVM_SRCTL_START_SHIFT 30 700 - #define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT) 701 1334 #define I40E_GLNVM_SRCTL_DONE_SHIFT 31 702 1335 #define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) 703 1336 #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 704 - #define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 705 - #define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT) 706 1337 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 707 1338 #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 708 1339 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 709 - #define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 710 - #define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) 711 - #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1 712 - #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT) 713 - #define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2 714 - #define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT) 715 1340 #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 716 1341 #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 717 1342 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 718 1343 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 719 - #define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5 720 - #define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT) 721 - #define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6 722 - #define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT) 723 - #define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7 724 - #define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT) 725 - #define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8 726 - #define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT) 727 - #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9 728 - #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT) 729 - #define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */ 730 - #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0 731 - #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT) 732 - #define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */ 733 - #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0 734 - #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT) 735 - #define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */ 736 - #define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0 737 - #define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT) 738 1344 #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 739 - #define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0 740 - #define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT) 741 - #define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2 742 - #define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT) 743 - #define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3 744 - #define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT) 745 1345 #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 746 1346 #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 747 - #define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5 748 - #define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT) 749 - #define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6 750 - #define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT) 751 - #define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7 752 - #define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT) 753 - #define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16 754 - #define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT) 755 - #define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17 756 - #define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT) 757 - #define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18 758 - #define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT) 759 - #define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19 760 - #define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT) 761 - #define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20 762 - #define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT) 763 - #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30 764 - #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT) 765 - #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31 766 - #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT) 767 - #define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */ 768 - #define I40E_GLPCI_CNF_FLEX10_SHIFT 1 769 - #define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT) 770 - #define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2 771 - #define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT) 772 1347 #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 773 - #define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0 774 - #define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT) 775 - #define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1 776 - #define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT) 777 1348 #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 778 1349 #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 779 1350 #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 780 1351 #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 781 - #define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */ 782 - #define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0 783 - #define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT) 784 - #define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */ 785 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0 786 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT) 787 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1 788 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT) 789 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2 790 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT) 791 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3 792 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT) 793 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4 794 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT) 795 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5 796 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT) 797 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6 798 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT) 799 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7 800 - #define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT) 801 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8 802 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT) 803 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9 804 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT) 805 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14 806 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT) 807 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15 808 - #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT) 809 - #define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28 810 - #define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT) 811 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29 812 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT) 813 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30 814 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT) 815 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31 816 - #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT) 817 - #define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */ 818 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0 819 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT) 820 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8 821 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT) 822 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16 823 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT) 824 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24 825 - #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT) 826 - #define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 827 - #define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3 828 - #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 829 - #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) 830 - #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 831 - #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) 832 - #define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 833 - #define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 834 - #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 835 - #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) 836 1352 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 837 - #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 838 - #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) 839 - #define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 840 - #define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT) 841 - #define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 842 - #define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) 843 - #define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4 844 - #define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT) 845 1353 #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 846 1354 #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 847 - #define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT 10 848 - #define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT) 849 - #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11 850 - #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT) 851 - #define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */ 852 - #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0 853 - #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT) 854 - #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6 855 - #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT) 856 - #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9 857 - #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT) 858 - #define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */ 859 - #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0 860 - #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT) 861 - #define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */ 862 - #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0 863 - #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT) 864 - #define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */ 865 - #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0 866 - #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT) 867 - #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16 868 - #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT) 869 - #define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */ 870 - #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0 871 - #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT) 872 - #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16 873 - #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT) 874 - #define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */ 875 - #define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0 876 - #define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT) 877 - #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2 878 - #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT) 879 - #define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5 880 - #define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT) 881 - #define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8 882 - #define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT) 883 - #define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11 884 - #define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT) 885 - #define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14 886 - #define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT) 887 - #define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15 888 - #define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT) 889 - #define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */ 890 - #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0 891 - #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT) 892 - #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8 893 - #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT) 894 - #define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */ 895 - #define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0 896 - #define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT) 897 - #define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8 898 - #define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT) 899 - #define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16 900 - #define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT) 901 - #define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24 902 - #define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT) 903 - #define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */ 904 - #define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0 905 - #define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT) 906 - #define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */ 907 - #define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0 908 - #define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT) 909 - #define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */ 910 - #define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0 911 - #define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT) 912 - #define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */ 913 - #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0 914 - #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT) 915 - #define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */ 916 - #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0 917 - #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT) 918 - #define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */ 919 - #define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0 920 - #define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT) 921 - #define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */ 922 - #define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1 923 - #define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT) 924 - #define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */ 925 - #define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0 926 - #define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT) 927 - #define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */ 928 - #define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 929 - #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) 930 - #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 931 - #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) 932 - #define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */ 933 - #define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9 934 - #define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT) 935 - #define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11 936 - #define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT) 937 1355 #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 938 - #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 939 - #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) 940 - #define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 941 - #define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) 942 - #define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 943 - #define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) 944 1356 #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 945 - #define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0 946 - #define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT) 947 1357 #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 948 - #define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT) 949 1358 #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 950 - #define I40E_PF_PCI_CIAD_DATA_SHIFT 0 951 - #define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT) 952 - #define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */ 953 - #define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0 954 - #define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT) 955 - #define I40E_PFPCI_CLASS_RESERVED_1_SHIFT 1 956 - #define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT) 957 - #define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT 2 958 - #define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT) 959 - #define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */ 960 - #define I40E_PFPCI_CNF_MSI_EN_SHIFT 2 961 - #define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT) 962 - #define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3 963 - #define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT) 964 - #define I40E_PFPCI_CNF_IO_BAR_SHIFT 4 965 - #define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT) 966 - #define I40E_PFPCI_CNF_INT_PIN_SHIFT 5 967 - #define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT) 968 - #define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */ 969 - #define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0 970 - #define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT) 971 - #define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16 972 - #define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT) 973 - #define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */ 974 - #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0 975 - #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT) 976 - #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3 977 - #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT) 978 - #define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */ 979 - #define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0 980 - #define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT) 981 - #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1 982 - #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT) 983 - #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2 984 - #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT) 985 - #define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */ 986 - #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0 987 - #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT) 988 - #define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */ 989 - #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0 990 - #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT) 991 - #define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */ 992 - #define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0 993 - #define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT) 994 - #define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */ 995 - #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 996 - #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT) 997 - #define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */ 998 - #define I40E_PFPCI_PM_PME_EN_SHIFT 0 999 - #define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT) 1000 - #define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */ 1001 - #define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0 1002 - #define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT) 1003 - #define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */ 1004 - #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0 1005 - #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT) 1006 - #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16 1007 - #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT) 1008 - #define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */ 1009 - #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 1010 - #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT) 1011 - #define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */ 1012 - #define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127 1013 - #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0 1014 - #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT) 1015 - #define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */ 1016 - #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0 1017 - #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT) 1018 - #define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */ 1019 - #define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0 1020 - #define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT) 1021 - #define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */ 1022 - #define I40E_PFPCI_VMPEND_PENDING_SHIFT 0 1023 - #define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT) 1024 1359 #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 1025 - #define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29 1026 - #define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT) 1027 1360 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 1028 1361 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 1029 1362 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 1030 1363 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 1031 - #define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */ 1032 - #define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16 1033 - #define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT) 1034 - #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24 1035 - #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT) 1036 - #define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26 1037 - #define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT) 1038 - #define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */ 1039 - #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31 1040 - #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT) 1041 - #define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */ 1042 - #define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0 1043 - #define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT) 1044 - #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 1045 - #define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) 1046 - #define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */ 1047 - #define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0 1048 - #define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT) 1049 - #define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */ 1050 - #define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0 1051 - #define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT) 1052 - #define I40E_PRTPM_GC_MNG_VETO_SHIFT 1 1053 - #define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT) 1054 - #define I40E_PRTPM_GC_RATD_SHIFT 2 1055 - #define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT) 1056 - #define I40E_PRTPM_GC_LCDMP_SHIFT 3 1057 - #define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT) 1058 - #define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 1059 - #define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) 1060 1364 #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 1061 - #define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 1062 - #define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT) 1063 1365 #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 1064 - #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 1065 - #define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT) 1066 - #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 1067 - #define I40E_GL_PRS_FVBM_MAX_INDEX 3 1068 - #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT 0 1069 - #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT) 1070 - #define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8 1071 - #define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT) 1072 - #define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT 31 1073 - #define I40E_GL_PRS_FVBM_MSK_ENA_MASK I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT) 1074 - #define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */ 1075 - #define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 1076 - #define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT) 1077 - #define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */ 1078 - #define I40E_GLRPB_GHW_GHW_SHIFT 0 1079 - #define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT) 1080 - #define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */ 1081 - #define I40E_GLRPB_GLW_GLW_SHIFT 0 1082 - #define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT) 1083 - #define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */ 1084 - #define I40E_GLRPB_PHW_PHW_SHIFT 0 1085 - #define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT) 1086 - #define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */ 1087 - #define I40E_GLRPB_PLW_PLW_SHIFT 0 1088 - #define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT) 1089 - #define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 1090 - #define I40E_PRTRPB_DHW_MAX_INDEX 7 1091 - #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 1092 - #define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT) 1093 - #define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 1094 - #define I40E_PRTRPB_DLW_MAX_INDEX 7 1095 - #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 1096 - #define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT) 1097 - #define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 1098 - #define I40E_PRTRPB_DPS_MAX_INDEX 7 1099 - #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 1100 - #define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT) 1101 - #define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 1102 - #define I40E_PRTRPB_SHT_MAX_INDEX 7 1103 - #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 1104 - #define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT) 1105 - #define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */ 1106 - #define I40E_PRTRPB_SHW_SHW_SHIFT 0 1107 - #define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT) 1108 - #define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 1109 - #define I40E_PRTRPB_SLT_MAX_INDEX 7 1110 - #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 1111 - #define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT) 1112 - #define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */ 1113 - #define I40E_PRTRPB_SLW_SLW_SHIFT 0 1114 - #define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT) 1115 - #define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */ 1116 - #define I40E_PRTRPB_SPS_SPS_SHIFT 0 1117 - #define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT) 1118 - #define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */ 1119 - #define I40E_GLQF_CTL_HTOEP_SHIFT 1 1120 - #define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT) 1121 - #define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2 1122 - #define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT) 1123 - #define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3 1124 - #define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT) 1125 - #define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6 1126 - #define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT) 1127 - #define I40E_GLQF_CTL_RSVD_SHIFT 7 1128 - #define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT) 1129 - #define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8 1130 - #define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT) 1131 - #define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11 1132 - #define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT) 1133 - #define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14 1134 - #define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT) 1135 - #define I40E_GLQF_CTL_FDBEST_SHIFT 17 1136 - #define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT) 1137 - #define I40E_GLQF_CTL_PROGPRIO_SHIFT 25 1138 - #define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT) 1139 - #define I40E_GLQF_CTL_INVALPRIO_SHIFT 26 1140 - #define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT) 1141 - #define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27 1142 - #define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT) 1143 1366 #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 1144 1367 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 1145 1368 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) ··· 405 2112 #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 406 2113 #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 407 2114 #define I40E_GLQF_HKEY_MAX_INDEX 12 408 - #define I40E_GLQF_HKEY_KEY_0_SHIFT 0 409 - #define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT) 410 - #define I40E_GLQF_HKEY_KEY_1_SHIFT 8 411 - #define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT) 412 - #define I40E_GLQF_HKEY_KEY_2_SHIFT 16 413 - #define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT) 414 - #define I40E_GLQF_HKEY_KEY_3_SHIFT 24 415 - #define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT) 416 - #define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 417 - #define I40E_GLQF_HSYM_MAX_INDEX 63 418 - #define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0 419 - #define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT) 420 2115 #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 421 - #define I40E_GLQF_PCNT_MAX_INDEX 511 422 - #define I40E_GLQF_PCNT_PCNT_SHIFT 0 423 - #define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT) 424 - #define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 425 - #define I40E_GLQF_SWAP_MAX_INDEX 1 426 - #define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0 427 - #define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) 428 - #define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6 429 - #define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) 430 - #define I40E_GLQF_SWAP_FLEN0_SHIFT 12 431 - #define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT) 432 - #define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16 433 - #define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) 434 - #define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22 435 - #define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) 436 - #define I40E_GLQF_SWAP_FLEN1_SHIFT 28 437 - #define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT) 438 2116 #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 439 2117 #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 440 2118 #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT) ··· 423 2159 #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 424 2160 #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 425 2161 #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 426 - #define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20 427 - #define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT) 428 - #define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24 429 - #define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT) 430 2162 #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 431 2163 #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 432 2164 #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 433 - #define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */ 434 - #define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0 435 - #define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT) 436 - #define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8 437 - #define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT) 438 2165 #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 439 2166 #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 440 2167 #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 441 2168 #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 442 2169 #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 443 2170 #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 444 - #define I40E_PFQF_HENA_MAX_INDEX 1 445 - #define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0 446 - #define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT) 447 2171 #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 448 2172 #define I40E_PFQF_HKEY_MAX_INDEX 12 449 - #define I40E_PFQF_HKEY_KEY_0_SHIFT 0 450 - #define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT) 451 - #define I40E_PFQF_HKEY_KEY_1_SHIFT 8 452 - #define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT) 453 - #define I40E_PFQF_HKEY_KEY_2_SHIFT 16 454 - #define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT) 455 - #define I40E_PFQF_HKEY_KEY_3_SHIFT 24 456 - #define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT) 457 2173 #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 458 2174 #define I40E_PFQF_HLUT_MAX_INDEX 127 459 - #define I40E_PFQF_HLUT_LUT0_SHIFT 0 460 - #define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT) 461 - #define I40E_PFQF_HLUT_LUT1_SHIFT 8 462 - #define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT) 463 - #define I40E_PFQF_HLUT_LUT2_SHIFT 16 464 - #define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT) 465 - #define I40E_PFQF_HLUT_LUT3_SHIFT 24 466 - #define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT) 467 - #define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */ 468 - #define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 469 - #define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) 470 - #define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */ 471 - #define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 472 - #define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 473 - #define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) 474 2175 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 475 2176 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 476 2177 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 ··· 444 2215 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 445 2216 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 446 2217 #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 447 - #define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 448 - #define I40E_PRTQF_FD_MSK_MAX_INDEX 63 449 - #define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 450 - #define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT) 451 - #define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 452 - #define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT) 453 2218 #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 454 - #define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 455 2219 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 456 2220 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 457 2221 #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 ··· 452 2230 #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 453 2231 #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 454 2232 #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 455 - #define I40E_VFQF_HENA1_MAX_INDEX 1 456 - #define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0 457 - #define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT) 458 2233 #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 459 2234 #define I40E_VFQF_HKEY1_MAX_INDEX 12 460 - #define I40E_VFQF_HKEY1_KEY_0_SHIFT 0 461 - #define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT) 462 - #define I40E_VFQF_HKEY1_KEY_1_SHIFT 8 463 - #define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT) 464 - #define I40E_VFQF_HKEY1_KEY_2_SHIFT 16 465 - #define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT) 466 - #define I40E_VFQF_HKEY1_KEY_3_SHIFT 24 467 - #define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT) 468 2235 #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 469 2236 #define I40E_VFQF_HLUT1_MAX_INDEX 15 470 - #define I40E_VFQF_HLUT1_LUT0_SHIFT 0 471 - #define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT) 472 - #define I40E_VFQF_HLUT1_LUT1_SHIFT 8 473 - #define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT) 474 - #define I40E_VFQF_HLUT1_LUT2_SHIFT 16 475 - #define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT) 476 - #define I40E_VFQF_HLUT1_LUT3_SHIFT 24 477 - #define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT) 478 - #define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */ 479 - #define I40E_VFQF_HREGION1_MAX_INDEX 7 480 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0 481 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT) 482 - #define I40E_VFQF_HREGION1_REGION_0_SHIFT 1 483 - #define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT) 484 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4 485 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT) 486 - #define I40E_VFQF_HREGION1_REGION_1_SHIFT 5 487 - #define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT) 488 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8 489 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT) 490 - #define I40E_VFQF_HREGION1_REGION_2_SHIFT 9 491 - #define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT) 492 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12 493 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT) 494 - #define I40E_VFQF_HREGION1_REGION_3_SHIFT 13 495 - #define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT) 496 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16 497 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT) 498 - #define I40E_VFQF_HREGION1_REGION_4_SHIFT 17 499 - #define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT) 500 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20 501 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT) 502 - #define I40E_VFQF_HREGION1_REGION_5_SHIFT 21 503 - #define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT) 504 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24 505 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT) 506 - #define I40E_VFQF_HREGION1_REGION_6_SHIFT 25 507 - #define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT) 508 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28 509 - #define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT) 510 - #define I40E_VFQF_HREGION1_REGION_7_SHIFT 29 511 - #define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT) 512 - #define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 513 - #define I40E_VPQF_CTL_MAX_INDEX 127 514 - #define I40E_VPQF_CTL_PEHSIZE_SHIFT 0 515 - #define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT) 516 - #define I40E_VPQF_CTL_PEDSIZE_SHIFT 5 517 - #define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT) 518 - #define I40E_VPQF_CTL_FCHSIZE_SHIFT 10 519 - #define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT) 520 - #define I40E_VPQF_CTL_FCDSIZE_SHIFT 14 521 - #define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT) 522 - #define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 523 - #define I40E_VSIQF_CTL_MAX_INDEX 383 524 - #define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0 525 - #define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT) 526 - #define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1 527 - #define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PETCP_ENA_SHIFT) 528 - #define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2 529 - #define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT) 530 - #define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3 531 - #define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT) 532 - #define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4 533 - #define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT) 534 - #define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5 535 - #define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT) 536 - #define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */ 537 - #define I40E_VSIQF_TCREGION_MAX_INDEX 3 538 - #define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0 539 - #define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT) 540 - #define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9 541 - #define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT) 542 - #define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16 543 - #define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT) 544 - #define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25 545 - #define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT) 546 - #define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 547 - #define I40E_GL_FCOECRC_MAX_INDEX 143 548 - #define I40E_GL_FCOECRC_FCOECRC_SHIFT 0 549 - #define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT) 550 - #define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 551 - #define I40E_GL_FCOEDDPC_MAX_INDEX 143 552 - #define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0 553 - #define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT) 554 - #define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 555 - #define I40E_GL_FCOEDIFEC_MAX_INDEX 143 556 - #define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0 557 - #define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT) 558 - #define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 559 - #define I40E_GL_FCOEDIFTCL_MAX_INDEX 143 560 - #define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0 561 - #define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT) 562 - #define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 563 - #define I40E_GL_FCOEDIXEC_MAX_INDEX 143 564 - #define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0 565 - #define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT) 566 - #define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 567 - #define I40E_GL_FCOEDIXVC_MAX_INDEX 143 568 - #define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0 569 - #define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT) 570 - #define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 571 - #define I40E_GL_FCOEDWRCH_MAX_INDEX 143 572 - #define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0 573 - #define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT) 574 - #define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 575 - #define I40E_GL_FCOEDWRCL_MAX_INDEX 143 576 - #define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0 577 - #define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT) 578 - #define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 579 - #define I40E_GL_FCOEDWTCH_MAX_INDEX 143 580 - #define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0 581 - #define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT) 582 - #define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 583 - #define I40E_GL_FCOEDWTCL_MAX_INDEX 143 584 - #define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0 585 - #define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT) 586 - #define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 587 - #define I40E_GL_FCOELAST_MAX_INDEX 143 588 - #define I40E_GL_FCOELAST_FCOELAST_SHIFT 0 589 - #define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT) 590 - #define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 591 - #define I40E_GL_FCOEPRC_MAX_INDEX 143 592 - #define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0 593 - #define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT) 594 - #define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 595 - #define I40E_GL_FCOEPTC_MAX_INDEX 143 596 - #define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0 597 - #define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT) 598 - #define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 599 - #define I40E_GL_FCOERPDC_MAX_INDEX 143 600 - #define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0 601 - #define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT) 602 - #define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 603 - #define I40E_GL_RXERR1_L_MAX_INDEX 143 604 - #define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0 605 - #define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT) 606 - #define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 607 - #define I40E_GL_RXERR2_L_MAX_INDEX 143 608 - #define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0 609 - #define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT) 610 2237 #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 611 - #define I40E_GLPRT_BPRCH_MAX_INDEX 3 612 - #define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0 613 - #define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT) 614 2238 #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 615 - #define I40E_GLPRT_BPRCL_MAX_INDEX 3 616 - #define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0 617 - #define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT) 618 2239 #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 619 - #define I40E_GLPRT_BPTCH_MAX_INDEX 3 620 - #define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0 621 - #define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT) 622 2240 #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 623 - #define I40E_GLPRT_BPTCL_MAX_INDEX 3 624 - #define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0 625 - #define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT) 626 2241 #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 627 - #define I40E_GLPRT_CRCERRS_MAX_INDEX 3 628 - #define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 629 - #define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) 630 2242 #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 631 - #define I40E_GLPRT_GORCH_MAX_INDEX 3 632 - #define I40E_GLPRT_GORCH_GORCH_SHIFT 0 633 - #define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT) 634 2243 #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 635 - #define I40E_GLPRT_GORCL_MAX_INDEX 3 636 - #define I40E_GLPRT_GORCL_GORCL_SHIFT 0 637 - #define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT) 638 2244 #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 639 - #define I40E_GLPRT_GOTCH_MAX_INDEX 3 640 - #define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0 641 - #define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT) 642 2245 #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 643 - #define I40E_GLPRT_GOTCL_MAX_INDEX 3 644 - #define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0 645 - #define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT) 646 2246 #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 647 - #define I40E_GLPRT_ILLERRC_MAX_INDEX 3 648 - #define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0 649 - #define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT) 650 - #define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 651 - #define I40E_GLPRT_LDPC_MAX_INDEX 3 652 - #define I40E_GLPRT_LDPC_LDPC_SHIFT 0 653 - #define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT) 654 2247 #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 655 - #define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3 656 - #define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0 657 - #define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT) 658 2248 #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 659 - #define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3 660 - #define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0 661 - #define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT) 662 2249 #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 663 - #define I40E_GLPRT_LXONRXC_MAX_INDEX 3 664 - #define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0 665 - #define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT) 666 2250 #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 667 - #define I40E_GLPRT_LXONTXC_MAX_INDEX 3 668 - #define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0 669 - #define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT) 670 2251 #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 671 - #define I40E_GLPRT_MLFC_MAX_INDEX 3 672 - #define I40E_GLPRT_MLFC_MLFC_SHIFT 0 673 - #define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT) 674 2252 #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 675 - #define I40E_GLPRT_MPRCH_MAX_INDEX 3 676 - #define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0 677 - #define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT) 678 2253 #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 679 - #define I40E_GLPRT_MPRCL_MAX_INDEX 3 680 - #define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0 681 - #define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT) 682 2254 #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 683 - #define I40E_GLPRT_MPTCH_MAX_INDEX 3 684 - #define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0 685 - #define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT) 686 2255 #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 687 - #define I40E_GLPRT_MPTCL_MAX_INDEX 3 688 - #define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0 689 - #define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT) 690 2256 #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 691 - #define I40E_GLPRT_MRFC_MAX_INDEX 3 692 - #define I40E_GLPRT_MRFC_MRFC_SHIFT 0 693 - #define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT) 694 2257 #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 695 - #define I40E_GLPRT_PRC1023H_MAX_INDEX 3 696 - #define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0 697 - #define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT) 698 2258 #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 699 - #define I40E_GLPRT_PRC1023L_MAX_INDEX 3 700 - #define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0 701 - #define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT) 702 2259 #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 703 - #define I40E_GLPRT_PRC127H_MAX_INDEX 3 704 - #define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0 705 - #define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT) 706 2260 #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 707 - #define I40E_GLPRT_PRC127L_MAX_INDEX 3 708 - #define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0 709 - #define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT) 710 2261 #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 711 - #define I40E_GLPRT_PRC1522H_MAX_INDEX 3 712 - #define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0 713 - #define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT) 714 2262 #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 715 - #define I40E_GLPRT_PRC1522L_MAX_INDEX 3 716 - #define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0 717 - #define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT) 718 2263 #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 719 - #define I40E_GLPRT_PRC255H_MAX_INDEX 3 720 - #define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0 721 - #define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT) 722 2264 #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 723 - #define I40E_GLPRT_PRC255L_MAX_INDEX 3 724 - #define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0 725 - #define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT) 726 2265 #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 727 - #define I40E_GLPRT_PRC511H_MAX_INDEX 3 728 - #define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0 729 - #define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT) 730 2266 #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 731 - #define I40E_GLPRT_PRC511L_MAX_INDEX 3 732 - #define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0 733 - #define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT) 734 2267 #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 735 - #define I40E_GLPRT_PRC64H_MAX_INDEX 3 736 - #define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0 737 - #define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT) 738 2268 #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 739 - #define I40E_GLPRT_PRC64L_MAX_INDEX 3 740 - #define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0 741 - #define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT) 742 2269 #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 743 - #define I40E_GLPRT_PRC9522H_MAX_INDEX 3 744 - #define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0 745 - #define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT) 746 2270 #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 747 - #define I40E_GLPRT_PRC9522L_MAX_INDEX 3 748 - #define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0 749 - #define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT) 750 2271 #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 751 - #define I40E_GLPRT_PTC1023H_MAX_INDEX 3 752 - #define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0 753 - #define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT) 754 2272 #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 755 - #define I40E_GLPRT_PTC1023L_MAX_INDEX 3 756 - #define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0 757 - #define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT) 758 2273 #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 759 - #define I40E_GLPRT_PTC127H_MAX_INDEX 3 760 - #define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0 761 - #define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT) 762 2274 #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 763 - #define I40E_GLPRT_PTC127L_MAX_INDEX 3 764 - #define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0 765 - #define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT) 766 2275 #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 767 - #define I40E_GLPRT_PTC1522H_MAX_INDEX 3 768 - #define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0 769 - #define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT) 770 2276 #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 771 - #define I40E_GLPRT_PTC1522L_MAX_INDEX 3 772 - #define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0 773 - #define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT) 774 2277 #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 775 - #define I40E_GLPRT_PTC255H_MAX_INDEX 3 776 - #define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0 777 - #define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT) 778 2278 #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 779 - #define I40E_GLPRT_PTC255L_MAX_INDEX 3 780 - #define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0 781 - #define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT) 782 2279 #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 783 - #define I40E_GLPRT_PTC511H_MAX_INDEX 3 784 - #define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0 785 - #define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT) 786 2280 #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 787 - #define I40E_GLPRT_PTC511L_MAX_INDEX 3 788 - #define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0 789 - #define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT) 790 2281 #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 791 - #define I40E_GLPRT_PTC64H_MAX_INDEX 3 792 - #define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0 793 - #define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT) 794 2282 #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 795 - #define I40E_GLPRT_PTC64L_MAX_INDEX 3 796 - #define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0 797 - #define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT) 798 2283 #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 799 - #define I40E_GLPRT_PTC9522H_MAX_INDEX 3 800 - #define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0 801 - #define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT) 802 2284 #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 803 - #define I40E_GLPRT_PTC9522L_MAX_INDEX 3 804 - #define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0 805 - #define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT) 806 2285 #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 807 - #define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3 808 - #define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0 809 - #define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT) 810 2286 #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 811 - #define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3 812 - #define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0 813 - #define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT) 814 2287 #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 815 - #define I40E_GLPRT_PXONRXC_MAX_INDEX 3 816 - #define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0 817 - #define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT) 818 2288 #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 819 - #define I40E_GLPRT_PXONTXC_MAX_INDEX 3 820 - #define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0 821 - #define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT) 822 2289 #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 823 - #define I40E_GLPRT_RDPC_MAX_INDEX 3 824 - #define I40E_GLPRT_RDPC_RDPC_SHIFT 0 825 - #define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT) 826 2290 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 827 - #define I40E_GLPRT_RFC_MAX_INDEX 3 828 - #define I40E_GLPRT_RFC_RFC_SHIFT 0 829 - #define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT) 830 2291 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 831 - #define I40E_GLPRT_RJC_MAX_INDEX 3 832 - #define I40E_GLPRT_RJC_RJC_SHIFT 0 833 - #define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT) 834 2292 #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 835 - #define I40E_GLPRT_RLEC_MAX_INDEX 3 836 - #define I40E_GLPRT_RLEC_RLEC_SHIFT 0 837 - #define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT) 838 2293 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 839 - #define I40E_GLPRT_ROC_MAX_INDEX 3 840 - #define I40E_GLPRT_ROC_ROC_SHIFT 0 841 - #define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT) 842 2294 #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 843 - #define I40E_GLPRT_RUC_MAX_INDEX 3 844 - #define I40E_GLPRT_RUC_RUC_SHIFT 0 845 - #define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT) 846 - #define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 847 - #define I40E_GLPRT_RUPP_MAX_INDEX 3 848 - #define I40E_GLPRT_RUPP_RUPP_SHIFT 0 849 - #define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT) 850 2295 #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 851 - #define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 852 - #define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 853 - #define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) 854 2296 #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 855 - #define I40E_GLPRT_TDOLD_MAX_INDEX 3 856 - #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 857 - #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) 858 2297 #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 859 - #define I40E_GLPRT_UPRCH_MAX_INDEX 3 860 - #define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 861 - #define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT) 862 2298 #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 863 - #define I40E_GLPRT_UPRCL_MAX_INDEX 3 864 - #define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 865 - #define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT) 866 2299 #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 867 - #define I40E_GLPRT_UPTCH_MAX_INDEX 3 868 - #define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0 869 - #define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT) 870 2300 #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 871 - #define I40E_GLPRT_UPTCL_MAX_INDEX 3 872 - #define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0 873 - #define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT) 874 2301 #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 875 - #define I40E_GLSW_BPRCH_MAX_INDEX 15 876 - #define I40E_GLSW_BPRCH_BPRCH_SHIFT 0 877 - #define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT) 878 2302 #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 879 - #define I40E_GLSW_BPRCL_MAX_INDEX 15 880 - #define I40E_GLSW_BPRCL_BPRCL_SHIFT 0 881 - #define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT) 882 2303 #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 883 - #define I40E_GLSW_BPTCH_MAX_INDEX 15 884 - #define I40E_GLSW_BPTCH_BPTCH_SHIFT 0 885 - #define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT) 886 2304 #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 887 - #define I40E_GLSW_BPTCL_MAX_INDEX 15 888 - #define I40E_GLSW_BPTCL_BPTCL_SHIFT 0 889 - #define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT) 890 2305 #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 891 - #define I40E_GLSW_GORCH_MAX_INDEX 15 892 - #define I40E_GLSW_GORCH_GORCH_SHIFT 0 893 - #define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT) 894 2306 #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 895 - #define I40E_GLSW_GORCL_MAX_INDEX 15 896 - #define I40E_GLSW_GORCL_GORCL_SHIFT 0 897 - #define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT) 898 2307 #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 899 - #define I40E_GLSW_GOTCH_MAX_INDEX 15 900 - #define I40E_GLSW_GOTCH_GOTCH_SHIFT 0 901 - #define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT) 902 2308 #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 903 - #define I40E_GLSW_GOTCL_MAX_INDEX 15 904 - #define I40E_GLSW_GOTCL_GOTCL_SHIFT 0 905 - #define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT) 906 2309 #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 907 - #define I40E_GLSW_MPRCH_MAX_INDEX 15 908 - #define I40E_GLSW_MPRCH_MPRCH_SHIFT 0 909 - #define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT) 910 2310 #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 911 - #define I40E_GLSW_MPRCL_MAX_INDEX 15 912 - #define I40E_GLSW_MPRCL_MPRCL_SHIFT 0 913 - #define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT) 914 2311 #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 915 - #define I40E_GLSW_MPTCH_MAX_INDEX 15 916 - #define I40E_GLSW_MPTCH_MPTCH_SHIFT 0 917 - #define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT) 918 2312 #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 919 - #define I40E_GLSW_MPTCL_MAX_INDEX 15 920 - #define I40E_GLSW_MPTCL_MPTCL_SHIFT 0 921 - #define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT) 922 2313 #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 923 - #define I40E_GLSW_RUPP_MAX_INDEX 15 924 - #define I40E_GLSW_RUPP_RUPP_SHIFT 0 925 - #define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT) 926 2314 #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 927 - #define I40E_GLSW_TDPC_MAX_INDEX 15 928 - #define I40E_GLSW_TDPC_TDPC_SHIFT 0 929 - #define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT) 930 2315 #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 931 - #define I40E_GLSW_UPRCH_MAX_INDEX 15 932 - #define I40E_GLSW_UPRCH_UPRCH_SHIFT 0 933 - #define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT) 934 2316 #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 935 - #define I40E_GLSW_UPRCL_MAX_INDEX 15 936 - #define I40E_GLSW_UPRCL_UPRCL_SHIFT 0 937 - #define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT) 938 2317 #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 939 - #define I40E_GLSW_UPTCH_MAX_INDEX 15 940 - #define I40E_GLSW_UPTCH_UPTCH_SHIFT 0 941 - #define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT) 942 2318 #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 943 - #define I40E_GLSW_UPTCL_MAX_INDEX 15 944 - #define I40E_GLSW_UPTCL_UPTCL_SHIFT 0 945 - #define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT) 946 2319 #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 947 - #define I40E_GLV_BPRCH_MAX_INDEX 383 948 - #define I40E_GLV_BPRCH_BPRCH_SHIFT 0 949 - #define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT) 950 2320 #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 951 - #define I40E_GLV_BPRCL_MAX_INDEX 383 952 - #define I40E_GLV_BPRCL_BPRCL_SHIFT 0 953 - #define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT) 954 2321 #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 955 - #define I40E_GLV_BPTCH_MAX_INDEX 383 956 - #define I40E_GLV_BPTCH_BPTCH_SHIFT 0 957 - #define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT) 958 2322 #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 959 - #define I40E_GLV_BPTCL_MAX_INDEX 383 960 - #define I40E_GLV_BPTCL_BPTCL_SHIFT 0 961 - #define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT) 962 2323 #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 963 - #define I40E_GLV_GORCH_MAX_INDEX 383 964 - #define I40E_GLV_GORCH_GORCH_SHIFT 0 965 - #define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT) 966 2324 #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 967 - #define I40E_GLV_GORCL_MAX_INDEX 383 968 - #define I40E_GLV_GORCL_GORCL_SHIFT 0 969 - #define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT) 970 2325 #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 971 - #define I40E_GLV_GOTCH_MAX_INDEX 383 972 - #define I40E_GLV_GOTCH_GOTCH_SHIFT 0 973 - #define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT) 974 2326 #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 975 - #define I40E_GLV_GOTCL_MAX_INDEX 383 976 - #define I40E_GLV_GOTCL_GOTCL_SHIFT 0 977 - #define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT) 978 2327 #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 979 - #define I40E_GLV_MPRCH_MAX_INDEX 383 980 - #define I40E_GLV_MPRCH_MPRCH_SHIFT 0 981 - #define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT) 982 2328 #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 983 - #define I40E_GLV_MPRCL_MAX_INDEX 383 984 - #define I40E_GLV_MPRCL_MPRCL_SHIFT 0 985 - #define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT) 986 2329 #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 987 - #define I40E_GLV_MPTCH_MAX_INDEX 383 988 - #define I40E_GLV_MPTCH_MPTCH_SHIFT 0 989 - #define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT) 990 2330 #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 991 - #define I40E_GLV_MPTCL_MAX_INDEX 383 992 - #define I40E_GLV_MPTCL_MPTCL_SHIFT 0 993 - #define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT) 994 2331 #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 995 - #define I40E_GLV_RDPC_MAX_INDEX 383 996 - #define I40E_GLV_RDPC_RDPC_SHIFT 0 997 - #define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT) 998 2332 #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 999 - #define I40E_GLV_RUPP_MAX_INDEX 383 1000 - #define I40E_GLV_RUPP_RUPP_SHIFT 0 1001 - #define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT) 1002 2333 #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 1003 - #define I40E_GLV_TEPC_MAX_INDEX 383 1004 - #define I40E_GLV_TEPC_TEPC_SHIFT 0 1005 - #define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT) 1006 2334 #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 1007 - #define I40E_GLV_UPRCH_MAX_INDEX 383 1008 - #define I40E_GLV_UPRCH_UPRCH_SHIFT 0 1009 - #define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT) 1010 2335 #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 1011 - #define I40E_GLV_UPRCL_MAX_INDEX 383 1012 - #define I40E_GLV_UPRCL_UPRCL_SHIFT 0 1013 - #define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT) 1014 2336 #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 1015 - #define I40E_GLV_UPTCH_MAX_INDEX 383 1016 - #define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0 1017 - #define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT) 1018 2337 #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 1019 - #define I40E_GLV_UPTCL_MAX_INDEX 383 1020 - #define I40E_GLV_UPTCL_UPTCL_SHIFT 0 1021 - #define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT) 1022 2338 #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1023 - #define I40E_GLVEBTC_RBCH_MAX_INDEX 7 1024 - #define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0 1025 - #define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT) 1026 2339 #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1027 - #define I40E_GLVEBTC_RBCL_MAX_INDEX 7 1028 - #define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0 1029 - #define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT) 1030 2340 #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1031 - #define I40E_GLVEBTC_RPCH_MAX_INDEX 7 1032 - #define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0 1033 - #define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT) 1034 2341 #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1035 - #define I40E_GLVEBTC_RPCL_MAX_INDEX 7 1036 - #define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0 1037 - #define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT) 1038 2342 #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1039 - #define I40E_GLVEBTC_TBCH_MAX_INDEX 7 1040 - #define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0 1041 - #define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT) 1042 2343 #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1043 - #define I40E_GLVEBTC_TBCL_MAX_INDEX 7 1044 - #define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0 1045 - #define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT) 1046 2344 #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1047 - #define I40E_GLVEBTC_TPCH_MAX_INDEX 7 1048 - #define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0 1049 - #define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT) 1050 2345 #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 1051 - #define I40E_GLVEBTC_TPCL_MAX_INDEX 7 1052 - #define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0 1053 - #define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT) 1054 - #define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1055 - #define I40E_GLVEBVL_BPCH_MAX_INDEX 127 1056 - #define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0 1057 - #define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT) 1058 - #define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1059 - #define I40E_GLVEBVL_BPCL_MAX_INDEX 127 1060 - #define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0 1061 - #define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT) 1062 - #define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1063 - #define I40E_GLVEBVL_GORCH_MAX_INDEX 127 1064 - #define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0 1065 - #define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT) 1066 - #define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1067 - #define I40E_GLVEBVL_GORCL_MAX_INDEX 127 1068 - #define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0 1069 - #define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT) 1070 - #define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1071 - #define I40E_GLVEBVL_GOTCH_MAX_INDEX 127 1072 - #define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0 1073 - #define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT) 1074 - #define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1075 - #define I40E_GLVEBVL_GOTCL_MAX_INDEX 127 1076 - #define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0 1077 - #define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT) 1078 - #define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1079 - #define I40E_GLVEBVL_MPCH_MAX_INDEX 127 1080 - #define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0 1081 - #define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT) 1082 - #define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1083 - #define I40E_GLVEBVL_MPCL_MAX_INDEX 127 1084 - #define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0 1085 - #define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT) 1086 - #define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1087 - #define I40E_GLVEBVL_UPCH_MAX_INDEX 127 1088 - #define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0 1089 - #define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT) 1090 - #define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 1091 - #define I40E_GLVEBVL_UPCL_MAX_INDEX 127 1092 - #define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0 1093 - #define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT) 1094 - #define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */ 1095 - #define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0 1096 - #define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT) 1097 - #define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */ 1098 - #define I40E_GL_SWR_DEF_ACT_MAX_INDEX 35 1099 - #define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0 1100 - #define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT) 1101 - #define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 1102 - #define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX 1 1103 - #define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0 1104 - #define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT) 1105 - #define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */ 1106 - #define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0 1107 - #define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT) 1108 - #define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31 1109 - #define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT) 1110 - #define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1111 - #define I40E_PRTTSYN_AUX_0_MAX_INDEX 1 1112 - #define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 1113 - #define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 1114 - #define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 1115 - #define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 1116 - #define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3 1117 - #define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT) 1118 - #define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8 1119 - #define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT) 1120 - #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 1121 - #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) 1122 - #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1123 - #define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 1124 - #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 1125 - #define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 1126 - #define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1 1127 - #define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT) 1128 - #define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1129 - #define I40E_PRTTSYN_CLKO_MAX_INDEX 1 1130 - #define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0 1131 - #define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT) 1132 2346 #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 1133 - #define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0 1134 - #define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT) 1135 2347 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 1136 2348 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 1137 - #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 1138 - #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) 1139 - #define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3 1140 - #define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT) 1141 2349 #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 1142 2350 #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 1143 - #define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12 1144 - #define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT) 1145 2351 #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 1146 2352 #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 1147 2353 #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 1148 2354 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 1149 2355 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 1150 - #define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8 1151 - #define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT) 1152 2356 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 1153 2357 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 1154 - #define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20 1155 - #define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT) 1156 2358 #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 1157 - #define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 1158 2359 #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 1159 2360 #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 1160 2361 #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 1161 2362 #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 1162 - #define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1163 - #define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1 1164 - #define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0 1165 - #define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT) 1166 - #define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1167 - #define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1 1168 - #define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0 1169 - #define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT) 1170 2363 #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 1171 - #define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0 1172 - #define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT) 1173 2364 #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 1174 - #define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0 1175 - #define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT) 1176 2365 #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 1177 - #define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3 1178 - #define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0 1179 - #define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT) 1180 2366 #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 1181 - #define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 1182 - #define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0 1183 - #define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT) 1184 2367 #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 1185 - #define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 1186 - #define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) 1187 - #define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1 1188 - #define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT) 1189 - #define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2 1190 - #define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT0_SHIFT) 1191 - #define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3 1192 - #define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT) 1193 2368 #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 1194 2369 #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 1195 2370 #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 1196 - #define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0 1197 - #define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT) 1198 - #define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1 1199 - #define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT1_SHIFT) 1200 - #define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2 1201 - #define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT) 1202 - #define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3 1203 - #define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT) 1204 - #define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1205 - #define I40E_PRTTSYN_TGT_H_MAX_INDEX 1 1206 - #define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0 1207 - #define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT) 1208 - #define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 1209 - #define I40E_PRTTSYN_TGT_L_MAX_INDEX 1 1210 - #define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0 1211 - #define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT) 1212 2371 #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 1213 - #define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0 1214 - #define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT) 1215 2372 #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 1216 - #define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 1217 - #define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) 1218 2373 #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 1219 - #define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 1220 - #define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) 1221 2374 #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 1222 - #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 1223 - #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) 1224 2375 #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 1225 2376 #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 1226 2377 #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) ··· 628 3033 #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 629 3034 #define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) 630 3035 #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 631 - #define I40E_VP_MDET_RX_MAX_INDEX 127 632 3036 #define I40E_VP_MDET_RX_VALID_SHIFT 0 633 3037 #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 634 3038 #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 635 - #define I40E_VP_MDET_TX_MAX_INDEX 127 636 3039 #define I40E_VP_MDET_TX_VALID_SHIFT 0 637 3040 #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) 638 - #define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */ 639 - #define I40E_GLPM_WUMC_NOTCO_SHIFT 0 640 - #define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT) 641 - #define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1 642 - #define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT) 643 - #define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2 644 - #define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_ROL_MODE_SHIFT) 645 - #define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3 646 - #define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT) 647 - #define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16 648 - #define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT) 649 3041 #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 650 3042 #define I40E_PFPM_APM_APME_SHIFT 0 651 3043 #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) 652 - #define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */ 653 - #define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7 654 - #define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0 655 - #define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT) 656 - #define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */ 657 - #define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5 658 - #define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT) 659 3044 #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 660 - #define I40E_PFPM_WUFC_LNKC_SHIFT 0 661 - #define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT) 662 3045 #define I40E_PFPM_WUFC_MAG_SHIFT 1 663 3046 #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT) 664 - #define I40E_PFPM_WUFC_MNG_SHIFT 3 665 - #define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MNG_SHIFT) 666 - #define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4 667 - #define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_ACT_SHIFT) 668 - #define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5 669 - #define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_ACT_SHIFT) 670 - #define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6 671 - #define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_ACT_SHIFT) 672 - #define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7 673 - #define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_ACT_SHIFT) 674 - #define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8 675 - #define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_ACT_SHIFT) 676 - #define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9 677 - #define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_ACT_SHIFT) 678 - #define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10 679 - #define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_ACT_SHIFT) 680 - #define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11 681 - #define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_ACT_SHIFT) 682 - #define I40E_PFPM_WUFC_FLX0_SHIFT 16 683 - #define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_SHIFT) 684 - #define I40E_PFPM_WUFC_FLX1_SHIFT 17 685 - #define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_SHIFT) 686 - #define I40E_PFPM_WUFC_FLX2_SHIFT 18 687 - #define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_SHIFT) 688 - #define I40E_PFPM_WUFC_FLX3_SHIFT 19 689 - #define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_SHIFT) 690 - #define I40E_PFPM_WUFC_FLX4_SHIFT 20 691 - #define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_SHIFT) 692 - #define I40E_PFPM_WUFC_FLX5_SHIFT 21 693 - #define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_SHIFT) 694 - #define I40E_PFPM_WUFC_FLX6_SHIFT 22 695 - #define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_SHIFT) 696 - #define I40E_PFPM_WUFC_FLX7_SHIFT 23 697 - #define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT) 698 - #define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31 699 - #define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT) 700 - #define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */ 701 - #define I40E_PFPM_WUS_LNKC_SHIFT 0 702 - #define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT) 703 - #define I40E_PFPM_WUS_MAG_SHIFT 1 704 - #define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MAG_SHIFT) 705 - #define I40E_PFPM_WUS_PME_STATUS_SHIFT 2 706 - #define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1, I40E_PFPM_WUS_PME_STATUS_SHIFT) 707 - #define I40E_PFPM_WUS_MNG_SHIFT 3 708 - #define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MNG_SHIFT) 709 - #define I40E_PFPM_WUS_FLX0_SHIFT 16 710 - #define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX0_SHIFT) 711 - #define I40E_PFPM_WUS_FLX1_SHIFT 17 712 - #define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX1_SHIFT) 713 - #define I40E_PFPM_WUS_FLX2_SHIFT 18 714 - #define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX2_SHIFT) 715 - #define I40E_PFPM_WUS_FLX3_SHIFT 19 716 - #define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX3_SHIFT) 717 - #define I40E_PFPM_WUS_FLX4_SHIFT 20 718 - #define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX4_SHIFT) 719 - #define I40E_PFPM_WUS_FLX5_SHIFT 21 720 - #define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX5_SHIFT) 721 - #define I40E_PFPM_WUS_FLX6_SHIFT 22 722 - #define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX6_SHIFT) 723 - #define I40E_PFPM_WUS_FLX7_SHIFT 23 724 - #define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT) 725 - #define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31 726 - #define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT) 727 - #define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */ 728 - #define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0 729 - #define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT) 730 - #define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1 731 - #define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT) 732 - #define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */ 733 - #define I40E_PRTPM_SAH_MAX_INDEX 3 734 - #define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0 735 - #define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT) 736 - #define I40E_PRTPM_SAH_PF_NUM_SHIFT 26 737 - #define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT) 738 - #define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30 739 - #define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT) 740 - #define I40E_PRTPM_SAH_AV_SHIFT 31 741 - #define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT) 742 - #define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */ 743 - #define I40E_PRTPM_SAL_MAX_INDEX 3 744 - #define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0 745 - #define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT) 746 3047 #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 747 - #define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 748 - #define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT) 749 3048 #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 750 - #define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 751 - #define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT) 752 3049 #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 753 - #define I40E_VF_ARQH1_ARQH_SHIFT 0 754 - #define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) 755 3050 #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 756 - #define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 757 - #define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) 758 - #define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 759 - #define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) 760 - #define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 761 - #define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 762 - #define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 763 - #define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 764 - #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 765 - #define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) 766 3051 #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 767 - #define I40E_VF_ARQT1_ARQT_SHIFT 0 768 - #define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) 769 3052 #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 770 - #define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 771 - #define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) 772 3053 #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 773 - #define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 774 - #define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT) 775 3054 #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 776 - #define I40E_VF_ATQH1_ATQH_SHIFT 0 777 - #define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT) 778 3055 #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 779 - #define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 780 - #define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) 781 - #define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 782 - #define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) 783 - #define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 784 - #define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 785 - #define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 786 - #define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 787 - #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 788 - #define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) 789 3056 #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 790 - #define I40E_VF_ATQT1_ATQT_SHIFT 0 791 - #define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) 792 - #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 793 - #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 794 - #define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 795 - #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 796 - #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 797 - #define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) 798 - #define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 799 - #define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) 800 - #define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 801 - #define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) 802 - #define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 803 - #define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) 804 - #define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 805 - #define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) 806 - #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 807 - #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) 808 - #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 809 - #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) 810 - #define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 811 - #define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) 812 - #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ 813 - #define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 814 - #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 815 - #define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) 816 - #define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 817 - #define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) 818 - #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 819 - #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) 820 - #define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 821 - #define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) 822 - #define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 823 - #define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) 824 - #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 825 - #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) 826 - #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 827 - #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) 828 - #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 829 - #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) 830 - #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ 831 - #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 832 - #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) 833 - #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 834 - #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) 835 - #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 836 - #define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) 837 - #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ 838 - #define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 839 - #define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT) 840 - #define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 841 - #define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT) 842 - #define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 843 - #define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT) 844 - #define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 845 - #define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT) 846 - #define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 847 - #define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT) 848 - #define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 849 - #define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) 850 - #define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 851 - #define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT) 852 - #define I40E_VFINT_ICR01_SWINT_SHIFT 31 853 - #define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT) 854 - #define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ 855 - #define I40E_VFINT_ITR01_MAX_INDEX 2 856 - #define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 857 - #define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) 858 - #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ 859 - #define I40E_VFINT_ITRN1_MAX_INDEX 2 860 - #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 861 - #define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) 862 - #define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ 863 - #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 864 - #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) 865 - #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ 866 - #define I40E_QRX_TAIL1_MAX_INDEX 15 867 - #define I40E_QRX_TAIL1_TAIL_SHIFT 0 868 - #define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) 869 - #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ 870 - #define I40E_QTX_TAIL1_MAX_INDEX 15 871 - #define I40E_QTX_TAIL1_TAIL_SHIFT 0 872 - #define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT) 873 - #define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ 874 - #define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 875 - #define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT) 876 - #define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 877 - #define I40E_VFMSIX_TADD_MAX_INDEX 16 878 - #define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 879 - #define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) 880 - #define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 881 - #define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT) 882 - #define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 883 - #define I40E_VFMSIX_TMSG_MAX_INDEX 16 884 - #define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 885 - #define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) 886 - #define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 887 - #define I40E_VFMSIX_TUADD_MAX_INDEX 16 888 - #define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 889 - #define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) 890 - #define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 891 - #define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 892 - #define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 893 - #define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT) 894 - #define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ 895 - #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 896 - #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) 897 - #define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 898 - #define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) 899 - #define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 900 - #define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) 901 - #define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ 902 - #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 903 - #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) 904 - #define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 905 - #define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) 906 - #define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 907 - #define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) 908 - #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 909 - #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) 910 - #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 911 - #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) 912 - #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 913 - #define I40E_VFQF_HENA_MAX_INDEX 1 914 - #define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 915 - #define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT) 916 - #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 917 - #define I40E_VFQF_HKEY_MAX_INDEX 12 918 - #define I40E_VFQF_HKEY_KEY_0_SHIFT 0 919 - #define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT) 920 - #define I40E_VFQF_HKEY_KEY_1_SHIFT 8 921 - #define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT) 922 - #define I40E_VFQF_HKEY_KEY_2_SHIFT 16 923 - #define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT) 924 - #define I40E_VFQF_HKEY_KEY_3_SHIFT 24 925 - #define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT) 926 - #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 927 3057 #define I40E_VFQF_HLUT_MAX_INDEX 15 928 - #define I40E_VFQF_HLUT_LUT0_SHIFT 0 929 - #define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT) 930 - #define I40E_VFQF_HLUT_LUT1_SHIFT 8 931 - #define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT) 932 - #define I40E_VFQF_HLUT_LUT2_SHIFT 16 933 - #define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT) 934 - #define I40E_VFQF_HLUT_LUT3_SHIFT 24 935 - #define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT) 936 - #define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ 937 - #define I40E_VFQF_HREGION_MAX_INDEX 7 938 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 939 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) 940 - #define I40E_VFQF_HREGION_REGION_0_SHIFT 1 941 - #define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT) 942 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 943 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) 944 - #define I40E_VFQF_HREGION_REGION_1_SHIFT 5 945 - #define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT) 946 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 947 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) 948 - #define I40E_VFQF_HREGION_REGION_2_SHIFT 9 949 - #define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT) 950 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 951 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) 952 - #define I40E_VFQF_HREGION_REGION_3_SHIFT 13 953 - #define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT) 954 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 955 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) 956 - #define I40E_VFQF_HREGION_REGION_4_SHIFT 17 957 - #define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT) 958 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 959 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) 960 - #define I40E_VFQF_HREGION_REGION_5_SHIFT 21 961 - #define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT) 962 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 963 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 964 - #define I40E_VFQF_HREGION_REGION_6_SHIFT 25 965 - #define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) 966 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 967 - #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 968 - #define I40E_VFQF_HREGION_REGION_7_SHIFT 29 969 - #define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) 970 3058 971 - #define I40E_MNGSB_FDCRC 0x000B7050 /* Reset: POR */ 972 - #define I40E_MNGSB_FDCRC_CRC_RES_SHIFT 0 973 - #define I40E_MNGSB_FDCRC_CRC_RES_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCRC_CRC_RES_SHIFT) 974 - #define I40E_MNGSB_FDCS 0x000B7040 /* Reset: POR */ 975 - #define I40E_MNGSB_FDCS_CRC_CONT_SHIFT 2 976 - #define I40E_MNGSB_FDCS_CRC_CONT_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_CONT_SHIFT) 977 - #define I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT 3 978 - #define I40E_MNGSB_FDCS_CRC_SEED_EN_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT) 979 - #define I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT 4 980 - #define I40E_MNGSB_FDCS_CRC_WR_INH_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT) 981 - #define I40E_MNGSB_FDCS_CRC_SEED_SHIFT 8 982 - #define I40E_MNGSB_FDCS_CRC_SEED_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCS_CRC_SEED_SHIFT) 983 - #define I40E_MNGSB_FDS 0x000B7048 /* Reset: POR */ 984 - #define I40E_MNGSB_FDS_START_BC_SHIFT 0 985 - #define I40E_MNGSB_FDS_START_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_START_BC_SHIFT) 986 - #define I40E_MNGSB_FDS_LAST_BC_SHIFT 16 987 - #define I40E_MNGSB_FDS_LAST_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_LAST_BC_SHIFT) 988 3059 989 - #define I40E_GL_VF_CTRL_RX(_VF) (0x00083600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 990 - #define I40E_GL_VF_CTRL_RX_MAX_INDEX 127 991 - #define I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT 0 992 - #define I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT) 993 - #define I40E_GL_VF_CTRL_TX(_VF) (0x00083400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 994 - #define I40E_GL_VF_CTRL_TX_MAX_INDEX 127 995 - #define I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT 0 996 - #define I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT) 997 3060 998 - #define I40E_GLCM_LAN_CACHESIZE 0x0010C4D8 /* Reset: CORER */ 999 - #define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT 0 1000 - #define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT) 1001 - #define I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT 12 1002 - #define I40E_GLCM_LAN_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT) 1003 - #define I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT 16 1004 - #define I40E_GLCM_LAN_CACHESIZE_WAYS_MASK I40E_MASK(0x3FF, I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT) 1005 - #define I40E_GLCM_PE_CACHESIZE 0x00138FE4 /* Reset: CORER */ 1006 - #define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT 0 1007 - #define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT) 1008 - #define I40E_GLCM_PE_CACHESIZE_SETS_SHIFT 12 1009 - #define I40E_GLCM_PE_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_PE_CACHESIZE_SETS_SHIFT) 1010 - #define I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT 16 1011 - #define I40E_GLCM_PE_CACHESIZE_WAYS_MASK I40E_MASK(0x1FF, I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT) 1012 - #define I40E_PFCM_PE_ERRDATA 0x00138D00 /* Reset: PFR */ 1013 - #define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 1014 - #define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT) 1015 - #define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 1016 - #define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT) 1017 - #define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8 1018 - #define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT) 1019 - #define I40E_PFCM_PE_ERRINFO 0x00138C80 /* Reset: PFR */ 1020 - #define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 1021 - #define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT) 1022 - #define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 1023 - #define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT) 1024 - #define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 1025 - #define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) 1026 - #define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 1027 - #define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) 1028 - #define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 1029 - #define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) 1030 3061 1031 - #define I40E_PRTDCB_TFMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 1032 - #define I40E_PRTDCB_TFMSTC_MAX_INDEX 7 1033 - #define I40E_PRTDCB_TFMSTC_MSTC_SHIFT 0 1034 - #define I40E_PRTDCB_TFMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TFMSTC_MSTC_SHIFT) 1035 - #define I40E_GL_FWSTS_FWROWD_SHIFT 8 1036 - #define I40E_GL_FWSTS_FWROWD_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWROWD_SHIFT) 1037 - #define I40E_GLFOC_CACHESIZE 0x000AA0DC /* Reset: CORER */ 1038 - #define I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT 0 1039 - #define I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT) 1040 - #define I40E_GLFOC_CACHESIZE_SETS_SHIFT 8 1041 - #define I40E_GLFOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLFOC_CACHESIZE_SETS_SHIFT) 1042 - #define I40E_GLFOC_CACHESIZE_WAYS_SHIFT 20 1043 - #define I40E_GLFOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLFOC_CACHESIZE_WAYS_SHIFT) 1044 - #define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1045 - #define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15 1046 - #define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0 1047 - #define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT) 1048 - #define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1049 - #define I40E_GLHMC_CEQPART_MAX_INDEX 15 1050 - #define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0 1051 - #define I40E_GLHMC_CEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT) 1052 - #define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16 1053 - #define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT) 1054 - #define I40E_GLHMC_DBCQMAX 0x000C20F0 /* Reset: CORER */ 1055 - #define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT 0 1056 - #define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK I40E_MASK(0x3FFFF, I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT) 1057 - #define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1058 - #define I40E_GLHMC_DBCQPART_MAX_INDEX 15 1059 - #define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0 1060 - #define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT) 1061 - #define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16 1062 - #define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT) 1063 - #define I40E_GLHMC_DBQPMAX 0x000C20EC /* Reset: CORER */ 1064 - #define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT 0 1065 - #define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK I40E_MASK(0x7FFFF, I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT) 1066 - #define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1067 - #define I40E_GLHMC_DBQPPART_MAX_INDEX 15 1068 - #define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0 1069 - #define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT) 1070 - #define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16 1071 - #define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT) 1072 - #define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1073 - #define I40E_GLHMC_PEARPBASE_MAX_INDEX 15 1074 - #define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0 1075 - #define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT) 1076 - #define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1077 - #define I40E_GLHMC_PEARPCNT_MAX_INDEX 15 1078 - #define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0 1079 - #define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT) 1080 - #define I40E_GLHMC_PEARPMAX 0x000C2038 /* Reset: CORER */ 1081 - #define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0 1082 - #define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT) 1083 - #define I40E_GLHMC_PEARPOBJSZ 0x000C2034 /* Reset: CORER */ 1084 - #define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0 1085 - #define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK I40E_MASK(0x7, I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT) 1086 - #define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1087 - #define I40E_GLHMC_PECQBASE_MAX_INDEX 15 1088 - #define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0 1089 - #define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT) 1090 - #define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1091 - #define I40E_GLHMC_PECQCNT_MAX_INDEX 15 1092 - #define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0 1093 - #define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT) 1094 - #define I40E_GLHMC_PECQOBJSZ 0x000C2020 /* Reset: CORER */ 1095 - #define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0 1096 - #define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT) 1097 - #define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1098 - #define I40E_GLHMC_PEHTCNT_MAX_INDEX 15 1099 - #define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0 1100 - #define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT) 1101 - #define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1102 - #define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15 1103 - #define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0 1104 - #define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT) 1105 - #define I40E_GLHMC_PEHTEOBJSZ 0x000C202c /* Reset: CORER */ 1106 - #define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0 1107 - #define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT) 1108 - #define I40E_GLHMC_PEHTMAX 0x000C2030 /* Reset: CORER */ 1109 - #define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0 1110 - #define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK I40E_MASK(0x1FFFFF, I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT) 1111 - #define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1112 - #define I40E_GLHMC_PEMRBASE_MAX_INDEX 15 1113 - #define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0 1114 - #define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT) 1115 - #define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1116 - #define I40E_GLHMC_PEMRCNT_MAX_INDEX 15 1117 - #define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0 1118 - #define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT) 1119 - #define I40E_GLHMC_PEMRMAX 0x000C2040 /* Reset: CORER */ 1120 - #define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0 1121 - #define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT) 1122 - #define I40E_GLHMC_PEMROBJSZ 0x000C203c /* Reset: CORER */ 1123 - #define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0 1124 - #define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT) 1125 - #define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1126 - #define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15 1127 - #define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0 1128 - #define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT) 1129 - #define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1130 - #define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15 1131 - #define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0 1132 - #define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT) 1133 - #define I40E_GLHMC_PEPBLMAX 0x000C206c /* Reset: CORER */ 1134 - #define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0 1135 - #define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT) 1136 - #define I40E_GLHMC_PEPFFIRSTSD 0x000C20E4 /* Reset: CORER */ 1137 - #define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT 0 1138 - #define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK I40E_MASK(0xFFF, I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT) 1139 - #define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1140 - #define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15 1141 - #define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0 1142 - #define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT) 1143 - #define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1144 - #define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15 1145 - #define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0 1146 - #define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT) 1147 - #define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1148 - #define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15 1149 - #define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0 1150 - #define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT) 1151 - #define I40E_GLHMC_PEQ1FLMAX 0x000C2058 /* Reset: CORER */ 1152 - #define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0 1153 - #define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT) 1154 - #define I40E_GLHMC_PEQ1MAX 0x000C2054 /* Reset: CORER */ 1155 - #define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0 1156 - #define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT) 1157 - #define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 /* Reset: CORER */ 1158 - #define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0 1159 - #define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT) 1160 - #define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1161 - #define I40E_GLHMC_PEQPBASE_MAX_INDEX 15 1162 - #define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0 1163 - #define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT) 1164 - #define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1165 - #define I40E_GLHMC_PEQPCNT_MAX_INDEX 15 1166 - #define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0 1167 - #define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT) 1168 - #define I40E_GLHMC_PEQPOBJSZ 0x000C201c /* Reset: CORER */ 1169 - #define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0 1170 - #define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT) 1171 - #define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1172 - #define I40E_GLHMC_PESRQBASE_MAX_INDEX 15 1173 - #define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0 1174 - #define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT) 1175 - #define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1176 - #define I40E_GLHMC_PESRQCNT_MAX_INDEX 15 1177 - #define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0 1178 - #define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT) 1179 - #define I40E_GLHMC_PESRQMAX 0x000C2028 /* Reset: CORER */ 1180 - #define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0 1181 - #define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT) 1182 - #define I40E_GLHMC_PESRQOBJSZ 0x000C2024 /* Reset: CORER */ 1183 - #define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0 1184 - #define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT) 1185 - #define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1186 - #define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15 1187 - #define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0 1188 - #define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT) 1189 - #define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1190 - #define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15 1191 - #define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0 1192 - #define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT) 1193 - #define I40E_GLHMC_PETIMERMAX 0x000C2084 /* Reset: CORER */ 1194 - #define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0 1195 - #define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT) 1196 - #define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 /* Reset: CORER */ 1197 - #define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0 1198 - #define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT) 1199 - #define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1200 - #define I40E_GLHMC_PEXFBASE_MAX_INDEX 15 1201 - #define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0 1202 - #define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT) 1203 - #define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1204 - #define I40E_GLHMC_PEXFCNT_MAX_INDEX 15 1205 - #define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0 1206 - #define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT) 1207 - #define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1208 - #define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15 1209 - #define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0 1210 - #define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT) 1211 - #define I40E_GLHMC_PEXFFLMAX 0x000C204c /* Reset: CORER */ 1212 - #define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0 1213 - #define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK I40E_MASK(0x1FFFFFF, I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT) 1214 - #define I40E_GLHMC_PEXFMAX 0x000C2048 /* Reset: CORER */ 1215 - #define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0 1216 - #define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT) 1217 - #define I40E_GLHMC_PEXFOBJSZ 0x000C2044 /* Reset: CORER */ 1218 - #define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0 1219 - #define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT) 1220 - #define I40E_GLHMC_PFPESDPART(_i) (0x000C0880 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1221 - #define I40E_GLHMC_PFPESDPART_MAX_INDEX 15 1222 - #define I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT 0 1223 - #define I40E_GLHMC_PFPESDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT) 1224 - #define I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT 16 1225 - #define I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT) 1226 - #define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1227 - #define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31 1228 - #define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0 1229 - #define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT) 1230 - #define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1231 - #define I40E_GLHMC_VFCEQPART_MAX_INDEX 31 1232 - #define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0 1233 - #define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT) 1234 - #define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16 1235 - #define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT) 1236 - #define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1237 - #define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31 1238 - #define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0 1239 - #define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT) 1240 - #define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16 1241 - #define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT) 1242 - #define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1243 - #define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31 1244 - #define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0 1245 - #define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT) 1246 - #define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16 1247 - #define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT) 1248 - #define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1249 - #define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31 1250 - #define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0 1251 - #define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT) 1252 - #define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1253 - #define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31 1254 - #define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0 1255 - #define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT) 1256 - #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1257 - #define I40E_GLHMC_VFPDINV_MAX_INDEX 31 1258 - #define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0 1259 - #define I40E_GLHMC_VFPDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT) 1260 - #define I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT 15 1261 - #define I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT) 1262 - #define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16 1263 - #define I40E_GLHMC_VFPDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT) 1264 - #define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1265 - #define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31 1266 - #define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0 1267 - #define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT) 1268 - #define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1269 - #define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31 1270 - #define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0 1271 - #define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT) 1272 - #define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1273 - #define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31 1274 - #define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0 1275 - #define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT) 1276 - #define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1277 - #define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31 1278 - #define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0 1279 - #define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT) 1280 - #define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1281 - #define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31 1282 - #define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0 1283 - #define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT) 1284 - #define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1285 - #define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31 1286 - #define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0 1287 - #define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT) 1288 - #define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1289 - #define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31 1290 - #define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0 1291 - #define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT) 1292 - #define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1293 - #define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31 1294 - #define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0 1295 - #define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT) 1296 - #define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1297 - #define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31 1298 - #define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0 1299 - #define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT) 1300 - #define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1301 - #define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31 1302 - #define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0 1303 - #define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT) 1304 - #define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1305 - #define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31 1306 - #define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0 1307 - #define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT) 1308 - #define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1309 - #define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31 1310 - #define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0 1311 - #define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT) 1312 - #define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1313 - #define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31 1314 - #define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0 1315 - #define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT) 1316 - #define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1317 - #define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31 1318 - #define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0 1319 - #define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT) 1320 - #define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1321 - #define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31 1322 - #define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0 1323 - #define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT) 1324 - #define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1325 - #define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31 1326 - #define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0 1327 - #define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT) 1328 - #define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1329 - #define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31 1330 - #define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0 1331 - #define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT) 1332 - #define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1333 - #define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31 1334 - #define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0 1335 - #define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT) 1336 - #define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1337 - #define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31 1338 - #define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0 1339 - #define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT) 1340 - #define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1341 - #define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31 1342 - #define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0 1343 - #define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT) 1344 - #define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1345 - #define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31 1346 - #define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0 1347 - #define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT) 1348 - #define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1349 - #define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31 1350 - #define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0 1351 - #define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT) 1352 - #define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1353 - #define I40E_GLHMC_VFSDPART_MAX_INDEX 31 1354 - #define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0 1355 - #define I40E_GLHMC_VFSDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT) 1356 - #define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16 1357 - #define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT) 1358 - #define I40E_GLPBLOC_CACHESIZE 0x000A80BC /* Reset: CORER */ 1359 - #define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT 0 1360 - #define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT) 1361 - #define I40E_GLPBLOC_CACHESIZE_SETS_SHIFT 8 1362 - #define I40E_GLPBLOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPBLOC_CACHESIZE_SETS_SHIFT) 1363 - #define I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT 20 1364 - #define I40E_GLPBLOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT) 1365 - #define I40E_GLPDOC_CACHESIZE 0x000D0088 /* Reset: CORER */ 1366 - #define I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT 0 1367 - #define I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT) 1368 - #define I40E_GLPDOC_CACHESIZE_SETS_SHIFT 8 1369 - #define I40E_GLPDOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPDOC_CACHESIZE_SETS_SHIFT) 1370 - #define I40E_GLPDOC_CACHESIZE_WAYS_SHIFT 20 1371 - #define I40E_GLPDOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPDOC_CACHESIZE_WAYS_SHIFT) 1372 - #define I40E_GLPEOC_CACHESIZE 0x000A60E8 /* Reset: CORER */ 1373 - #define I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT 0 1374 - #define I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT) 1375 - #define I40E_GLPEOC_CACHESIZE_SETS_SHIFT 8 1376 - #define I40E_GLPEOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPEOC_CACHESIZE_SETS_SHIFT) 1377 - #define I40E_GLPEOC_CACHESIZE_WAYS_SHIFT 20 1378 - #define I40E_GLPEOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPEOC_CACHESIZE_WAYS_SHIFT) 1379 - #define I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT 15 1380 - #define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT) 1381 - #define I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT 15 1382 - #define I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT) 1383 - #define I40E_GL_PPRS_SPARE 0x000856E0 /* Reset: CORER */ 1384 - #define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT 0 1385 - #define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT) 1386 - #define I40E_GL_TLAN_SPARE 0x000E64E0 /* Reset: CORER */ 1387 - #define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT 0 1388 - #define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT) 1389 - #define I40E_GL_TUPM_SPARE 0x000a2230 /* Reset: CORER */ 1390 - #define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT 0 1391 - #define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT) 1392 - #define I40E_GLGEN_CAR_DEBUG 0x000B81C0 /* Reset: POR */ 1393 - #define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT 0 1394 - #define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT) 1395 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT 1 1396 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT) 1397 - #define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT 2 1398 - #define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT) 1399 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT 3 1400 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT) 1401 - #define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT 4 1402 - #define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT) 1403 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT 5 1404 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT) 1405 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT 6 1406 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT) 1407 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT 7 1408 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT) 1409 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT 8 1410 - #define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT) 1411 - #define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT 9 1412 - #define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT) 1413 - #define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT 10 1414 - #define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT) 1415 - #define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT 11 1416 - #define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT) 1417 - #define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT 12 1418 - #define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT) 1419 - #define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT 13 1420 - #define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT) 1421 - #define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT 14 1422 - #define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT) 1423 - #define I40E_GLGEN_MISC_SPARE 0x000880E0 /* Reset: POR */ 1424 - #define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT 0 1425 - #define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT) 1426 - #define I40E_GL_UFUSE_SOC 0x000BE550 /* Reset: POR */ 1427 - #define I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT 0 1428 - #define I40E_GL_UFUSE_SOC_PORT_MODE_MASK I40E_MASK(0x3, I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT) 1429 - #define I40E_GL_UFUSE_SOC_NIC_ID_SHIFT 2 1430 - #define I40E_GL_UFUSE_SOC_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_SOC_NIC_ID_SHIFT) 1431 - #define I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT 3 1432 - #define I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK I40E_MASK(0x1FFF, I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT) 1433 3062 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 1434 3063 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 1435 3064 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 1436 3065 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 1437 - #define I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 1438 - #define I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 1439 - #define I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 1440 - #define I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 1441 - #define I40E_VPLAN_QBASE(_VF) (0x00074800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1442 - #define I40E_VPLAN_QBASE_MAX_INDEX 127 1443 - #define I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT 0 1444 - #define I40E_VPLAN_QBASE_VFFIRSTQ_MASK I40E_MASK(0x7FF, I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT) 1445 - #define I40E_VPLAN_QBASE_VFNUMQ_SHIFT 11 1446 - #define I40E_VPLAN_QBASE_VFNUMQ_MASK I40E_MASK(0xFF, I40E_VPLAN_QBASE_VFNUMQ_SHIFT) 1447 - #define I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT 31 1448 - #define I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT) 1449 - #define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */ 1450 - #define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT 0 1451 - #define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT) 1452 - #define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */ 1453 - #define I40E_GLNVM_AL_REQ_POR_SHIFT 0 1454 - #define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_POR_SHIFT) 1455 - #define I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT 1 1456 - #define I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT) 1457 - #define I40E_GLNVM_AL_REQ_GLOBR_SHIFT 2 1458 - #define I40E_GLNVM_AL_REQ_GLOBR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_GLOBR_SHIFT) 1459 - #define I40E_GLNVM_AL_REQ_CORER_SHIFT 3 1460 - #define I40E_GLNVM_AL_REQ_CORER_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_CORER_SHIFT) 1461 - #define I40E_GLNVM_AL_REQ_PE_SHIFT 4 1462 - #define I40E_GLNVM_AL_REQ_PE_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PE_SHIFT) 1463 - #define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT 5 1464 - #define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT) 1465 - #define I40E_GLNVM_ALTIMERS 0x000B6140 /* Reset: POR */ 1466 - #define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT 0 1467 - #define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT) 1468 - #define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT 12 1469 - #define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT) 1470 3066 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 1471 3067 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 1472 3068 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 1473 3069 1474 3070 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1475 - #define I40E_GLNVM_ULD_PCIER_DONE_SHIFT 0 1476 - #define I40E_GLNVM_ULD_PCIER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_SHIFT) 1477 - #define I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT 1 1478 - #define I40E_GLNVM_ULD_PCIER_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT) 1479 - #define I40E_GLNVM_ULD_CORER_DONE_SHIFT 3 1480 - #define I40E_GLNVM_ULD_CORER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CORER_DONE_SHIFT) 1481 - #define I40E_GLNVM_ULD_GLOBR_DONE_SHIFT 4 1482 - #define I40E_GLNVM_ULD_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_GLOBR_DONE_SHIFT) 1483 - #define I40E_GLNVM_ULD_POR_DONE_SHIFT 5 1484 - #define I40E_GLNVM_ULD_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_SHIFT) 1485 - #define I40E_GLNVM_ULD_POR_DONE_1_SHIFT 8 1486 - #define I40E_GLNVM_ULD_POR_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_1_SHIFT) 1487 - #define I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT 9 1488 - #define I40E_GLNVM_ULD_PCIER_DONE_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT) 1489 - #define I40E_GLNVM_ULD_PE_DONE_SHIFT 10 1490 - #define I40E_GLNVM_ULD_PE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PE_DONE_SHIFT) 1491 - #define I40E_GLNVM_ULT 0x000B6154 /* Reset: POR */ 1492 - #define I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT 0 1493 - #define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT) 1494 - #define I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT 1 1495 - #define I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT) 1496 - #define I40E_GLNVM_ULT_RESERVED_1_SHIFT 2 1497 - #define I40E_GLNVM_ULT_RESERVED_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_1_SHIFT) 1498 - #define I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT 3 1499 - #define I40E_GLNVM_ULT_CONF_CORE_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT) 1500 - #define I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT 4 1501 - #define I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT) 1502 - #define I40E_GLNVM_ULT_CONF_POR_AE_SHIFT 5 1503 - #define I40E_GLNVM_ULT_CONF_POR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_POR_AE_SHIFT) 1504 - #define I40E_GLNVM_ULT_RESERVED_2_SHIFT 6 1505 - #define I40E_GLNVM_ULT_RESERVED_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_2_SHIFT) 1506 - #define I40E_GLNVM_ULT_RESERVED_3_SHIFT 7 1507 - #define I40E_GLNVM_ULT_RESERVED_3_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_3_SHIFT) 1508 - #define I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT 8 1509 - #define I40E_GLNVM_ULT_CONF_EMP_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT) 1510 - #define I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT 9 1511 - #define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT) 1512 - #define I40E_GLNVM_ULT_RESERVED_4_SHIFT 10 1513 - #define I40E_GLNVM_ULT_RESERVED_4_MASK I40E_MASK(0x3FFFFF, I40E_GLNVM_ULT_RESERVED_4_SHIFT) 1514 - #define I40E_MEM_INIT_DONE_STAT 0x000B615C /* Reset: POR */ 1515 - #define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT 0 1516 - #define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT) 1517 - #define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT 1 1518 - #define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT) 1519 - #define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT 2 1520 - #define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT) 1521 - #define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT 3 1522 - #define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT) 1523 - #define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT 4 1524 - #define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT) 1525 - #define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT 5 1526 - #define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT) 1527 - #define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT 6 1528 - #define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT) 1529 - #define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT 7 1530 - #define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT) 1531 - #define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT 8 1532 - #define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT) 1533 - #define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT 9 1534 - #define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT) 1535 - #define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT 10 1536 - #define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT) 1537 - #define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT 11 1538 - #define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT) 1539 - #define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT 12 1540 - #define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT) 1541 - #define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT 13 1542 - #define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT) 1543 - #define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT 14 1544 - #define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT) 1545 - #define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT 15 1546 - #define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT) 1547 - #define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT 16 1548 - #define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT) 1549 - #define I40E_MNGSB_DADD 0x000B7030 /* Reset: POR */ 1550 - #define I40E_MNGSB_DADD_ADDR_SHIFT 0 1551 - #define I40E_MNGSB_DADD_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DADD_ADDR_SHIFT) 1552 - #define I40E_MNGSB_DCNT 0x000B7034 /* Reset: POR */ 1553 - #define I40E_MNGSB_DCNT_BYTE_CNT_SHIFT 0 1554 - #define I40E_MNGSB_DCNT_BYTE_CNT_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DCNT_BYTE_CNT_SHIFT) 1555 - #define I40E_MNGSB_MSGCTL 0x000B7020 /* Reset: POR */ 1556 - #define I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT 0 1557 - #define I40E_MNGSB_MSGCTL_HDR_DWS_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT) 1558 - #define I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT 8 1559 - #define I40E_MNGSB_MSGCTL_EXP_RDW_MASK I40E_MASK(0x1FF, I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT) 1560 - #define I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT 26 1561 - #define I40E_MNGSB_MSGCTL_MSG_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT) 1562 - #define I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT 28 1563 - #define I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT) 1564 - #define I40E_MNGSB_MSGCTL_BARCLR_SHIFT 30 1565 - #define I40E_MNGSB_MSGCTL_BARCLR_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_BARCLR_SHIFT) 1566 - #define I40E_MNGSB_MSGCTL_CMDV_SHIFT 31 1567 - #define I40E_MNGSB_MSGCTL_CMDV_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_CMDV_SHIFT) 1568 - #define I40E_MNGSB_RDATA 0x000B7300 /* Reset: POR */ 1569 - #define I40E_MNGSB_RDATA_DATA_SHIFT 0 1570 - #define I40E_MNGSB_RDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_RDATA_DATA_SHIFT) 1571 - #define I40E_MNGSB_RHDR0 0x000B72FC /* Reset: POR */ 1572 - #define I40E_MNGSB_RHDR0_DESTINATION_SHIFT 0 1573 - #define I40E_MNGSB_RHDR0_DESTINATION_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_DESTINATION_SHIFT) 1574 - #define I40E_MNGSB_RHDR0_SOURCE_SHIFT 8 1575 - #define I40E_MNGSB_RHDR0_SOURCE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_SOURCE_SHIFT) 1576 - #define I40E_MNGSB_RHDR0_OPCODE_SHIFT 16 1577 - #define I40E_MNGSB_RHDR0_OPCODE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_OPCODE_SHIFT) 1578 - #define I40E_MNGSB_RHDR0_TAG_SHIFT 24 1579 - #define I40E_MNGSB_RHDR0_TAG_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_TAG_SHIFT) 1580 - #define I40E_MNGSB_RHDR0_RESPONSE_SHIFT 27 1581 - #define I40E_MNGSB_RHDR0_RESPONSE_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_RESPONSE_SHIFT) 1582 - #define I40E_MNGSB_RHDR0_EH_SHIFT 31 1583 - #define I40E_MNGSB_RHDR0_EH_MASK I40E_MASK(0x1, I40E_MNGSB_RHDR0_EH_SHIFT) 1584 - #define I40E_MNGSB_RSPCTL 0x000B7024 /* Reset: POR */ 1585 - #define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT 0 1586 - #define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK I40E_MASK(0x1FF, I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT) 1587 - #define I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT 26 1588 - #define I40E_MNGSB_RSPCTL_RSP_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT) 1589 - #define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT 30 1590 - #define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT) 1591 - #define I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT 31 1592 - #define I40E_MNGSB_RSPCTL_RSP_ERR_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT) 1593 - #define I40E_MNGSB_WDATA 0x000B7100 /* Reset: POR */ 1594 - #define I40E_MNGSB_WDATA_DATA_SHIFT 0 1595 - #define I40E_MNGSB_WDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WDATA_DATA_SHIFT) 1596 - #define I40E_MNGSB_WHDR0 0x000B70F4 /* Reset: POR */ 1597 - #define I40E_MNGSB_WHDR0_RAW_DEST_SHIFT 0 1598 - #define I40E_MNGSB_WHDR0_RAW_DEST_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_RAW_DEST_SHIFT) 1599 - #define I40E_MNGSB_WHDR0_DEST_SEL_SHIFT 12 1600 - #define I40E_MNGSB_WHDR0_DEST_SEL_MASK I40E_MASK(0xF, I40E_MNGSB_WHDR0_DEST_SEL_SHIFT) 1601 - #define I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT 16 1602 - #define I40E_MNGSB_WHDR0_OPCODE_SEL_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT) 1603 - #define I40E_MNGSB_WHDR0_TAG_SHIFT 24 1604 - #define I40E_MNGSB_WHDR0_TAG_MASK I40E_MASK(0x7F, I40E_MNGSB_WHDR0_TAG_SHIFT) 1605 - #define I40E_MNGSB_WHDR1 0x000B70F8 /* Reset: POR */ 1606 - #define I40E_MNGSB_WHDR1_ADDR_SHIFT 0 1607 - #define I40E_MNGSB_WHDR1_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR1_ADDR_SHIFT) 1608 - #define I40E_MNGSB_WHDR2 0x000B70FC /* Reset: POR */ 1609 - #define I40E_MNGSB_WHDR2_LENGTH_SHIFT 0 1610 - #define I40E_MNGSB_WHDR2_LENGTH_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR2_LENGTH_SHIFT) 1611 3071 1612 - #define I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT 21 1613 - #define I40E_GLPCI_CAPSUP_WAKUP_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT) 1614 3072 1615 - #define I40E_GLPCI_CUR_CLNT_COMMON 0x0009CA18 /* Reset: PCIR */ 1616 - #define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT 0 1617 - #define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT) 1618 - #define I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT 16 1619 - #define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT) 1620 - #define I40E_GLPCI_CUR_CLNT_PIPEMON 0x0009CA20 /* Reset: PCIR */ 1621 - #define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT 0 1622 - #define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT) 1623 - #define I40E_GLPCI_CUR_MNG_ALWD 0x0009c514 /* Reset: PCIR */ 1624 - #define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT 0 1625 - #define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT) 1626 - #define I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT 16 1627 - #define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT) 1628 - #define I40E_GLPCI_CUR_MNG_RSVD 0x0009c594 /* Reset: PCIR */ 1629 - #define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT 0 1630 - #define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT) 1631 - #define I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT 16 1632 - #define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT) 1633 - #define I40E_GLPCI_CUR_PMAT_ALWD 0x0009c510 /* Reset: PCIR */ 1634 - #define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT 0 1635 - #define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT) 1636 - #define I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT 16 1637 - #define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT) 1638 - #define I40E_GLPCI_CUR_PMAT_RSVD 0x0009c590 /* Reset: PCIR */ 1639 - #define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT 0 1640 - #define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT) 1641 - #define I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT 16 1642 - #define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT) 1643 - #define I40E_GLPCI_CUR_RLAN_ALWD 0x0009c500 /* Reset: PCIR */ 1644 - #define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT 0 1645 - #define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT) 1646 - #define I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT 16 1647 - #define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT) 1648 - #define I40E_GLPCI_CUR_RLAN_RSVD 0x0009c580 /* Reset: PCIR */ 1649 - #define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT 0 1650 - #define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT) 1651 - #define I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT 16 1652 - #define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT) 1653 - #define I40E_GLPCI_CUR_RXPE_ALWD 0x0009c508 /* Reset: PCIR */ 1654 - #define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT 0 1655 - #define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT) 1656 - #define I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT 16 1657 - #define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT) 1658 - #define I40E_GLPCI_CUR_RXPE_RSVD 0x0009c588 /* Reset: PCIR */ 1659 - #define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT 0 1660 - #define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT) 1661 - #define I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT 16 1662 - #define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT) 1663 - #define I40E_GLPCI_CUR_TDPU_ALWD 0x0009c518 /* Reset: PCIR */ 1664 - #define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT 0 1665 - #define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT) 1666 - #define I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT 16 1667 - #define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT) 1668 - #define I40E_GLPCI_CUR_TDPU_RSVD 0x0009c598 /* Reset: PCIR */ 1669 - #define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT 0 1670 - #define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT) 1671 - #define I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT 16 1672 - #define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT) 1673 - #define I40E_GLPCI_CUR_TLAN_ALWD 0x0009c504 /* Reset: PCIR */ 1674 - #define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT 0 1675 - #define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT) 1676 - #define I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT 16 1677 - #define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT) 1678 - #define I40E_GLPCI_CUR_TLAN_RSVD 0x0009c584 /* Reset: PCIR */ 1679 - #define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT 0 1680 - #define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT) 1681 - #define I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT 16 1682 - #define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT) 1683 - #define I40E_GLPCI_CUR_TXPE_ALWD 0x0009c50C /* Reset: PCIR */ 1684 - #define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT 0 1685 - #define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT) 1686 - #define I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT 16 1687 - #define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT) 1688 - #define I40E_GLPCI_CUR_TXPE_RSVD 0x0009c58c /* Reset: PCIR */ 1689 - #define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT 0 1690 - #define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT) 1691 - #define I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT 16 1692 - #define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT) 1693 - #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON 0x0009CA28 /* Reset: PCIR */ 1694 - #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT 0 1695 - #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT) 1696 - #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT 16 1697 - #define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT) 1698 3073 1699 - #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4 1700 - #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT) 1701 - #define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10 1702 - #define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT) 1703 - #define I40E_GLPCI_NPQ_CFG 0x0009CA00 /* Reset: PCIR */ 1704 - #define I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT 0 1705 - #define I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT) 1706 - #define I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT 1 1707 - #define I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT) 1708 - #define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT 2 1709 - #define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT) 1710 - #define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT 6 1711 - #define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK I40E_MASK(0x3FF, I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT) 1712 - #define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT 16 1713 - #define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT) 1714 - #define I40E_GLPCI_WATMK_CLNT_PIPEMON 0x0009CA30 /* Reset: PCIR */ 1715 - #define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT 0 1716 - #define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT) 1717 - #define I40E_GLPCI_WATMK_MNG_ALWD 0x0009CB14 /* Reset: PCIR */ 1718 - #define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT 0 1719 - #define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT) 1720 - #define I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT 16 1721 - #define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT) 1722 - #define I40E_GLPCI_WATMK_PMAT_ALWD 0x0009CB10 /* Reset: PCIR */ 1723 - #define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT 0 1724 - #define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT) 1725 - #define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT 16 1726 - #define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT) 1727 - #define I40E_GLPCI_WATMK_RLAN_ALWD 0x0009CB00 /* Reset: PCIR */ 1728 - #define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT 0 1729 - #define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT) 1730 - #define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT 16 1731 - #define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT) 1732 - #define I40E_GLPCI_WATMK_RXPE_ALWD 0x0009CB08 /* Reset: PCIR */ 1733 - #define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT 0 1734 - #define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT) 1735 - #define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT 16 1736 - #define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT) 1737 - #define I40E_GLPCI_WATMK_TLAN_ALWD 0x0009CB04 /* Reset: PCIR */ 1738 - #define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT 0 1739 - #define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT) 1740 - #define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT 16 1741 - #define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT) 1742 - #define I40E_GLPCI_WATMK_TPDU_ALWD 0x0009CB18 /* Reset: PCIR */ 1743 - #define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT 0 1744 - #define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT) 1745 - #define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT 16 1746 - #define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT) 1747 - #define I40E_GLPCI_WATMK_TXPE_ALWD 0x0009CB0c /* Reset: PCIR */ 1748 - #define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT 0 1749 - #define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT) 1750 - #define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT 16 1751 - #define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT) 1752 - #define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */ 1753 - #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0 1754 - #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT) 1755 - #define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */ 1756 - #define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0 1757 - #define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT) 1758 - #define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */ 1759 - #define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0 1760 - #define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT) 1761 - #define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */ 1762 - #define I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT 0 1763 - #define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK I40E_MASK(0xFFFF, I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT) 1764 - #define I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT 17 1765 - #define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT) 1766 - #define I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT 18 1767 - #define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT) 1768 - #define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */ 1769 - #define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT 0 1770 - #define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK I40E_MASK(0x1, I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT) 1771 - #define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1772 - #define I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX 15 1773 - #define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0 1774 - #define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT) 1775 - #define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1776 - #define I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX 15 1777 - #define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0 1778 - #define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT) 1779 - #define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1780 - #define I40E_GLPE_PFCQEDROPCNT_MAX_INDEX 15 1781 - #define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT 0 1782 - #define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT) 1783 - #define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */ 1784 - #define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT 0 1785 - #define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT) 1786 - #define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */ 1787 - #define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT 0 1788 - #define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT) 1789 - #define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */ 1790 - #define I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT 0 1791 - #define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT) 1792 - #define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT 26 1793 - #define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT) 1794 - #define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT 27 1795 - #define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT) 1796 - #define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT 28 1797 - #define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT) 1798 - #define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT 29 1799 - #define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT) 1800 - #define I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT 30 1801 - #define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT) 1802 - #define I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT 31 1803 - #define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT) 1804 - #define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */ 1805 - #define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT 0 1806 - #define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT) 1807 - #define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */ 1808 - #define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT 0 1809 - #define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT) 1810 - #define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */ 1811 - #define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT 0 1812 - #define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT) 1813 - #define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1814 - #define I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX 31 1815 - #define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0 1816 - #define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT) 1817 - #define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1818 - #define I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX 31 1819 - #define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0 1820 - #define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT) 1821 - #define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 1822 - #define I40E_GLPE_VFCQEDROPCNT_MAX_INDEX 31 1823 - #define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT 0 1824 - #define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT) 1825 - #define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 1826 - #define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31 1827 - #define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0 1828 - #define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT) 1829 - #define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8 1830 - #define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT) 1831 - #define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 1832 - #define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31 1833 - #define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 1834 - #define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT) 1835 - #define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 1836 - #define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31 1837 - #define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 1838 - #define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT) 1839 - #define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 1840 - #define I40E_GLPE_VFUDACTRL_MAX_INDEX 31 1841 - #define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0 1842 - #define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT) 1843 - #define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1 1844 - #define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT) 1845 - #define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2 1846 - #define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT) 1847 - #define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3 1848 - #define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT) 1849 - #define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 1850 - #define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT) 1851 - #define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 1852 - #define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31 1853 - #define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0 1854 - #define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT) 1855 - #define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31 1856 - #define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT) 1857 - #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */ 1858 - #define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0 1859 - #define I40E_PFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_AEQALLOC_AECOUNT_SHIFT) 1860 - #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */ 1861 - #define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 1862 - #define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT) 1863 - #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */ 1864 - #define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0 1865 - #define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT) 1866 - #define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */ 1867 - #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 1868 - #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT) 1869 - #define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4 1870 - #define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT) 1871 - #define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16 1872 - #define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT) 1873 - #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 1874 - #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT) 1875 - #define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */ 1876 - #define I40E_PFPE_CQACK_PECQID_SHIFT 0 1877 - #define I40E_PFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQACK_PECQID_SHIFT) 1878 - #define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */ 1879 - #define I40E_PFPE_CQARM_PECQID_SHIFT 0 1880 - #define I40E_PFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQARM_PECQID_SHIFT) 1881 - #define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */ 1882 - #define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0 1883 - #define I40E_PFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPDB_WQHEAD_SHIFT) 1884 - #define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */ 1885 - #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 1886 - #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) 1887 - #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 1888 - #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) 1889 - #define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */ 1890 - #define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0 1891 - #define I40E_PFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT) 1892 - #define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 1893 - #define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT) 1894 - #define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */ 1895 - #define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 1896 - #define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT) 1897 - #define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */ 1898 - #define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 1899 - #define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT) 1900 - #define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */ 1901 - #define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0 1902 - #define I40E_PFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_PFPE_IPCONFIG0_PEIPID_SHIFT) 1903 - #define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 1904 - #define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) 1905 - #define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */ 1906 - #define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 1907 - #define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) 1908 - #define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */ 1909 - #define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 1910 - #define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) 1911 - #define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */ 1912 - #define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 1913 - #define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT) 1914 - #define I40E_PFPE_UDACTRL 0x00008700 /* Reset: PFR */ 1915 - #define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0 1916 - #define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT) 1917 - #define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1 1918 - #define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT) 1919 - #define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2 1920 - #define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT) 1921 - #define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3 1922 - #define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT) 1923 - #define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 1924 - #define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT) 1925 - #define I40E_PFPE_UDAUCFBQPN 0x00008780 /* Reset: PFR */ 1926 - #define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0 1927 - #define I40E_PFPE_UDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_PFPE_UDAUCFBQPN_QPN_SHIFT) 1928 - #define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31 1929 - #define I40E_PFPE_UDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_PFPE_UDAUCFBQPN_VALID_SHIFT) 1930 - #define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */ 1931 - #define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0 1932 - #define I40E_PFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_PFPE_WQEALLOC_PEQPID_SHIFT) 1933 - #define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 1934 - #define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) 1935 - #define I40E_PRTDCB_RLPMC 0x0001F140 /* Reset: PE_CORER */ 1936 - #define I40E_PRTDCB_RLPMC_TC2PFC_SHIFT 0 1937 - #define I40E_PRTDCB_RLPMC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RLPMC_TC2PFC_SHIFT) 1938 - #define I40E_PRTDCB_TCMSTC_RLPM(_i) (0x0001F040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: PE_CORER */ 1939 - #define I40E_PRTDCB_TCMSTC_RLPM_MAX_INDEX 7 1940 - #define I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT 0 1941 - #define I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT) 1942 - #define I40E_PRTDCB_TCPMC_RLPM 0x0001F1A0 /* Reset: PE_CORER */ 1943 - #define I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT 0 1944 - #define I40E_PRTDCB_TCPMC_RLPM_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT) 1945 - #define I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT 13 1946 - #define I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT) 1947 - #define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT 30 1948 - #define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT) 1949 - #define I40E_PRTE_RUPM_TCCNTR03 0x0000DAE0 /* Reset: PE_CORER */ 1950 - #define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT 0 1951 - #define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT) 1952 - #define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT 8 1953 - #define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT) 1954 - #define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT 16 1955 - #define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT) 1956 - #define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT 24 1957 - #define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT) 1958 - #define I40E_PRTPE_RUPM_CNTR 0x0000DB20 /* Reset: PE_CORER */ 1959 - #define I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT 0 1960 - #define I40E_PRTPE_RUPM_CNTR_COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT) 1961 - #define I40E_PRTPE_RUPM_CTL 0x0000DA40 /* Reset: PE_CORER */ 1962 - #define I40E_PRTPE_RUPM_CTL_LLTC_SHIFT 13 1963 - #define I40E_PRTPE_RUPM_CTL_LLTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CTL_LLTC_SHIFT) 1964 - #define I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT 30 1965 - #define I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT) 1966 - #define I40E_PRTPE_RUPM_PFCCTL 0x0000DA60 /* Reset: PE_CORER */ 1967 - #define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT 0 1968 - #define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT) 1969 - #define I40E_PRTPE_RUPM_PFCPC 0x0000DA80 /* Reset: PE_CORER */ 1970 - #define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT 0 1971 - #define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT) 1972 - #define I40E_PRTPE_RUPM_PFCTCC 0x0000DAA0 /* Reset: PE_CORER */ 1973 - #define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT 0 1974 - #define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT) 1975 - #define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT 16 1976 - #define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT) 1977 - #define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT 31 1978 - #define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT) 1979 - #define I40E_PRTPE_RUPM_PTCTCCNTR47 0x0000DB60 /* Reset: PE_CORER */ 1980 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT 0 1981 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT) 1982 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT 8 1983 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT) 1984 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT 16 1985 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT) 1986 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT 24 1987 - #define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT) 1988 - #define I40E_PRTPE_RUPM_PTXTCCNTR03 0x0000DB40 /* Reset: PE_CORER */ 1989 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT 0 1990 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT) 1991 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT 8 1992 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT) 1993 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT 16 1994 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT) 1995 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT 24 1996 - #define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT) 1997 - #define I40E_PRTPE_RUPM_TCCNTR47 0x0000DB00 /* Reset: PE_CORER */ 1998 - #define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT 0 1999 - #define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT) 2000 - #define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT 8 2001 - #define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT) 2002 - #define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT 16 2003 - #define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT) 2004 - #define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT 24 2005 - #define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT) 2006 - #define I40E_PRTPE_RUPM_THRES 0x0000DA20 /* Reset: PE_CORER */ 2007 - #define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT 0 2008 - #define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT) 2009 - #define I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT 8 2010 - #define I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT) 2011 - #define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT 16 2012 - #define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT) 2013 - #define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2014 - #define I40E_VFPE_AEQALLOC_MAX_INDEX 127 2015 - #define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0 2016 - #define I40E_VFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC_AECOUNT_SHIFT) 2017 - #define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2018 - #define I40E_VFPE_CCQPHIGH_MAX_INDEX 127 2019 - #define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 2020 - #define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT) 2021 - #define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2022 - #define I40E_VFPE_CCQPLOW_MAX_INDEX 127 2023 - #define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0 2024 - #define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT) 2025 - #define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2026 - #define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127 2027 - #define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 2028 - #define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT) 2029 - #define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4 2030 - #define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT) 2031 - #define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16 2032 - #define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT) 2033 - #define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 2034 - #define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT) 2035 - #define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2036 - #define I40E_VFPE_CQACK_MAX_INDEX 127 2037 - #define I40E_VFPE_CQACK_PECQID_SHIFT 0 2038 - #define I40E_VFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK_PECQID_SHIFT) 2039 - #define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2040 - #define I40E_VFPE_CQARM_MAX_INDEX 127 2041 - #define I40E_VFPE_CQARM_PECQID_SHIFT 0 2042 - #define I40E_VFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM_PECQID_SHIFT) 2043 - #define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2044 - #define I40E_VFPE_CQPDB_MAX_INDEX 127 2045 - #define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0 2046 - #define I40E_VFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB_WQHEAD_SHIFT) 2047 - #define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2048 - #define I40E_VFPE_CQPERRCODES_MAX_INDEX 127 2049 - #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 2050 - #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) 2051 - #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 2052 - #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) 2053 - #define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2054 - #define I40E_VFPE_CQPTAIL_MAX_INDEX 127 2055 - #define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0 2056 - #define I40E_VFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL_WQTAIL_SHIFT) 2057 - #define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 2058 - #define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT) 2059 - #define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2060 - #define I40E_VFPE_IPCONFIG0_MAX_INDEX 127 2061 - #define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0 2062 - #define I40E_VFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG0_PEIPID_SHIFT) 2063 - #define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 2064 - #define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) 2065 - #define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2066 - #define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127 2067 - #define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 2068 - #define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) 2069 - #define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2070 - #define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127 2071 - #define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 2072 - #define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) 2073 - #define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2074 - #define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127 2075 - #define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 2076 - #define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT) 2077 - #define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2078 - #define I40E_VFPE_WQEALLOC_MAX_INDEX 127 2079 - #define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0 2080 - #define I40E_VFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC_PEQPID_SHIFT) 2081 - #define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 2082 - #define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) 2083 - #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2084 - #define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15 2085 - #define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 2086 - #define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT) 2087 - #define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2088 - #define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15 2089 - #define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 2090 - #define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) 2091 - #define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2092 - #define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15 2093 - #define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 2094 - #define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) 2095 - #define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2096 - #define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15 2097 - #define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 2098 - #define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) 2099 - #define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2100 - #define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15 2101 - #define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 2102 - #define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) 2103 - #define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2104 - #define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15 2105 - #define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 2106 - #define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) 2107 - #define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2108 - #define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15 2109 - #define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 2110 - #define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) 2111 - #define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2112 - #define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15 2113 - #define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 2114 - #define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) 2115 - #define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2116 - #define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15 2117 - #define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 2118 - #define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) 2119 - #define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2120 - #define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15 2121 - #define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 2122 - #define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) 2123 - #define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2124 - #define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15 2125 - #define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 2126 - #define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) 2127 - #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2128 - #define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15 2129 - #define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 2130 - #define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT) 2131 - #define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2132 - #define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15 2133 - #define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 2134 - #define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) 2135 - #define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2136 - #define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15 2137 - #define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 2138 - #define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) 2139 - #define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2140 - #define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15 2141 - #define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 2142 - #define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) 2143 - #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2144 - #define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15 2145 - #define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 2146 - #define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) 2147 - #define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2148 - #define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15 2149 - #define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 2150 - #define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) 2151 - #define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2152 - #define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15 2153 - #define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 2154 - #define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) 2155 - #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2156 - #define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15 2157 - #define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 2158 - #define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) 2159 - #define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2160 - #define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15 2161 - #define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 2162 - #define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) 2163 - #define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2164 - #define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15 2165 - #define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 2166 - #define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) 2167 - #define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2168 - #define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15 2169 - #define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 2170 - #define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) 2171 - #define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2172 - #define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15 2173 - #define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 2174 - #define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) 2175 - #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2176 - #define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15 2177 - #define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 2178 - #define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT) 2179 - #define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2180 - #define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15 2181 - #define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 2182 - #define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) 2183 - #define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2184 - #define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15 2185 - #define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 2186 - #define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) 2187 - #define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2188 - #define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15 2189 - #define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 2190 - #define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) 2191 - #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2192 - #define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15 2193 - #define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 2194 - #define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) 2195 - #define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2196 - #define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15 2197 - #define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 2198 - #define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) 2199 - #define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2200 - #define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15 2201 - #define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 2202 - #define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) 2203 - #define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2204 - #define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15 2205 - #define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 2206 - #define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) 2207 - #define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2208 - #define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15 2209 - #define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 2210 - #define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) 2211 - #define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2212 - #define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15 2213 - #define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 2214 - #define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) 2215 - #define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2216 - #define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15 2217 - #define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 2218 - #define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) 2219 - #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2220 - #define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15 2221 - #define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 2222 - #define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT) 2223 - #define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2224 - #define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15 2225 - #define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 2226 - #define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) 2227 - #define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2228 - #define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15 2229 - #define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 2230 - #define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) 2231 - #define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2232 - #define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15 2233 - #define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 2234 - #define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) 2235 - #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2236 - #define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15 2237 - #define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 2238 - #define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) 2239 - #define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2240 - #define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15 2241 - #define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 2242 - #define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) 2243 - #define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2244 - #define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15 2245 - #define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 2246 - #define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) 2247 - #define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2248 - #define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15 2249 - #define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 2250 - #define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) 2251 - #define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2252 - #define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15 2253 - #define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 2254 - #define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) 2255 - #define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2256 - #define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15 2257 - #define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 2258 - #define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) 2259 - #define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2260 - #define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15 2261 - #define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 2262 - #define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) 2263 - #define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2264 - #define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15 2265 - #define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 2266 - #define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) 2267 - #define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2268 - #define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15 2269 - #define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 2270 - #define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT) 2271 - #define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2272 - #define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15 2273 - #define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 2274 - #define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT) 2275 - #define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2276 - #define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15 2277 - #define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 2278 - #define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) 2279 - #define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2280 - #define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15 2281 - #define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 2282 - #define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) 2283 - #define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2284 - #define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15 2285 - #define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 2286 - #define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT) 2287 - #define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2288 - #define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15 2289 - #define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 2290 - #define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT) 2291 - #define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2292 - #define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15 2293 - #define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 2294 - #define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT) 2295 - #define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2296 - #define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15 2297 - #define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 2298 - #define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT) 2299 - #define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2300 - #define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15 2301 - #define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 2302 - #define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) 2303 - #define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2304 - #define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15 2305 - #define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 2306 - #define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) 2307 - #define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2308 - #define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15 2309 - #define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 2310 - #define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT) 2311 - #define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2312 - #define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15 2313 - #define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 2314 - #define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT) 2315 - #define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2316 - #define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15 2317 - #define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 2318 - #define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT) 2319 - #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2320 - #define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15 2321 - #define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 2322 - #define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT) 2323 - #define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2324 - #define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15 2325 - #define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0 2326 - #define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT) 2327 - #define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2328 - #define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15 2329 - #define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0 2330 - #define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT) 2331 - #define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2332 - #define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15 2333 - #define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0 2334 - #define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT) 2335 - #define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2336 - #define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15 2337 - #define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0 2338 - #define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT) 2339 - #define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2340 - #define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15 2341 - #define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 2342 - #define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT) 2343 - #define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 2344 - #define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15 2345 - #define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 2346 - #define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) 2347 - #define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2348 - #define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15 2349 - #define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 2350 - #define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) 2351 - #define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2352 - #define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15 2353 - #define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 2354 - #define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) 2355 - #define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2356 - #define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15 2357 - #define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 2358 - #define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT) 2359 - #define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2360 - #define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15 2361 - #define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 2362 - #define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT) 2363 - #define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2364 - #define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15 2365 - #define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 2366 - #define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) 2367 - #define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2368 - #define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15 2369 - #define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 2370 - #define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) 2371 - #define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2372 - #define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15 2373 - #define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 2374 - #define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) 2375 - #define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 2376 - #define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15 2377 - #define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 2378 - #define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) 2379 - #define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */ 2380 - #define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0 2381 - #define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT) 2382 - #define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */ 2383 - #define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0 2384 - #define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT) 2385 - #define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */ 2386 - #define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0 2387 - #define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT) 2388 - #define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */ 2389 - #define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0 2390 - #define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT) 2391 - #define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */ 2392 - #define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0 2393 - #define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT) 2394 - #define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */ 2395 - #define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0 2396 - #define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT) 2397 - #define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */ 2398 - #define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0 2399 - #define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT) 2400 - #define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */ 2401 - #define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0 2402 - #define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT) 2403 - #define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */ 2404 - #define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0 2405 - #define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT) 2406 - #define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */ 2407 - #define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0 2408 - #define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT) 2409 - #define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */ 2410 - #define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0 2411 - #define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT) 2412 - #define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */ 2413 - #define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0 2414 - #define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT) 2415 - #define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */ 2416 - #define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0 2417 - #define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT) 2418 - #define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */ 2419 - #define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0 2420 - #define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT) 2421 - #define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */ 2422 - #define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0 2423 - #define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT) 2424 - #define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */ 2425 - #define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0 2426 - #define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT) 2427 - #define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */ 2428 - #define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0 2429 - #define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT) 2430 - #define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */ 2431 - #define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0 2432 - #define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT) 2433 - #define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */ 2434 - #define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0 2435 - #define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT) 2436 - #define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */ 2437 - #define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0 2438 - #define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT) 2439 - #define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */ 2440 - #define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0 2441 - #define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT) 2442 - #define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */ 2443 - #define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0 2444 - #define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT) 2445 - #define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2446 - #define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31 2447 - #define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 2448 - #define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT) 2449 - #define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2450 - #define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31 2451 - #define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 2452 - #define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) 2453 - #define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2454 - #define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31 2455 - #define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 2456 - #define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) 2457 - #define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2458 - #define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31 2459 - #define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 2460 - #define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) 2461 - #define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2462 - #define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31 2463 - #define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 2464 - #define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) 2465 - #define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2466 - #define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31 2467 - #define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 2468 - #define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) 2469 - #define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2470 - #define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31 2471 - #define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 2472 - #define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) 2473 - #define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2474 - #define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31 2475 - #define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 2476 - #define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) 2477 - #define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2478 - #define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31 2479 - #define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 2480 - #define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) 2481 - #define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2482 - #define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31 2483 - #define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 2484 - #define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) 2485 - #define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2486 - #define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31 2487 - #define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 2488 - #define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) 2489 - #define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2490 - #define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31 2491 - #define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 2492 - #define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT) 2493 - #define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2494 - #define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31 2495 - #define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 2496 - #define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) 2497 - #define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2498 - #define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31 2499 - #define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 2500 - #define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) 2501 - #define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2502 - #define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31 2503 - #define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 2504 - #define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) 2505 - #define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2506 - #define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31 2507 - #define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 2508 - #define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) 2509 - #define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2510 - #define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31 2511 - #define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 2512 - #define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) 2513 - #define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2514 - #define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31 2515 - #define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 2516 - #define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) 2517 - #define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2518 - #define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31 2519 - #define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 2520 - #define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) 2521 - #define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2522 - #define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31 2523 - #define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 2524 - #define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) 2525 - #define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2526 - #define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31 2527 - #define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 2528 - #define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) 2529 - #define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2530 - #define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31 2531 - #define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 2532 - #define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) 2533 - #define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2534 - #define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31 2535 - #define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 2536 - #define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) 2537 - #define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2538 - #define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31 2539 - #define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 2540 - #define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT) 2541 - #define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2542 - #define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31 2543 - #define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 2544 - #define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) 2545 - #define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2546 - #define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31 2547 - #define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 2548 - #define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) 2549 - #define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2550 - #define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31 2551 - #define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 2552 - #define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) 2553 - #define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2554 - #define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31 2555 - #define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 2556 - #define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) 2557 - #define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2558 - #define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31 2559 - #define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 2560 - #define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) 2561 - #define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2562 - #define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31 2563 - #define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 2564 - #define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) 2565 - #define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2566 - #define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31 2567 - #define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 2568 - #define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) 2569 - #define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2570 - #define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31 2571 - #define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 2572 - #define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) 2573 - #define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2574 - #define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31 2575 - #define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 2576 - #define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) 2577 - #define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2578 - #define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31 2579 - #define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 2580 - #define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) 2581 - #define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2582 - #define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31 2583 - #define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 2584 - #define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT) 2585 - #define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2586 - #define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31 2587 - #define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 2588 - #define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) 2589 - #define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2590 - #define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31 2591 - #define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 2592 - #define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) 2593 - #define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2594 - #define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31 2595 - #define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 2596 - #define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) 2597 - #define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2598 - #define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31 2599 - #define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 2600 - #define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) 2601 - #define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2602 - #define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31 2603 - #define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 2604 - #define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) 2605 - #define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2606 - #define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31 2607 - #define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 2608 - #define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) 2609 - #define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2610 - #define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31 2611 - #define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 2612 - #define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) 2613 - #define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2614 - #define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31 2615 - #define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 2616 - #define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) 2617 - #define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2618 - #define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31 2619 - #define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 2620 - #define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) 2621 - #define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2622 - #define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31 2623 - #define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 2624 - #define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) 2625 - #define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2626 - #define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31 2627 - #define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 2628 - #define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) 2629 - #define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2630 - #define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31 2631 - #define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 2632 - #define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT) 2633 - #define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2634 - #define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31 2635 - #define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 2636 - #define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT) 2637 - #define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2638 - #define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31 2639 - #define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 2640 - #define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) 2641 - #define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2642 - #define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31 2643 - #define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 2644 - #define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) 2645 - #define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2646 - #define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31 2647 - #define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 2648 - #define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT) 2649 - #define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2650 - #define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31 2651 - #define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 2652 - #define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT) 2653 - #define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2654 - #define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31 2655 - #define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 2656 - #define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT) 2657 - #define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2658 - #define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31 2659 - #define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 2660 - #define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT) 2661 - #define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2662 - #define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31 2663 - #define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 2664 - #define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) 2665 - #define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2666 - #define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31 2667 - #define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 2668 - #define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) 2669 - #define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2670 - #define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31 2671 - #define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 2672 - #define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT) 2673 - #define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2674 - #define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31 2675 - #define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 2676 - #define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT) 2677 - #define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2678 - #define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31 2679 - #define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 2680 - #define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT) 2681 - #define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2682 - #define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31 2683 - #define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 2684 - #define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT) 2685 - #define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2686 - #define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31 2687 - #define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0 2688 - #define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT) 2689 - #define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2690 - #define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31 2691 - #define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0 2692 - #define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT) 2693 - #define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2694 - #define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31 2695 - #define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0 2696 - #define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT) 2697 - #define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2698 - #define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31 2699 - #define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0 2700 - #define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT) 2701 - #define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2702 - #define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31 2703 - #define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 2704 - #define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT) 2705 - #define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 2706 - #define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31 2707 - #define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 2708 - #define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) 2709 - #define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2710 - #define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31 2711 - #define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 2712 - #define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) 2713 - #define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2714 - #define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31 2715 - #define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 2716 - #define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) 2717 - #define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2718 - #define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31 2719 - #define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 2720 - #define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT) 2721 - #define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2722 - #define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31 2723 - #define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 2724 - #define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT) 2725 - #define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2726 - #define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31 2727 - #define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 2728 - #define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) 2729 - #define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2730 - #define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31 2731 - #define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 2732 - #define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) 2733 - #define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2734 - #define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31 2735 - #define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 2736 - #define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) 2737 - #define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 2738 - #define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31 2739 - #define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 2740 - #define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) 2741 - #define I40E_GLGEN_PME_TO 0x000B81BC /* Reset: POR */ 2742 - #define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT 0 2743 - #define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK I40E_MASK(0x1, I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT) 2744 - #define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset: CORER */ 2745 - #define I40E_GLQF_APBVT_MAX_INDEX 2047 2746 - #define I40E_GLQF_APBVT_APBVT_SHIFT 0 2747 - #define I40E_GLQF_APBVT_APBVT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_APBVT_APBVT_SHIFT) 2748 - #define I40E_GLQF_FD_PCTYPES(_i) (0x00268000 + ((_i) * 4)) /* _i=0...63 */ /* Reset: POR */ 2749 - #define I40E_GLQF_FD_PCTYPES_MAX_INDEX 63 2750 - #define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0 2751 - #define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT) 2752 - #define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 2753 - #define I40E_GLQF_FD_MSK_MAX_INDEX 1 2754 - #define I40E_GLQF_FD_MSK_MASK_SHIFT 0 2755 - #define I40E_GLQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT) 2756 - #define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16 2757 - #define I40E_GLQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT) 2758 3074 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 2759 - #define I40E_GLQF_HASH_INSET_MAX_INDEX 1 2760 - #define I40E_GLQF_HASH_INSET_INSET_SHIFT 0 2761 - #define I40E_GLQF_HASH_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT) 2762 - #define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 2763 - #define I40E_GLQF_HASH_MSK_MAX_INDEX 1 2764 - #define I40E_GLQF_HASH_MSK_MASK_SHIFT 0 2765 - #define I40E_GLQF_HASH_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT) 2766 - #define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16 2767 - #define I40E_GLQF_HASH_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT) 2768 3075 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 2769 - #define I40E_GLQF_ORT_MAX_INDEX 63 2770 3076 #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0 2771 3077 #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT) 2772 3078 #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5 2773 3079 #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT) 2774 3080 #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7 2775 3081 #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) 2776 - #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) /* _i=0...23 */ /* Reset: CORER */ 2777 - #define I40E_GLQF_PIT_MAX_INDEX 23 2778 - #define I40E_GLQF_PIT_SOURCE_OFF_SHIFT 0 2779 - #define I40E_GLQF_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_SOURCE_OFF_SHIFT) 2780 - #define I40E_GLQF_PIT_FSIZE_SHIFT 5 2781 - #define I40E_GLQF_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_FSIZE_SHIFT) 2782 - #define I40E_GLQF_PIT_DEST_OFF_SHIFT 10 2783 - #define I40E_GLQF_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_GLQF_PIT_DEST_OFF_SHIFT) 2784 3082 #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 2785 - #define I40E_GLQF_FDEVICTENA_MAX_INDEX 1 2786 - #define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0 2787 - #define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT) 2788 - #define I40E_GLQF_FDEVICTFLAG 0x00270280 /* Reset: CORER */ 2789 - #define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT 0 2790 - #define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT) 2791 - #define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT 8 2792 - #define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT) 2793 - #define I40E_PFQF_CTL_2 0x00270300 /* Reset: CORER */ 2794 - #define I40E_PFQF_CTL_2_PEHSIZE_SHIFT 0 2795 - #define I40E_PFQF_CTL_2_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEHSIZE_SHIFT) 2796 - #define I40E_PFQF_CTL_2_PEDSIZE_SHIFT 5 2797 - #define I40E_PFQF_CTL_2_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEDSIZE_SHIFT) 2798 3083 /* Redefined for X722 family */ 2799 - #define I40E_X722_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 2800 - #define I40E_X722_PFQF_HLUT_MAX_INDEX 127 2801 - #define I40E_X722_PFQF_HLUT_LUT0_SHIFT 0 2802 - #define I40E_X722_PFQF_HLUT_LUT0_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT0_SHIFT) 2803 - #define I40E_X722_PFQF_HLUT_LUT1_SHIFT 8 2804 - #define I40E_X722_PFQF_HLUT_LUT1_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT1_SHIFT) 2805 - #define I40E_X722_PFQF_HLUT_LUT2_SHIFT 16 2806 - #define I40E_X722_PFQF_HLUT_LUT2_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT2_SHIFT) 2807 - #define I40E_X722_PFQF_HLUT_LUT3_SHIFT 24 2808 - #define I40E_X722_PFQF_HLUT_LUT3_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT3_SHIFT) 2809 - #define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ /* Reset: CORER */ 2810 - #define I40E_PFQF_HREGION_MAX_INDEX 7 2811 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 2812 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT) 2813 - #define I40E_PFQF_HREGION_REGION_0_SHIFT 1 2814 - #define I40E_PFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT) 2815 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 2816 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT) 2817 - #define I40E_PFQF_HREGION_REGION_1_SHIFT 5 2818 - #define I40E_PFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT) 2819 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 2820 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT) 2821 - #define I40E_PFQF_HREGION_REGION_2_SHIFT 9 2822 - #define I40E_PFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT) 2823 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 2824 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT) 2825 - #define I40E_PFQF_HREGION_REGION_3_SHIFT 13 2826 - #define I40E_PFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT) 2827 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 2828 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT) 2829 - #define I40E_PFQF_HREGION_REGION_4_SHIFT 17 2830 - #define I40E_PFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT) 2831 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 2832 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT) 2833 - #define I40E_PFQF_HREGION_REGION_5_SHIFT 21 2834 - #define I40E_PFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT) 2835 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 2836 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 2837 - #define I40E_PFQF_HREGION_REGION_6_SHIFT 25 2838 - #define I40E_PFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT) 2839 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 2840 - #define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 2841 - #define I40E_PFQF_HREGION_REGION_7_SHIFT 29 2842 - #define I40E_PFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT) 2843 - #define I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT 8 2844 - #define I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT) 2845 - #define I40E_VSIQF_HKEY(_i, _VSI) (0x002A0000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...12, _VSI=0...383 */ /* Reset: CORER */ 2846 - #define I40E_VSIQF_HKEY_MAX_INDEX 12 2847 - #define I40E_VSIQF_HKEY_KEY_0_SHIFT 0 2848 - #define I40E_VSIQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_0_SHIFT) 2849 - #define I40E_VSIQF_HKEY_KEY_1_SHIFT 8 2850 - #define I40E_VSIQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_1_SHIFT) 2851 - #define I40E_VSIQF_HKEY_KEY_2_SHIFT 16 2852 - #define I40E_VSIQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_2_SHIFT) 2853 - #define I40E_VSIQF_HKEY_KEY_3_SHIFT 24 2854 - #define I40E_VSIQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_3_SHIFT) 2855 - #define I40E_VSIQF_HLUT(_i, _VSI) (0x00220000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...15, _VSI=0...383 */ /* Reset: CORER */ 2856 - #define I40E_VSIQF_HLUT_MAX_INDEX 15 2857 - #define I40E_VSIQF_HLUT_LUT0_SHIFT 0 2858 - #define I40E_VSIQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT0_SHIFT) 2859 - #define I40E_VSIQF_HLUT_LUT1_SHIFT 8 2860 - #define I40E_VSIQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT1_SHIFT) 2861 - #define I40E_VSIQF_HLUT_LUT2_SHIFT 16 2862 - #define I40E_VSIQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT2_SHIFT) 2863 - #define I40E_VSIQF_HLUT_LUT3_SHIFT 24 2864 - #define I40E_VSIQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT3_SHIFT) 2865 3084 #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 2866 - #define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT 0 2867 - #define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT) 2868 - #define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */ 2869 - #define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0 2870 - #define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT) 2871 - #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 2872 - #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) 2873 - #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 2874 - #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) 2875 - #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ 2876 - #define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 2877 - #define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) 2878 - #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ 2879 - #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 2880 - #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) 2881 - #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ 2882 - #define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 2883 - #define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) 2884 - #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ 2885 - #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 2886 - #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) 2887 - #define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 2888 - #define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) 2889 - #define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 2890 - #define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) 2891 - #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 2892 - #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) 2893 - #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ 2894 - #define I40E_VFPE_CQACK1_PECQID_SHIFT 0 2895 - #define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT) 2896 - #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ 2897 - #define I40E_VFPE_CQARM1_PECQID_SHIFT 0 2898 - #define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT) 2899 - #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ 2900 - #define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 2901 - #define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT) 2902 - #define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ 2903 - #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 2904 - #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) 2905 - #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 2906 - #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) 2907 - #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ 2908 - #define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 2909 - #define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) 2910 - #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 2911 - #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) 2912 - #define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ 2913 - #define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 2914 - #define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) 2915 - #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 2916 - #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) 2917 - #define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ 2918 - #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 2919 - #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) 2920 - #define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ 2921 - #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 2922 - #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) 2923 - #define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ 2924 - #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 2925 - #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) 2926 - #define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ 2927 - #define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 2928 - #define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) 2929 - #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 2930 - #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) 2931 3085 #endif /* _I40E_REGISTER_H_ */
-25
drivers/net/ethernet/intel/i40e/i40e_txrx.h
··· 18 18 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 19 19 #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */ 20 20 #define I40E_MIN_ITR 2 /* reg uses 2 usec resolution */ 21 - #define I40E_ITR_100K 10 /* all values below must be even */ 22 - #define I40E_ITR_50K 20 23 21 #define I40E_ITR_20K 50 24 - #define I40E_ITR_18K 60 25 22 #define I40E_ITR_8K 122 26 23 #define I40E_MAX_ITR 8160 /* maximum value as per datasheet */ 27 24 #define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC) ··· 49 52 else 50 53 return 0; 51 54 } 52 - #define I40E_INTRL_8K 125 /* 8000 ints/sec */ 53 - #define I40E_INTRL_62K 16 /* 62500 ints/sec */ 54 - #define I40E_INTRL_83K 12 /* 83333 ints/sec */ 55 55 56 56 #define I40E_QUEUE_END_OF_LIST 0x7FF 57 57 ··· 67 73 /* these are indexes into ITRN registers */ 68 74 #define I40E_RX_ITR I40E_IDX_ITR0 69 75 #define I40E_TX_ITR I40E_IDX_ITR1 70 - #define I40E_PE_ITR I40E_IDX_ITR2 71 76 72 77 /* Supported RSS offloads */ 73 78 #define I40E_DEFAULT_RSS_HENA ( \ ··· 186 193 187 194 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 188 195 #define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */ 189 - #define I40E_RX_INCREMENT(r, i) \ 190 - do { \ 191 - (i)++; \ 192 - if ((i) == (r)->count) \ 193 - i = 0; \ 194 - r->next_to_clean = i; \ 195 - } while (0) 196 196 197 197 #define I40E_RX_NEXT_DESC(r, i, n) \ 198 198 do { \ ··· 195 209 (n) = I40E_RX_DESC((r), (i)); \ 196 210 } while (0) 197 211 198 - #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 199 - do { \ 200 - I40E_RX_NEXT_DESC((r), (i), (n)); \ 201 - prefetch((n)); \ 202 - } while (0) 203 212 204 213 #define I40E_MAX_BUFFER_TXD 8 205 214 #define I40E_MIN_TX_LEN 17 ··· 243 262 244 263 /* Tx Descriptors needed, worst case */ 245 264 #define DESC_NEEDED (MAX_SKB_FRAGS + 6) 246 - #define I40E_MIN_DESC_PENDING 4 247 265 248 266 #define I40E_TX_FLAGS_HW_VLAN BIT(1) 249 267 #define I40E_TX_FLAGS_SW_VLAN BIT(2) 250 268 #define I40E_TX_FLAGS_TSO BIT(3) 251 269 #define I40E_TX_FLAGS_IPV4 BIT(4) 252 270 #define I40E_TX_FLAGS_IPV6 BIT(5) 253 - #define I40E_TX_FLAGS_FCCRC BIT(6) 254 - #define I40E_TX_FLAGS_FSO BIT(7) 255 271 #define I40E_TX_FLAGS_TSYN BIT(8) 256 272 #define I40E_TX_FLAGS_FD_SB BIT(9) 257 273 #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) ··· 310 332 /* some useful defines for virtchannel interface, which 311 333 * is the only remaining user of header split 312 334 */ 313 - #define I40E_RX_DTYPE_NO_SPLIT 0 314 335 #define I40E_RX_DTYPE_HEADER_SPLIT 1 315 - #define I40E_RX_DTYPE_SPLIT_ALWAYS 2 316 336 #define I40E_RX_SPLIT_L2 0x1 317 337 #define I40E_RX_SPLIT_IP 0x2 318 338 #define I40E_RX_SPLIT_TCP_UDP 0x4 ··· 420 444 #define I40E_ITR_ADAPTIVE_MAX_USECS 0x007e 421 445 #define I40E_ITR_ADAPTIVE_LATENCY 0x8000 422 446 #define I40E_ITR_ADAPTIVE_BULK 0x0000 423 - #define ITR_IS_BULK(x) (!((x) & I40E_ITR_ADAPTIVE_LATENCY)) 424 447 425 448 struct i40e_ring_container { 426 449 struct i40e_ring *ring; /* pointer to linked list of ring(s) */
-82
drivers/net/ethernet/intel/i40e/i40e_type.h
··· 84 84 I40E_GLGEN_MSCA_OPCODE_SHIFT) 85 85 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \ 86 86 I40E_GLGEN_MSCA_OPCODE_SHIFT) 87 - #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \ 88 - I40E_GLGEN_MSCA_OPCODE_SHIFT) 89 87 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \ 90 88 I40E_GLGEN_MSCA_OPCODE_SHIFT) 91 89 ··· 176 178 u8 module_type[3]; 177 179 /* 1st byte: module identifier */ 178 180 #define I40E_MODULE_TYPE_SFP 0x03 179 - #define I40E_MODULE_TYPE_QSFP 0x0D 180 - /* 2nd byte: ethernet compliance codes for 10/40G */ 181 - #define I40E_MODULE_TYPE_40G_ACTIVE 0x01 182 - #define I40E_MODULE_TYPE_40G_LR4 0x02 183 - #define I40E_MODULE_TYPE_40G_SR4 0x04 184 - #define I40E_MODULE_TYPE_40G_CR4 0x08 185 - #define I40E_MODULE_TYPE_10G_BASE_SR 0x10 186 - #define I40E_MODULE_TYPE_10G_BASE_LR 0x20 187 - #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 188 - #define I40E_MODULE_TYPE_10G_BASE_ER 0x80 189 181 /* 3rd byte: ethernet compliance codes for 1G */ 190 182 #define I40E_MODULE_TYPE_1000BASE_SX 0x01 191 183 #define I40E_MODULE_TYPE_1000BASE_LX 0x02 192 - #define I40E_MODULE_TYPE_1000BASE_CX 0x04 193 - #define I40E_MODULE_TYPE_1000BASE_T 0x08 194 184 }; 195 185 196 186 struct i40e_phy_info { ··· 248 262 /* Capabilities of a PF or a VF or the whole device */ 249 263 struct i40e_hw_capabilities { 250 264 u32 switch_mode; 251 - #define I40E_NVM_IMAGE_TYPE_EVB 0x0 252 - #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 253 - #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 254 265 255 266 /* Cloud filter modes: 256 267 * Mode1: Filter on L4 port only ··· 256 273 */ 257 274 #define I40E_CLOUD_FILTER_MODE1 0x6 258 275 #define I40E_CLOUD_FILTER_MODE2 0x7 259 - #define I40E_CLOUD_FILTER_MODE3 0x8 260 276 #define I40E_SWITCH_MODE_MASK 0xF 261 277 262 278 u32 management_mode; 263 279 u32 mng_protocols_over_mctp; 264 - #define I40E_MNG_PROTOCOL_PLDM 0x2 265 - #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 266 - #define I40E_MNG_PROTOCOL_NCSI 0x8 267 280 u32 npar_enable; 268 281 u32 os2bmc; 269 282 u32 valid_functions; ··· 273 294 bool flex10_enable; 274 295 bool flex10_capable; 275 296 u32 flex10_mode; 276 - #define I40E_FLEX10_MODE_UNKNOWN 0x0 277 - #define I40E_FLEX10_MODE_DCC 0x1 278 - #define I40E_FLEX10_MODE_DCI 0x2 279 297 280 298 u32 flex10_status; 281 - #define I40E_FLEX10_STATUS_DCC_ERROR 0x1 282 - #define I40E_FLEX10_STATUS_VC_MODE 0x2 283 299 284 300 bool sec_rev_disabled; 285 301 bool update_disabled; ··· 395 421 #define I40E_NVM_AQE 0xe 396 422 #define I40E_NVM_EXEC 0xf 397 423 398 - #define I40E_NVM_ADAPT_SHIFT 16 399 - #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT) 400 424 401 425 #define I40E_NVMUPD_MAX_DATA 4096 402 - #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 403 426 404 427 struct i40e_nvm_access { 405 428 u32 command; ··· 409 438 /* (Q)SFP module access definitions */ 410 439 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0 411 440 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 412 - #define I40E_MODULE_TYPE_ADDR 0x00 413 441 #define I40E_MODULE_REVISION_ADDR 0x01 414 442 #define I40E_MODULE_SFF_8472_COMP 0x5E 415 443 #define I40E_MODULE_SFF_8472_SWAP 0x5C ··· 517 547 #define I40E_DCBX_MODE_CEE 0x1 518 548 #define I40E_DCBX_MODE_IEEE 0x2 519 549 u8 app_mode; 520 - #define I40E_DCBX_APPS_NON_WILLING 0x1 521 550 u32 numapps; 522 551 u32 tlv_status; /* CEE mode TLV status */ 523 552 struct i40e_dcb_ets_config etscfg; ··· 864 895 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 865 896 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 866 897 867 - #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 868 - #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 869 - I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 870 898 871 899 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 872 900 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) ··· 892 926 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 893 927 }; 894 928 895 - #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 896 929 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 897 930 898 931 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 ··· 928 963 __le64 cmd_type_offset_bsz; 929 964 }; 930 965 931 - #define I40E_TXD_QW1_DTYPE_SHIFT 0 932 - #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 933 966 934 967 enum i40e_tx_desc_dtype_value { 935 968 I40E_TX_DESC_DTYPE_DATA = 0x0, ··· 943 980 }; 944 981 945 982 #define I40E_TXD_QW1_CMD_SHIFT 4 946 - #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 947 983 948 984 enum i40e_tx_desc_cmd_bits { 949 985 I40E_TX_DESC_CMD_EOP = 0x0001, ··· 966 1004 }; 967 1005 968 1006 #define I40E_TXD_QW1_OFFSET_SHIFT 16 969 - #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 970 - I40E_TXD_QW1_OFFSET_SHIFT) 971 1007 972 1008 enum i40e_tx_desc_length_fields { 973 1009 /* Note: These are predefined bit offsets */ ··· 975 1015 }; 976 1016 977 1017 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 978 - #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 979 - I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 980 1018 981 1019 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 982 - #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 983 1020 984 1021 /* Context descriptors */ 985 1022 struct i40e_tx_context_desc { ··· 986 1029 __le64 type_cmd_tso_mss; 987 1030 }; 988 1031 989 - #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 990 - #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 991 1032 992 1033 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 993 - #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 994 1034 995 1035 enum i40e_tx_ctx_desc_cmd_bits { 996 1036 I40E_TX_CTX_DESC_TSO = 0x01, ··· 1002 1048 }; 1003 1049 1004 1050 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1005 - #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1006 - I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1007 1051 1008 1052 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1009 - #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1010 - I40E_TXD_CTX_QW1_MSS_SHIFT) 1011 1053 1012 - #define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1013 - #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1014 1054 1015 - #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1016 - #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1017 - I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1018 1055 1019 1056 enum i40e_tx_ctx_desc_eipt_offload { 1020 1057 I40E_TX_CTX_EXT_IP_NONE = 0x0, ··· 1015 1070 }; 1016 1071 1017 1072 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1018 - #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1019 - I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1020 1073 1021 1074 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1022 - #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1023 1075 1024 1076 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 1025 1077 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1026 1078 1027 - #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1028 - #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \ 1029 - BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1030 1079 1031 - #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1032 1080 1033 1081 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1034 - #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1035 - I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1036 1082 1037 - #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1038 - #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1039 - I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1040 1083 1041 1084 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 1042 1085 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) ··· 1094 1161 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1095 1162 1096 1163 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1097 - #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1098 - I40E_TXD_FLTR_QW1_CMD_SHIFT) 1099 1164 1100 1165 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1101 - #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1102 1166 1103 1167 enum i40e_filter_program_desc_pcmd { 1104 1168 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, ··· 1246 1316 #define I40E_NVM_OEM_VER_OFF 0x83 1247 1317 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1248 1318 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1249 - #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1250 1319 #define I40E_SR_NVM_EETRACK_LO 0x2D 1251 1320 #define I40E_SR_NVM_EETRACK_HI 0x2E 1252 1321 #define I40E_SR_VPD_PTR 0x2F ··· 1258 1329 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1259 1330 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1260 1331 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1261 - #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) 1262 1332 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) 1263 1333 #define I40E_PTR_TYPE BIT(15) 1264 1334 #define I40E_SR_OCP_CFG_WORD0 0x2B ··· 1391 1463 /* Offsets into Alternate Ram */ 1392 1464 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1393 1465 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1394 - #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1395 - #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1396 1466 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1397 1467 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1398 1468 1399 1469 /* Alternate Ram Bandwidth Masks */ 1400 1470 #define I40E_ALT_BW_VALUE_MASK 0xFF 1401 - #define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1402 1471 #define I40E_ALT_BW_VALID_MASK 0x80000000 1403 1472 1404 1473 /* RSS Hash Table Size */ ··· 1454 1529 /* Generic segment header */ 1455 1530 struct i40e_generic_seg_header { 1456 1531 #define SEGMENT_TYPE_METADATA 0x00000001 1457 - #define SEGMENT_TYPE_NOTES 0x00000002 1458 1532 #define SEGMENT_TYPE_I40E 0x00000011 1459 - #define SEGMENT_TYPE_X722 0x00000012 1460 1533 u32 type; 1461 1534 struct i40e_ddp_version version; 1462 1535 u32 size; ··· 1464 1541 struct i40e_metadata_segment { 1465 1542 struct i40e_generic_seg_header header; 1466 1543 struct i40e_ddp_version version; 1467 - #define I40E_DDP_TRACKID_RDONLY 0 1468 1544 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF 1469 1545 u32 track_id; 1470 1546 char name[I40E_DDP_NAME_SIZE]; ··· 1497 1575 #define SECTION_TYPE_AQ 0x00000801 1498 1576 #define SECTION_TYPE_RB_AQ 0x00001801 1499 1577 #define SECTION_TYPE_NOTE 0x80000000 1500 - #define SECTION_TYPE_NAME 0x80000001 1501 - #define SECTION_TYPE_PROTO 0x80000002 1502 - #define SECTION_TYPE_PCTYPE 0x80000003 1503 - #define SECTION_TYPE_PTYPE 0x80000004 1504 1578 u32 type; 1505 1579 u32 offset; 1506 1580 u32 size;
-1
drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h
··· 10 10 11 11 #define I40E_VIRTCHNL_SUPPORTED_QTYPES 2 12 12 13 - #define I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED 3 14 13 #define I40E_DEFAULT_NUM_INVALID_MSGS_ALLOWED 10 15 14 16 15 #define I40E_VLAN_PRIORITY_SHIFT 13
-9
include/linux/net/intel/i40e_client.h
··· 37 37 struct i40e_ops; 38 38 struct i40e_client; 39 39 40 - /* HW does not define a type value for AEQ; only for RX/TX and CEQ. 41 - * In order for us to keep the interface simple, SW will define a 42 - * unique type value for AEQ. 43 - */ 44 - #define I40E_QUEUE_TYPE_PE_AEQ 0x80 45 40 #define I40E_QUEUE_INVALID_IDX 0xFFFF 46 41 47 42 struct i40e_qv_info { ··· 51 56 struct i40e_qv_info qv_info[1]; 52 57 }; 53 58 54 - #define I40E_CLIENT_MSIX_ALL 0xFFFFFFFF 55 59 56 60 /* set of LAN parameters useful for clients managed by LAN */ 57 61 ··· 81 87 u8 __iomem *hw_addr; 82 88 u8 fid; /* function id, PF id or VF id */ 83 89 #define I40E_CLIENT_FTYPE_PF 0 84 - #define I40E_CLIENT_FTYPE_VF 1 85 90 u8 ftype; /* function type, PF or VF */ 86 91 void *pf; 87 92 ··· 177 184 unsigned long state; /* client state */ 178 185 atomic_t ref_cnt; /* Count of all the client devices of this kind */ 179 186 u32 flags; 180 - #define I40E_CLIENT_FLAGS_LAUNCH_ON_PROBE BIT(0) 181 - #define I40E_TX_FLAGS_NOTIFY_OTHER_EVENTS BIT(2) 182 187 u8 type; 183 188 #define I40E_CLIENT_IWARP 0 184 189 const struct i40e_client_ops *ops; /* client ops provided by the client */