tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

gpio: use raw spinlock for gpio chip shadowed data

In case of PREEMPT_RT, there is a raw_spinlock -> spinlock dependency
as the lockdep report shows.

__irq_set_handler
irq_get_desc_buslock
__irq_get_desc_lock
raw_spin_lock_irqsave(&desc->lock, *flags); // raw spinlock get here
__irq_do_set_handler
mask_ack_irq
dwapb_irq_ack
spin_lock_irqsave(&gc->bgpio_lock, flags); // sleep able spinlock
irq_put_desc_busunlock

Replace with a raw lock to avoid BUGs. This lock is only used to access
registers, and It's safe to replace with the raw lock without bad
influence.

[ 15.090359][ T1] =============================
[ 15.090365][ T1] [ BUG: Invalid wait context ]
[ 15.090373][ T1] 5.10.59-rt52-00983-g186a6841c682-dirty #3 Not tainted
[ 15.090386][ T1] -----------------------------
[ 15.090392][ T1] swapper/0/1 is trying to lock:
[ 15.090402][ T1] 70ff00018507c188 (&gc->bgpio_lock){....}-{3:3}, at: _raw_spin_lock_irqsave+0x1c/0x28
[ 15.090470][ T1] other info that might help us debug this:
[ 15.090477][ T1] context-{5:5}
[ 15.090485][ T1] 3 locks held by swapper/0/1:
[ 15.090497][ T1] #0: c2ff0001816de1a0 (&dev->mutex){....}-{4:4}, at: __device_driver_lock+0x98/0x104
[ 15.090553][ T1] #1: ffff90001485b4b8 (irq_domain_mutex){+.+.}-{4:4}, at: irq_domain_associate+0xbc/0x6d4
[ 15.090606][ T1] #2: 4bff000185d7a8e0 (lock_class){....}-{2:2}, at: _raw_spin_lock_irqsave+0x1c/0x28
[ 15.090654][ T1] stack backtrace:
[ 15.090661][ T1] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.59-rt52-00983-g186a6841c682-dirty #3
[ 15.090682][ T1] Hardware name: Horizon Robotics Journey 5 DVB (DT)
[ 15.090692][ T1] Call trace:
......
[ 15.090811][ T1] _raw_spin_lock_irqsave+0x1c/0x28
[ 15.090828][ T1] dwapb_irq_ack+0xb4/0x300
[ 15.090846][ T1] __irq_do_set_handler+0x494/0xb2c
[ 15.090864][ T1] __irq_set_handler+0x74/0x114
[ 15.090881][ T1] irq_set_chip_and_handler_name+0x44/0x58
[ 15.090900][ T1] gpiochip_irq_map+0x210/0x644

Signed-off-by: Schspa Shi <schspa@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Doug Berger <opendmb@gmail.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>

authored by

Schspa Shi and committed by
Bartosz Golaszewski 3c938cc5 4f3e79b3

+108 -108
+5 -5
drivers/gpio/gpio-amdpt.c
··· 36 36 37 37 dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset); 38 38 39 - spin_lock_irqsave(&gc->bgpio_lock, flags); 39 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 40 40 41 41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 42 42 if (using_pins & BIT(offset)) { 43 43 dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n", 44 44 offset); 45 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 45 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 46 46 return -EINVAL; 47 47 } 48 48 49 49 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); 50 50 51 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 51 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 52 52 53 53 return 0; 54 54 } ··· 59 59 unsigned long flags; 60 60 u32 using_pins; 61 61 62 - spin_lock_irqsave(&gc->bgpio_lock, flags); 62 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 63 63 64 64 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 65 65 using_pins &= ~BIT(offset); 66 66 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); 67 67 68 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 68 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 69 69 70 70 dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset); 71 71 }
+6 -6
drivers/gpio/gpio-brcmstb.c
··· 92 92 unsigned long status; 93 93 unsigned long flags; 94 94 95 - spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 95 + raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 96 96 status = __brcmstb_gpio_get_active_irqs(bank); 97 - spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 97 + raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 98 98 99 99 return status; 100 100 } ··· 114 114 u32 imask; 115 115 unsigned long flags; 116 116 117 - spin_lock_irqsave(&gc->bgpio_lock, flags); 117 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 118 118 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); 119 119 if (enable) 120 120 imask |= mask; 121 121 else 122 122 imask &= ~mask; 123 123 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); 124 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 124 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 125 125 } 126 126 127 127 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) ··· 204 204 return -EINVAL; 205 205 } 206 206 207 - spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 207 + raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 208 208 209 209 iedge_config = bank->gc.read_reg(priv->reg_base + 210 210 GIO_EC(bank->id)) & ~mask; ··· 220 220 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), 221 221 ilevel | level); 222 222 223 - spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 223 + raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 224 224 return 0; 225 225 } 226 226
+6 -6
drivers/gpio/gpio-cadence.c
··· 41 41 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip); 42 42 unsigned long flags; 43 43 44 - spin_lock_irqsave(&chip->bgpio_lock, flags); 44 + raw_spin_lock_irqsave(&chip->bgpio_lock, flags); 45 45 46 46 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset), 47 47 cgpio->regs + CDNS_GPIO_BYPASS_MODE); 48 48 49 - spin_unlock_irqrestore(&chip->bgpio_lock, flags); 49 + raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags); 50 50 return 0; 51 51 } 52 52 ··· 55 55 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip); 56 56 unsigned long flags; 57 57 58 - spin_lock_irqsave(&chip->bgpio_lock, flags); 58 + raw_spin_lock_irqsave(&chip->bgpio_lock, flags); 59 59 60 60 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) | 61 61 (BIT(offset) & cgpio->bypass_orig), 62 62 cgpio->regs + CDNS_GPIO_BYPASS_MODE); 63 63 64 - spin_unlock_irqrestore(&chip->bgpio_lock, flags); 64 + raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags); 65 65 } 66 66 67 67 static void cdns_gpio_irq_mask(struct irq_data *d) ··· 90 90 u32 mask = BIT(d->hwirq); 91 91 int ret = 0; 92 92 93 - spin_lock_irqsave(&chip->bgpio_lock, flags); 93 + raw_spin_lock_irqsave(&chip->bgpio_lock, flags); 94 94 95 95 int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask; 96 96 int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask; ··· 115 115 iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE); 116 116 117 117 err_irq_type: 118 - spin_unlock_irqrestore(&chip->bgpio_lock, flags); 118 + raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags); 119 119 return ret; 120 120 } 121 121
+18 -18
drivers/gpio/gpio-dwapb.c
··· 243 243 u32 val = BIT(irqd_to_hwirq(d)); 244 244 unsigned long flags; 245 245 246 - spin_lock_irqsave(&gc->bgpio_lock, flags); 246 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 247 247 dwapb_write(gpio, GPIO_PORTA_EOI, val); 248 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 248 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 249 249 } 250 250 251 251 static void dwapb_irq_mask(struct irq_data *d) ··· 255 255 unsigned long flags; 256 256 u32 val; 257 257 258 - spin_lock_irqsave(&gc->bgpio_lock, flags); 258 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 259 259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d)); 260 260 dwapb_write(gpio, GPIO_INTMASK, val); 261 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 261 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 262 262 } 263 263 264 264 static void dwapb_irq_unmask(struct irq_data *d) ··· 268 268 unsigned long flags; 269 269 u32 val; 270 270 271 - spin_lock_irqsave(&gc->bgpio_lock, flags); 271 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 272 272 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d)); 273 273 dwapb_write(gpio, GPIO_INTMASK, val); 274 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 274 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 275 275 } 276 276 277 277 static void dwapb_irq_enable(struct irq_data *d) ··· 281 281 unsigned long flags; 282 282 u32 val; 283 283 284 - spin_lock_irqsave(&gc->bgpio_lock, flags); 284 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 285 285 val = dwapb_read(gpio, GPIO_INTEN); 286 286 val |= BIT(irqd_to_hwirq(d)); 287 287 dwapb_write(gpio, GPIO_INTEN, val); 288 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 288 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 289 289 } 290 290 291 291 static void dwapb_irq_disable(struct irq_data *d) ··· 295 295 unsigned long flags; 296 296 u32 val; 297 297 298 - spin_lock_irqsave(&gc->bgpio_lock, flags); 298 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 299 299 val = dwapb_read(gpio, GPIO_INTEN); 300 300 val &= ~BIT(irqd_to_hwirq(d)); 301 301 dwapb_write(gpio, GPIO_INTEN, val); 302 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 302 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 303 303 } 304 304 305 305 static int dwapb_irq_set_type(struct irq_data *d, u32 type) ··· 309 309 irq_hw_number_t bit = irqd_to_hwirq(d); 310 310 unsigned long level, polarity, flags; 311 311 312 - spin_lock_irqsave(&gc->bgpio_lock, flags); 312 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 313 313 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 314 314 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 315 315 ··· 344 344 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 345 345 if (type != IRQ_TYPE_EDGE_BOTH) 346 346 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 347 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 347 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 348 348 349 349 return 0; 350 350 } ··· 374 374 unsigned long flags, val_deb; 375 375 unsigned long mask = BIT(offset); 376 376 377 - spin_lock_irqsave(&gc->bgpio_lock, flags); 377 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 378 378 379 379 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 380 380 if (debounce) ··· 383 383 val_deb &= ~mask; 384 384 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); 385 385 386 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 386 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 387 387 388 388 return 0; 389 389 } ··· 738 738 unsigned long flags; 739 739 int i; 740 740 741 - spin_lock_irqsave(&gc->bgpio_lock, flags); 741 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 742 742 for (i = 0; i < gpio->nr_ports; i++) { 743 743 unsigned int offset; 744 744 unsigned int idx = gpio->ports[i].idx; ··· 765 765 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); 766 766 } 767 767 } 768 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 768 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 769 769 770 770 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 771 771 ··· 785 785 return err; 786 786 } 787 787 788 - spin_lock_irqsave(&gc->bgpio_lock, flags); 788 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 789 789 for (i = 0; i < gpio->nr_ports; i++) { 790 790 unsigned int offset; 791 791 unsigned int idx = gpio->ports[i].idx; ··· 812 812 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 813 813 } 814 814 } 815 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 815 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 816 816 817 817 return 0; 818 818 }
+15 -15
drivers/gpio/gpio-grgpio.c
··· 145 145 return -EINVAL; 146 146 } 147 147 148 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 148 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 149 149 150 150 ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask; 151 151 iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask; ··· 153 153 priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); 154 154 priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); 155 155 156 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 156 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 157 157 158 158 return 0; 159 159 } ··· 164 164 int offset = d->hwirq; 165 165 unsigned long flags; 166 166 167 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 167 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 168 168 169 169 grgpio_set_imask(priv, offset, 0); 170 170 171 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 171 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 172 172 } 173 173 174 174 static void grgpio_irq_unmask(struct irq_data *d) ··· 177 177 int offset = d->hwirq; 178 178 unsigned long flags; 179 179 180 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 180 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 181 181 182 182 grgpio_set_imask(priv, offset, 1); 183 183 184 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 184 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 185 185 } 186 186 187 187 static struct irq_chip grgpio_irq_chip = { ··· 199 199 int i; 200 200 int match = 0; 201 201 202 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 202 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 203 203 204 204 /* 205 205 * For each gpio line, call its interrupt handler if it its underlying ··· 215 215 } 216 216 } 217 217 218 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 218 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 219 219 220 220 if (!match) 221 221 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq); ··· 247 247 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n", 248 248 irq, offset); 249 249 250 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 250 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 251 251 252 252 /* Request underlying irq if not already requested */ 253 253 lirq->irq = irq; 254 254 uirq = &priv->uirqs[lirq->index]; 255 255 if (uirq->refcnt == 0) { 256 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 256 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 257 257 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0, 258 258 dev_name(priv->dev), priv); 259 259 if (ret) { ··· 262 262 uirq->uirq); 263 263 return ret; 264 264 } 265 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 265 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 266 266 } 267 267 uirq->refcnt++; 268 268 269 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 269 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 270 270 271 271 /* Setup irq */ 272 272 irq_set_chip_data(irq, priv); ··· 290 290 irq_set_chip_and_handler(irq, NULL, NULL); 291 291 irq_set_chip_data(irq, NULL); 292 292 293 - spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 293 + raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); 294 294 295 295 /* Free underlying irq if last user unmapped */ 296 296 index = -1; ··· 309 309 uirq = &priv->uirqs[lirq->index]; 310 310 uirq->refcnt--; 311 311 if (uirq->refcnt == 0) { 312 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 312 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 313 313 free_irq(uirq->uirq, priv); 314 314 return; 315 315 } 316 316 } 317 317 318 - spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 318 + raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); 319 319 } 320 320 321 321 static const struct irq_domain_ops grgpio_irq_domain_ops = {
+9 -9
drivers/gpio/gpio-hlwd.c
··· 65 65 int hwirq; 66 66 u32 emulated_pending; 67 67 68 - spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 68 + raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 69 69 pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); 70 70 pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 71 71 ··· 93 93 /* Mark emulated interrupts as pending */ 94 94 pending |= rising | falling; 95 95 } 96 - spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 96 + raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 97 97 98 98 chained_irq_enter(chip, desc); 99 99 ··· 118 118 unsigned long flags; 119 119 u32 mask; 120 120 121 - spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 121 + raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 122 122 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 123 123 mask &= ~BIT(data->hwirq); 124 124 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); 125 - spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 125 + raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 126 126 } 127 127 128 128 static void hlwd_gpio_irq_unmask(struct irq_data *data) ··· 132 132 unsigned long flags; 133 133 u32 mask; 134 134 135 - spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 135 + raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 136 136 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); 137 137 mask |= BIT(data->hwirq); 138 138 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); 139 - spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 139 + raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 140 140 } 141 141 142 142 static void hlwd_gpio_irq_enable(struct irq_data *data) ··· 173 173 unsigned long flags; 174 174 u32 level; 175 175 176 - spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 176 + raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); 177 177 178 178 hlwd->edge_emulation &= ~BIT(data->hwirq); 179 179 ··· 194 194 hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type); 195 195 break; 196 196 default: 197 - spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 197 + raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 198 198 return -EINVAL; 199 199 } 200 200 201 - spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 201 + raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); 202 202 return 0; 203 203 } 204 204
+6 -6
drivers/gpio/gpio-idt3243x.c
··· 57 57 if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH)) 58 58 return -EINVAL; 59 59 60 - spin_lock_irqsave(&gc->bgpio_lock, flags); 60 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 61 61 62 62 ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL); 63 63 if (sense & IRQ_TYPE_LEVEL_HIGH) ··· 68 68 writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL); 69 69 irq_set_handler_locked(d, handle_level_irq); 70 70 71 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 71 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 72 72 return 0; 73 73 } 74 74 ··· 86 86 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); 87 87 unsigned long flags; 88 88 89 - spin_lock_irqsave(&gc->bgpio_lock, flags); 89 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 90 90 91 91 ctrl->mask_cache |= BIT(d->hwirq); 92 92 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); 93 93 94 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 94 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 95 95 } 96 96 97 97 static void idt_gpio_unmask(struct irq_data *d) ··· 100 100 struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc); 101 101 unsigned long flags; 102 102 103 - spin_lock_irqsave(&gc->bgpio_lock, flags); 103 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 104 104 105 105 ctrl->mask_cache &= ~BIT(d->hwirq); 106 106 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); 107 107 108 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 108 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 109 109 } 110 110 111 111 static int idt_gpio_irq_init_hw(struct gpio_chip *gc)
+2 -2
drivers/gpio/gpio-ixp4xx.c
··· 126 126 int_reg = IXP4XX_REG_GPIT1; 127 127 } 128 128 129 - spin_lock_irqsave(&g->gc.bgpio_lock, flags); 129 + raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags); 130 130 131 131 /* Clear the style for the appropriate pin */ 132 132 val = __raw_readl(g->base + int_reg); ··· 145 145 val |= BIT(d->hwirq); 146 146 __raw_writel(val, g->base + IXP4XX_REG_GPOE); 147 147 148 - spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); 148 + raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); 149 149 150 150 /* This parent only accept level high (asserted) */ 151 151 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
+4 -4
drivers/gpio/gpio-loongson1.c
··· 25 25 { 26 26 unsigned long flags; 27 27 28 - spin_lock_irqsave(&gc->bgpio_lock, flags); 28 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 29 29 __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset), 30 30 gpio_reg_base + GPIO_CFG); 31 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 31 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 32 32 33 33 return 0; 34 34 } ··· 37 37 { 38 38 unsigned long flags; 39 39 40 - spin_lock_irqsave(&gc->bgpio_lock, flags); 40 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 41 41 __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset), 42 42 gpio_reg_base + GPIO_CFG); 43 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 43 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 44 44 } 45 45 46 46 static int ls1x_gpio_probe(struct platform_device *pdev)
+4 -4
drivers/gpio/gpio-menz127.c
··· 64 64 debounce /= 50; 65 65 } 66 66 67 - spin_lock(&gc->bgpio_lock); 67 + raw_spin_lock(&gc->bgpio_lock); 68 68 69 69 db_en = readl(priv->reg_base + MEN_Z127_DBER); 70 70 ··· 79 79 writel(db_en, priv->reg_base + MEN_Z127_DBER); 80 80 writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); 81 81 82 - spin_unlock(&gc->bgpio_lock); 82 + raw_spin_unlock(&gc->bgpio_lock); 83 83 84 84 return 0; 85 85 } ··· 91 91 struct men_z127_gpio *priv = gpiochip_get_data(gc); 92 92 u32 od_en; 93 93 94 - spin_lock(&gc->bgpio_lock); 94 + raw_spin_lock(&gc->bgpio_lock); 95 95 od_en = readl(priv->reg_base + MEN_Z127_ODER); 96 96 97 97 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN) ··· 101 101 od_en &= ~BIT(offset); 102 102 103 103 writel(od_en, priv->reg_base + MEN_Z127_ODER); 104 - spin_unlock(&gc->bgpio_lock); 104 + raw_spin_unlock(&gc->bgpio_lock); 105 105 106 106 return 0; 107 107 }
+9 -9
drivers/gpio/gpio-mlxbf2.c
··· 131 131 u32 arm_gpio_lock_val; 132 132 133 133 mutex_lock(yu_arm_gpio_lock_param.lock); 134 - spin_lock(&gs->gc.bgpio_lock); 134 + raw_spin_lock(&gs->gc.bgpio_lock); 135 135 136 136 arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io); 137 137 ··· 139 139 * When lock active bit[31] is set, ModeX is write enabled 140 140 */ 141 141 if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) { 142 - spin_unlock(&gs->gc.bgpio_lock); 142 + raw_spin_unlock(&gs->gc.bgpio_lock); 143 143 mutex_unlock(yu_arm_gpio_lock_param.lock); 144 144 return -EINVAL; 145 145 } ··· 157 157 __releases(yu_arm_gpio_lock_param.lock) 158 158 { 159 159 writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io); 160 - spin_unlock(&gs->gc.bgpio_lock); 160 + raw_spin_unlock(&gs->gc.bgpio_lock); 161 161 mutex_unlock(yu_arm_gpio_lock_param.lock); 162 162 } 163 163 ··· 237 237 unsigned long flags; 238 238 u32 val; 239 239 240 - spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 240 + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 241 241 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); 242 242 val |= BIT(offset); 243 243 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); ··· 245 245 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 246 246 val |= BIT(offset); 247 247 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 248 - spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 248 + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 249 249 } 250 250 251 251 static void mlxbf2_gpio_irq_disable(struct irq_data *irqd) ··· 256 256 unsigned long flags; 257 257 u32 val; 258 258 259 - spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 259 + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 260 260 val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 261 261 val &= ~BIT(offset); 262 262 writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); 263 - spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 263 + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 264 264 } 265 265 266 266 static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr) ··· 307 307 return -EINVAL; 308 308 } 309 309 310 - spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 310 + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); 311 311 if (fall) { 312 312 val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); 313 313 val |= BIT(offset); ··· 319 319 val |= BIT(offset); 320 320 writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN); 321 321 } 322 - spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 322 + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); 323 323 324 324 return 0; 325 325 }
+11 -11
drivers/gpio/gpio-mmio.c
··· 220 220 unsigned long mask = bgpio_line2mask(gc, gpio); 221 221 unsigned long flags; 222 222 223 - spin_lock_irqsave(&gc->bgpio_lock, flags); 223 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 224 224 225 225 if (val) 226 226 gc->bgpio_data |= mask; ··· 229 229 230 230 gc->write_reg(gc->reg_dat, gc->bgpio_data); 231 231 232 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 232 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 233 233 } 234 234 235 235 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, ··· 248 248 unsigned long mask = bgpio_line2mask(gc, gpio); 249 249 unsigned long flags; 250 250 251 - spin_lock_irqsave(&gc->bgpio_lock, flags); 251 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 252 252 253 253 if (val) 254 254 gc->bgpio_data |= mask; ··· 257 257 258 258 gc->write_reg(gc->reg_set, gc->bgpio_data); 259 259 260 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 260 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 261 261 } 262 262 263 263 static void bgpio_multiple_get_masks(struct gpio_chip *gc, ··· 286 286 unsigned long flags; 287 287 unsigned long set_mask, clear_mask; 288 288 289 - spin_lock_irqsave(&gc->bgpio_lock, flags); 289 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 290 290 291 291 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 292 292 ··· 295 295 296 296 gc->write_reg(reg, gc->bgpio_data); 297 297 298 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 298 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 299 299 } 300 300 301 301 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, ··· 347 347 { 348 348 unsigned long flags; 349 349 350 - spin_lock_irqsave(&gc->bgpio_lock, flags); 350 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 351 351 352 352 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 353 353 ··· 356 356 if (gc->reg_dir_out) 357 357 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 358 358 359 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 359 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 360 360 361 361 return 0; 362 362 } ··· 387 387 { 388 388 unsigned long flags; 389 389 390 - spin_lock_irqsave(&gc->bgpio_lock, flags); 390 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 391 391 392 392 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 393 393 ··· 396 396 if (gc->reg_dir_out) 397 397 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 398 398 399 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 399 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 400 400 } 401 401 402 402 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, ··· 610 610 if (gc->bgpio_bits > BITS_PER_LONG) 611 611 return -EINVAL; 612 612 613 - spin_lock_init(&gc->bgpio_lock); 613 + raw_spin_lock_init(&gc->bgpio_lock); 614 614 gc->parent = dev; 615 615 gc->label = dev_name(dev); 616 616 gc->base = -1;
+6 -6
drivers/gpio/gpio-sifive.c
··· 44 44 unsigned long flags; 45 45 unsigned int trigger; 46 46 47 - spin_lock_irqsave(&chip->gc.bgpio_lock, flags); 47 + raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags); 48 48 trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; 49 49 regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), 50 50 (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0); ··· 54 54 (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0); 55 55 regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), 56 56 (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0); 57 - spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); 57 + raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); 58 58 } 59 59 60 60 static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger) ··· 84 84 /* Switch to input */ 85 85 gc->direction_input(gc, offset); 86 86 87 - spin_lock_irqsave(&gc->bgpio_lock, flags); 87 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 88 88 /* Clear any sticky pending interrupts */ 89 89 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); 90 90 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); 91 91 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); 92 92 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); 93 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 93 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 94 94 95 95 /* Enable interrupts */ 96 96 assign_bit(offset, &chip->irq_state, 1); ··· 116 116 u32 bit = BIT(offset); 117 117 unsigned long flags; 118 118 119 - spin_lock_irqsave(&gc->bgpio_lock, flags); 119 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 120 120 /* Clear all pending interrupts */ 121 121 regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); 122 122 regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); 123 123 regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); 124 124 regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); 125 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 125 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 126 126 127 127 irq_chip_eoi_parent(d); 128 128 }
+2 -2
drivers/gpio/gpio-tb10x.c
··· 62 62 u32 r; 63 63 unsigned long flags; 64 64 65 - spin_lock_irqsave(&gpio->gc.bgpio_lock, flags); 65 + raw_spin_lock_irqsave(&gpio->gc.bgpio_lock, flags); 66 66 67 67 r = tb10x_reg_read(gpio, offs); 68 68 r = (r & ~mask) | (val & mask); 69 69 70 70 tb10x_reg_write(gpio, offs, r); 71 71 72 - spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags); 72 + raw_spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags); 73 73 } 74 74 75 75 static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+4 -4
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
··· 104 104 unsigned long flags; 105 105 unsigned long val; 106 106 107 - spin_lock_irqsave(&gc->bgpio_lock, flags); 107 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 108 108 109 109 val = ioread32(reg) | pinmask; 110 110 iowrite32(val, reg); 111 111 112 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 112 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 113 113 } 114 114 115 115 static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, ··· 118 118 unsigned long flags; 119 119 unsigned long val; 120 120 121 - spin_lock_irqsave(&gc->bgpio_lock, flags); 121 + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 122 122 123 123 val = ioread32(reg) & ~pinmask; 124 124 iowrite32(val, reg); 125 125 126 - spin_unlock_irqrestore(&gc->bgpio_lock, flags); 126 + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 127 127 } 128 128 129 129 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+1 -1
include/linux/gpio/driver.h
··· 436 436 void __iomem *reg_dir_in; 437 437 bool bgpio_dir_unreadable; 438 438 int bgpio_bits; 439 - spinlock_t bgpio_lock; 439 + raw_spinlock_t bgpio_lock; 440 440 unsigned long bgpio_data; 441 441 unsigned long bgpio_dir; 442 442 #endif /* CONFIG_GPIO_GENERIC */