FRV: arrange things such that BRA can reach from the trap table

Arrange the sections in the FRV arch so that a BRA instruction with a
16-bit displacement can always reach from the trap table to entry.S,
tlb-miss.S and break.S.

The problem otherwise is that the linker can insert sufficient code between
the slots in the trap table and the targets of the branch instructions in
those slots that the displacement field in the instruction isn't
sufficiently large. This is because the branch targets were in the .text
section along with most of the other code in the kernel.

Signed-off-by: David Howells <[e-mail]>
Signed-off-by: Andrew Morton <[e-mail]>
Signed-off-by: Linus Torvalds <[e-mail]>

arch/frv/kernel/break.S

···
 # entry point for Break Exceptions/Interrupts
 #
 ###############################################################################
-	.text
+	.section	.text.break
 	.balign		4
 	.globl		__entry_break
 __entry_break:

arch/frv/kernel/entry.S

···
 
 #define nr_syscalls ((syscall_table_size)/4)
 
-	.text
+	.section	.text.entry
 	.balign		4
 
 .macro LEDS val

arch/frv/kernel/vmlinux.lds.S

···
 	  *(.data.init_task)
   }
 
+  . = ALIGN(4096);
+  .data.page_aligned : { *(.data.idt) }
+
+  . = ALIGN(L1_CACHE_BYTES);
+  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
   .trap : {
 	/* trap table management - read entry-table.S before modifying */
 	. = ALIGN(8192);
···
 	*(.trap.break)
   }
 
-  . = ALIGN(4096);
-  .data.page_aligned : { *(.data.idt) }
-
-  . = ALIGN(L1_CACHE_BYTES);
-  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
-
   /* Text and read-only data */
   . = ALIGN(4);
   _text = .;
   _stext = .;
   .text : {
-	*(
-		.text.start .text.*
-#ifdef CONFIG_DEBUG_INFO
-	.init.text
-	.exit.text
-	.exitcall.exit
-#endif
-	)
+	*(.text.start)
+	*(.text.entry)
+	*(.text.break)
+	*(.text.tlbmiss)
 	TEXT_TEXT
 	SCHED_TEXT
 	LOCK_TEXT
+#ifdef CONFIG_DEBUG_INFO
+	*(
+	.init.text
+	.exit.text
+	.exitcall.exit
+	)
+#endif
 	*(.fixup)
 	*(.gnu.warning)
 	*(.exitcall.exit)

arch/frv/mm/tlb-miss.S

···
 #include <asm/highmem.h>
 #include <asm/spr-regs.h>
 
-	.section	.text
+	.section	.text.tlbmiss
 	.balign		4
 
 	.globl		__entry_insn_mmu_miss