tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: pxa: move clk register definitions to driver

The clock register definitions are now used (almost) exclusively in the
clk driver, and that relies on no other mach/*.h header files any more.

Remove the dependency on mach/pxa*-regs.h by addressing the registers
as offsets from a void __iomem * pointer, which is either passed from
a board file, or (for the moment) ioremapped at boot time from a hardcoded
address in case of DT (this should be moved into the DT of course).

Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 3c816d95 fd13f811

+210 -170
+4 -3
arch/arm/mach-pxa/generic.c
··· 19 19 #include <linux/init.h> 20 20 #include <linux/soc/pxa/cpu.h> 21 21 #include <linux/soc/pxa/smemc.h> 22 + #include <linux/clk/pxa.h> 22 23 23 24 #include <asm/mach/map.h> 24 25 #include <asm/mach-types.h> ··· 49 48 void __init pxa_timer_init(void) 50 49 { 51 50 if (cpu_is_pxa25x()) 52 - pxa25x_clocks_init(); 51 + pxa25x_clocks_init(io_p2v(0x41300000)); 53 52 if (cpu_is_pxa27x()) 54 - pxa27x_clocks_init(); 53 + pxa27x_clocks_init(io_p2v(0x41300000)); 55 54 if (cpu_is_pxa3xx()) 56 - pxa3xx_clocks_init(); 55 + pxa3xx_clocks_init(io_p2v(0x41340000), io_p2v(0x41350000)); 57 56 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); 58 57 } 59 58
-3
arch/arm/mach-pxa/generic.h
··· 22 22 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) 23 23 24 24 #define pxa25x_handle_irq icip_handle_irq 25 - extern int __init pxa25x_clocks_init(void); 26 25 extern void __init pxa25x_init_irq(void); 27 26 extern void __init pxa25x_map_io(void); 28 27 extern void __init pxa26x_init_irq(void); 29 28 30 29 #define pxa27x_handle_irq ichp_handle_irq 31 - extern int __init pxa27x_clocks_init(void); 32 30 extern unsigned pxa27x_get_clk_frequency_khz(int); 33 31 extern void __init pxa27x_init_irq(void); 34 32 extern void __init pxa27x_map_io(void); 35 33 36 34 #define pxa3xx_handle_irq ichp_handle_irq 37 - extern int __init pxa3xx_clocks_init(void); 38 35 extern void __init pxa3xx_init_irq(void); 39 36 extern void __init pxa3xx_map_io(void); 40 37
-45
arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
··· 136 136 #define CKEN io_p2v(0x41300004) /* Clock Enable Register */ 137 137 #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */ 138 138 139 - #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ 140 - #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ 141 - #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ 142 - 143 - #define CCCR_CPDIS_BIT (31) 144 - #define CCCR_PPDIS_BIT (30) 145 - #define CCCR_LCD_26_BIT (27) 146 - #define CCCR_A_BIT (25) 147 - 148 - #define CCSR_N2_MASK CCCR_N_MASK 149 - #define CCSR_M_MASK CCCR_M_MASK 150 - #define CCSR_L_MASK CCCR_L_MASK 151 - #define CCSR_N2_SHIFT 7 152 - 153 - #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ 154 - #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ 155 - #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ 156 - #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ 157 - #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ 158 - #define CKEN_IM (20) /* Internal Memory Clock Enable */ 159 - #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ 160 - #define CKEN_USIM (18) /* USIM Unit Clock Enable */ 161 - #define CKEN_MSL (17) /* MSL Unit Clock Enable */ 162 - #define CKEN_LCD (16) /* LCD Unit Clock Enable */ 163 - #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ 164 - #define CKEN_I2C (14) /* I2C Unit Clock Enable */ 165 - #define CKEN_FICP (13) /* FICP Unit Clock Enable */ 166 - #define CKEN_MMC (12) /* MMC Unit Clock Enable */ 167 - #define CKEN_USB (11) /* USB Unit Clock Enable */ 168 - #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ 169 - #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ 170 - #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ 171 - #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ 172 - #define CKEN_I2S (8) /* I2S Unit Clock Enable */ 173 - #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ 174 - #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ 175 - #define CKEN_STUART (5) /* STUART Unit Clock Enable */ 176 - #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ 177 - #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ 178 - #define CKEN_SSP (3) /* SSP Unit Clock Enable */ 179 - #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ 180 - #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ 181 - #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ 182 - #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ 183 - 184 139 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 185 140 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 186 141
-69
arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
··· 131 131 #define CKENC __REG(0x41340024) /* C Clock Enable Register */ 132 132 #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ 133 133 134 - #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ 135 - #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ 136 - #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ 137 - #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ 138 - #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ 139 - 140 - #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ 141 - #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ 142 - #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ 143 - #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ 144 - #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ 145 - #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ 146 - #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ 147 - 148 - #define ACCR_SMCFS(x) (((x) & 0x7) << 23) 149 - #define ACCR_SFLFS(x) (((x) & 0x3) << 18) 150 - #define ACCR_XSPCLK(x) (((x) & 0x3) << 16) 151 - #define ACCR_HSS(x) (((x) & 0x3) << 14) 152 - #define ACCR_DMCFS(x) (((x) & 0x3) << 12) 153 - #define ACCR_XN(x) (((x) & 0x7) << 8) 154 - #define ACCR_XL(x) ((x) & 0x1f) 155 - 156 - /* 157 - * Clock Enable Bit 158 - */ 159 - #define CKEN_LCD 1 /* < LCD Clock Enable */ 160 - #define CKEN_USBH 2 /* < USB host clock enable */ 161 - #define CKEN_CAMERA 3 /* < Camera interface clock enable */ 162 - #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ 163 - #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ 164 - #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ 165 - #define CKEN_SMC 9 /* < Static Memory Controller clock enable */ 166 - #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ 167 - #define CKEN_BOOT 11 /* < Boot rom clock enable */ 168 - #define CKEN_MMC1 12 /* < MMC1 Clock enable */ 169 - #define CKEN_MMC2 13 /* < MMC2 clock enable */ 170 - #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ 171 - #define CKEN_CIR 15 /* < Consumer IR Clock Enable */ 172 - #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ 173 - #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ 174 - #define CKEN_TPM 19 /* < TPM clock enable */ 175 - #define CKEN_UDC 20 /* < UDC clock enable */ 176 - #define CKEN_BTUART 21 /* < BTUART clock enable */ 177 - #define CKEN_FFUART 22 /* < FFUART clock enable */ 178 - #define CKEN_STUART 23 /* < STUART clock enable */ 179 - #define CKEN_AC97 24 /* < AC97 clock enable */ 180 - #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ 181 - #define CKEN_SSP1 26 /* < SSP1 clock enable */ 182 - #define CKEN_SSP2 27 /* < SSP2 clock enable */ 183 - #define CKEN_SSP3 28 /* < SSP3 clock enable */ 184 - #define CKEN_SSP4 29 /* < SSP4 clock enable */ 185 - #define CKEN_MSL0 30 /* < MSL0 clock enable */ 186 - #define CKEN_PWM0 32 /* < PWM[0] clock enable */ 187 - #define CKEN_PWM1 33 /* < PWM[1] clock enable */ 188 - #define CKEN_I2C 36 /* < I2C clock enable */ 189 - #define CKEN_INTC 38 /* < Interrupt controller clock enable */ 190 - #define CKEN_GPIO 39 /* < GPIO clock enable */ 191 - #define CKEN_1WIRE 40 /* < 1-wire clock enable */ 192 - #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ 193 - #define CKEN_MINI_IM 48 /* < Mini-IM */ 194 - #define CKEN_MINI_LCD 49 /* < Mini LCD */ 195 - 196 - #define CKEN_MMC3 5 /* < MMC3 Clock Enable */ 197 - #define CKEN_MVED 43 /* < MVED clock enable */ 198 - 199 - /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ 200 - #define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ 201 - #define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ 202 - 203 134 #endif /* __ASM_ARCH_PXA3XX_REGS_H */
+3 -1
arch/arm/mach-pxa/sleep.S
··· 18 18 19 19 #define MDREFR_KDIV 0x200a4000 // all banks 20 20 #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 21 - 21 + #define CCCR_N_MASK 0x00000380 22 + #define CCCR_M_MASK 0x00000060 23 + #define CCCR_L_MASK 0x0000001f 22 24 .text 23 25 24 26 #ifdef CONFIG_PXA3xx
+3 -1
drivers/clk/pxa/clk-pxa.c
··· 95 95 clk_register_clkdev(clk, con_id, dev_id); 96 96 } 97 97 98 - int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks) 98 + int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, 99 + int nb_clks, void __iomem *clk_regs) 99 100 { 100 101 int i; 101 102 struct pxa_clk *pxa_clk; ··· 108 107 pxa_clk->lp = clks[i].lp; 109 108 pxa_clk->hp = clks[i].hp; 110 109 pxa_clk->gate = clks[i].gate; 110 + pxa_clk->gate.reg = clk_regs + clks[i].cken_reg; 111 111 pxa_clk->gate.lock = &pxa_clk_lock; 112 112 clk = clk_register_composite(NULL, clks[i].name, 113 113 clks[i].parent_names, 2,
+4 -2
drivers/clk/pxa/clk-pxa.h
··· 105 105 struct desc_clk_cken { 106 106 struct clk_hw hw; 107 107 int ckid; 108 + int cken_reg; 108 109 const char *name; 109 110 const char *dev_id; 110 111 const char *con_id; ··· 120 119 #define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \ 121 120 _mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag) \ 122 121 { .ckid = CLK_ ## _name, .name = #_name, \ 122 + .cken_reg = _cken_reg, \ 123 123 .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\ 124 124 .lp = { .mult = _mult_lp, .div = _div_lp }, \ 125 125 .hp = { .mult = _mult_hp, .div = _div_hp }, \ 126 126 .is_in_low_power = is_lp, \ 127 - .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \ 127 + .gate = { .bit_idx = _cken_bit }, \ 128 128 .flags = flag, \ 129 129 } 130 130 #define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \ ··· 149 147 extern void clkdev_pxa_register(int ckid, const char *con_id, 150 148 const char *dev_id, struct clk *clk); 151 149 extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, 152 - int nb_clks); 150 + int nb_clks, void __iomem *clk_regs); 153 151 void clk_pxa_dt_common_init(struct device_node *np); 154 152 155 153 void pxa2xx_core_turbo_switch(bool on);
+10 -8
drivers/clk/pxa/clk-pxa25x.c
··· 14 14 #include <linux/clkdev.h> 15 15 #include <linux/io.h> 16 16 #include <linux/of.h> 17 - #include <mach/pxa2xx-regs.h> 18 17 #include <linux/soc/pxa/smemc.h> 19 18 20 19 #include <dt-bindings/clock/pxa-clock.h> 21 20 #include "clk-pxa.h" 21 + #include "clk-pxa2xx.h" 22 22 23 23 #define KHz 1000 24 24 #define MHz (1000 * 1000) ··· 39 39 /* 40 40 * Various clock factors driven by the CCCR register. 41 41 */ 42 + static void __iomem *clk_regs; 42 43 43 44 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 44 45 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; ··· 98 97 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw, 99 98 unsigned long parent_rate) 100 99 { 101 - unsigned long cccr = readl(CCCR); 100 + unsigned long cccr = readl(clk_regs + CCCR); 102 101 unsigned int m = M_clk_mult[(cccr >> 5) & 0x03]; 103 102 104 103 return parent_rate / m; ··· 202 201 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw, 203 202 unsigned long parent_rate) 204 203 { 205 - unsigned long cccr = readl(CCCR); 204 + unsigned long cccr = readl(clk_regs + CCCR); 206 205 unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 207 206 208 207 return (parent_rate / n2) * 2; ··· 213 212 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw, 214 213 unsigned long parent_rate) 215 214 { 216 - unsigned long clkcfg, cccr = readl(CCCR); 215 + unsigned long clkcfg, cccr = readl(clk_regs + CCCR); 217 216 unsigned int l, m, n2, t; 218 217 219 218 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); ··· 245 244 if (i >= ARRAY_SIZE(pxa25x_freqs)) 246 245 return -EINVAL; 247 246 248 - pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, CCCR); 247 + pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR); 249 248 250 249 return 0; 251 250 } ··· 322 321 } 323 322 } 324 323 325 - int __init pxa25x_clocks_init(void) 324 + int __init pxa25x_clocks_init(void __iomem *regs) 326 325 { 326 + clk_regs = regs; 327 327 pxa25x_base_clocks_init(); 328 328 pxa25x_dummy_clocks_init(); 329 - return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks)); 329 + return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs); 330 330 } 331 331 332 332 static void __init pxa25x_dt_clocks_init(struct device_node *np) 333 333 { 334 - pxa25x_clocks_init(); 334 + pxa25x_clocks_init(ioremap(0x41300000ul, 0x10)); 335 335 clk_pxa_dt_common_init(np); 336 336 } 337 337 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
+21 -18
drivers/clk/pxa/clk-pxa27x.c
··· 7 7 * Heavily inspired from former arch/arm/mach-pxa/clock.c. 8 8 */ 9 9 #include <linux/clk-provider.h> 10 - #include <mach/pxa2xx-regs.h> 11 10 #include <linux/io.h> 12 11 #include <linux/clk.h> 13 12 #include <linux/clkdev.h> ··· 15 16 16 17 #include <dt-bindings/clock/pxa-clock.h> 17 18 #include "clk-pxa.h" 19 + #include "clk-pxa2xx.h" 18 20 19 21 #define KHz 1000 20 22 #define MHz (1000 * 1000) ··· 51 51 52 52 /* Define the refresh period in mSec for the SDRAM and the number of rows */ 53 53 #define SDRAM_TREF 64 /* standard 64ms SDRAM */ 54 + 55 + static void __iomem *clk_regs; 54 56 55 57 static const char * const get_freq_khz[] = { 56 58 "core", "run", "cpll", "memory", ··· 101 99 102 100 bool pxa27x_is_ppll_disabled(void) 103 101 { 104 - unsigned long ccsr = readl(CCSR); 102 + unsigned long ccsr = readl(clk_regs + CCSR); 105 103 106 104 return ccsr & (1 << CCCR_PPDIS_BIT); 107 105 } ··· 203 201 unsigned long clkcfg; 204 202 unsigned int t, ht; 205 203 unsigned int l, L, n2, N; 206 - unsigned long ccsr = readl(CCSR); 204 + unsigned long ccsr = readl(clk_regs + CCSR); 207 205 208 206 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); 209 207 t = clkcfg & (1 << 0); ··· 237 235 if (i >= ARRAY_SIZE(pxa27x_freqs)) 238 236 return -EINVAL; 239 237 240 - pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, CCCR); 238 + pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR); 241 239 return 0; 242 240 } 243 241 ··· 248 246 unsigned long parent_rate) 249 247 { 250 248 unsigned int l, osc_forced; 251 - unsigned long ccsr = readl(CCSR); 252 - unsigned long cccr = readl(CCCR); 249 + unsigned long ccsr = readl(clk_regs + CCSR); 250 + unsigned long cccr = readl(clk_regs + CCCR); 253 251 254 252 l = ccsr & CCSR_L_MASK; 255 253 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); ··· 270 268 static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw) 271 269 { 272 270 unsigned int osc_forced; 273 - unsigned long ccsr = readl(CCSR); 271 + unsigned long ccsr = readl(clk_regs + CCSR); 274 272 275 273 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 276 274 if (osc_forced) ··· 299 297 { 300 298 unsigned long clkcfg; 301 299 unsigned int t, ht, osc_forced; 302 - unsigned long ccsr = readl(CCSR); 300 + unsigned long ccsr = readl(clk_regs + CCSR); 303 301 304 302 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 305 303 if (osc_forced) ··· 336 334 static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw, 337 335 unsigned long parent_rate) 338 336 { 339 - unsigned long ccsr = readl(CCSR); 337 + unsigned long ccsr = readl(clk_regs + CCSR); 340 338 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; 341 339 342 340 return (parent_rate / n2) * 2; ··· 359 357 { 360 358 unsigned long clkcfg; 361 359 unsigned int b, osc_forced; 362 - unsigned long ccsr = readl(CCSR); 360 + unsigned long ccsr = readl(clk_regs + CCSR); 363 361 364 362 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 365 363 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); ··· 376 374 static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw) 377 375 { 378 376 unsigned int osc_forced; 379 - unsigned long ccsr = readl(CCSR); 377 + unsigned long ccsr = readl(clk_regs + CCSR); 380 378 381 379 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 382 380 if (osc_forced) ··· 392 390 unsigned long parent_rate) 393 391 { 394 392 unsigned int a, l, osc_forced; 395 - unsigned long cccr = readl(CCCR); 396 - unsigned long ccsr = readl(CCSR); 393 + unsigned long cccr = readl(clk_regs + CCCR); 394 + unsigned long ccsr = readl(clk_regs + CCSR); 397 395 398 396 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 399 397 a = cccr & (1 << CCCR_A_BIT); ··· 411 409 static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) 412 410 { 413 411 unsigned int osc_forced, a; 414 - unsigned long cccr = readl(CCCR); 415 - unsigned long ccsr = readl(CCSR); 412 + unsigned long cccr = readl(clk_regs + CCCR); 413 + unsigned long ccsr = readl(clk_regs + CCSR); 416 414 417 415 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); 418 416 a = cccr & (1 << CCCR_A_BIT); ··· 467 465 clk_register_clk_pxa27x_lcd_base(); 468 466 } 469 467 470 - int __init pxa27x_clocks_init(void) 468 + int __init pxa27x_clocks_init(void __iomem *regs) 471 469 { 470 + clk_regs = regs; 472 471 pxa27x_base_clocks_init(); 473 472 pxa27x_dummy_clocks_init(); 474 - return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks)); 473 + return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), regs); 475 474 } 476 475 477 476 static void __init pxa27x_dt_clocks_init(struct device_node *np) 478 477 { 479 - pxa27x_clocks_init(); 478 + pxa27x_clocks_init(ioremap(0x41300000ul, 0x10)); 480 479 clk_pxa_dt_common_init(np); 481 480 } 482 481 CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
+58
drivers/clk/pxa/clk-pxa2xx.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + #ifndef __CLK_PXA2XX_H 3 + #define __CLK_PXA2XX_H 4 + 5 + #define CCCR (0x0000) /* Core Clock Configuration Register */ 6 + #define CCSR (0x000C) /* Core Clock Status Register */ 7 + #define CKEN (0x0004) /* Clock Enable Register */ 8 + #define OSCC (0x0008) /* Oscillator Configuration Register */ 9 + 10 + #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ 11 + #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ 12 + #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ 13 + 14 + #define CCCR_CPDIS_BIT (31) 15 + #define CCCR_PPDIS_BIT (30) 16 + #define CCCR_LCD_26_BIT (27) 17 + #define CCCR_A_BIT (25) 18 + 19 + #define CCSR_N2_MASK CCCR_N_MASK 20 + #define CCSR_M_MASK CCCR_M_MASK 21 + #define CCSR_L_MASK CCCR_L_MASK 22 + #define CCSR_N2_SHIFT 7 23 + 24 + #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ 25 + #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ 26 + #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ 27 + #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ 28 + #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ 29 + #define CKEN_IM (20) /* Internal Memory Clock Enable */ 30 + #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ 31 + #define CKEN_USIM (18) /* USIM Unit Clock Enable */ 32 + #define CKEN_MSL (17) /* MSL Unit Clock Enable */ 33 + #define CKEN_LCD (16) /* LCD Unit Clock Enable */ 34 + #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ 35 + #define CKEN_I2C (14) /* I2C Unit Clock Enable */ 36 + #define CKEN_FICP (13) /* FICP Unit Clock Enable */ 37 + #define CKEN_MMC (12) /* MMC Unit Clock Enable */ 38 + #define CKEN_USB (11) /* USB Unit Clock Enable */ 39 + #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ 40 + #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ 41 + #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ 42 + #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ 43 + #define CKEN_I2S (8) /* I2S Unit Clock Enable */ 44 + #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ 45 + #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ 46 + #define CKEN_STUART (5) /* STUART Unit Clock Enable */ 47 + #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ 48 + #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ 49 + #define CKEN_SSP (3) /* SSP Unit Clock Enable */ 50 + #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ 51 + #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ 52 + #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ 53 + #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ 54 + 55 + #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 56 + #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 57 + 58 + #endif
+100 -20
drivers/clk/pxa/clk-pxa3xx.c
··· 17 17 #include <linux/soc/pxa/cpu.h> 18 18 #include <linux/soc/pxa/smemc.h> 19 19 #include <linux/clk/pxa.h> 20 - #include <mach/pxa3xx-regs.h> 21 20 22 21 #include <dt-bindings/clock/pxa-clock.h> 23 22 #include "clk-pxa.h" 24 23 25 24 #define KHz 1000 26 25 #define MHz (1000 * 1000) 26 + 27 + #define ACCR (0x0000) /* Application Subsystem Clock Configuration Register */ 28 + #define ACSR (0x0004) /* Application Subsystem Clock Status Register */ 29 + #define AICSR (0x0008) /* Application Subsystem Interrupt Control/Status Register */ 30 + #define CKENA (0x000C) /* A Clock Enable Register */ 31 + #define CKENB (0x0010) /* B Clock Enable Register */ 32 + #define CKENC (0x0024) /* C Clock Enable Register */ 33 + #define AC97_DIV (0x0014) /* AC97 clock divisor value register */ 34 + 35 + #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ 36 + #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ 37 + #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ 38 + #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ 39 + #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ 40 + 41 + #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ 42 + #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ 43 + #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ 44 + #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ 45 + #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ 46 + #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ 47 + #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ 48 + 49 + #define ACCR_SMCFS(x) (((x) & 0x7) << 23) 50 + #define ACCR_SFLFS(x) (((x) & 0x3) << 18) 51 + #define ACCR_XSPCLK(x) (((x) & 0x3) << 16) 52 + #define ACCR_HSS(x) (((x) & 0x3) << 14) 53 + #define ACCR_DMCFS(x) (((x) & 0x3) << 12) 54 + #define ACCR_XN(x) (((x) & 0x7) << 8) 55 + #define ACCR_XL(x) ((x) & 0x1f) 56 + 57 + /* 58 + * Clock Enable Bit 59 + */ 60 + #define CKEN_LCD 1 /* < LCD Clock Enable */ 61 + #define CKEN_USBH 2 /* < USB host clock enable */ 62 + #define CKEN_CAMERA 3 /* < Camera interface clock enable */ 63 + #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ 64 + #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ 65 + #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ 66 + #define CKEN_SMC 9 /* < Static Memory Controller clock enable */ 67 + #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ 68 + #define CKEN_BOOT 11 /* < Boot rom clock enable */ 69 + #define CKEN_MMC1 12 /* < MMC1 Clock enable */ 70 + #define CKEN_MMC2 13 /* < MMC2 clock enable */ 71 + #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ 72 + #define CKEN_CIR 15 /* < Consumer IR Clock Enable */ 73 + #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ 74 + #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ 75 + #define CKEN_TPM 19 /* < TPM clock enable */ 76 + #define CKEN_UDC 20 /* < UDC clock enable */ 77 + #define CKEN_BTUART 21 /* < BTUART clock enable */ 78 + #define CKEN_FFUART 22 /* < FFUART clock enable */ 79 + #define CKEN_STUART 23 /* < STUART clock enable */ 80 + #define CKEN_AC97 24 /* < AC97 clock enable */ 81 + #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ 82 + #define CKEN_SSP1 26 /* < SSP1 clock enable */ 83 + #define CKEN_SSP2 27 /* < SSP2 clock enable */ 84 + #define CKEN_SSP3 28 /* < SSP3 clock enable */ 85 + #define CKEN_SSP4 29 /* < SSP4 clock enable */ 86 + #define CKEN_MSL0 30 /* < MSL0 clock enable */ 87 + #define CKEN_PWM0 32 /* < PWM[0] clock enable */ 88 + #define CKEN_PWM1 33 /* < PWM[1] clock enable */ 89 + #define CKEN_I2C 36 /* < I2C clock enable */ 90 + #define CKEN_INTC 38 /* < Interrupt controller clock enable */ 91 + #define CKEN_GPIO 39 /* < GPIO clock enable */ 92 + #define CKEN_1WIRE 40 /* < 1-wire clock enable */ 93 + #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ 94 + #define CKEN_MINI_IM 48 /* < Mini-IM */ 95 + #define CKEN_MINI_LCD 49 /* < Mini LCD */ 96 + 97 + #define CKEN_MMC3 5 /* < MMC3 Clock Enable */ 98 + #define CKEN_MVED 43 /* < MVED clock enable */ 99 + 100 + /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ 101 + #define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ 102 + #define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ 103 + 27 104 28 105 enum { 29 106 PXA_CORE_60Mhz = 0, ··· 121 44 static const char * const get_freq_khz[] = { 122 45 "core", "ring_osc_60mhz", "run", "cpll", "system_bus" 123 46 }; 47 + 48 + static void __iomem *clk_regs; 124 49 125 50 /* 126 51 * Get the clock frequency as reflected by ACSR and the turbo flag. ··· 159 80 160 81 void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask) 161 82 { 162 - u32 accr = ACCR; 83 + u32 accr = readl(clk_regs + ACCR); 163 84 164 85 accr &= ~disable; 165 86 accr |= enable; 166 87 167 - ACCR = accr; 88 + writel(accr, ACCR); 168 89 if (xclkcfg) 169 90 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg)); 170 91 171 - while ((ACSR & mask) != (accr & mask)) 92 + while ((readl(clk_regs + ACSR) & mask) != (accr & mask)) 172 93 cpu_relax(); 173 94 } 174 95 ··· 177 98 { 178 99 unsigned long ac97_div, rate; 179 100 180 - ac97_div = AC97_DIV; 101 + ac97_div = readl(clk_regs + AC97_DIV); 181 102 182 103 /* This may loose precision for some rates but won't for the 183 104 * standard 24.576MHz. ··· 194 115 static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw, 195 116 unsigned long parent_rate) 196 117 { 197 - unsigned long acsr = ACSR; 118 + unsigned long acsr = readl(clk_regs + ACSR); 198 119 199 120 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / 200 121 pxa3xx_smemc_get_memclkdiv(); ··· 205 126 206 127 static bool pxa3xx_is_ring_osc_forced(void) 207 128 { 208 - unsigned long acsr = ACSR; 129 + unsigned long acsr = readl(clk_regs + ACSR); 209 130 210 131 return acsr & ACCR_D0CS; 211 132 } ··· 217 138 PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" }; 218 139 PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" }; 219 140 220 - #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA) 141 + #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? CKENB : CKENA) 221 142 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \ 222 143 div_hp, bit, is_lp, flags) \ 223 144 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \ ··· 285 206 static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw, 286 207 unsigned long parent_rate) 287 208 { 288 - unsigned long acsr = ACSR; 209 + unsigned long acsr = readl(clk_regs + ACSR); 289 210 unsigned int hss = (acsr >> 14) & 0x3; 290 211 291 212 if (pxa3xx_is_ring_osc_forced()) ··· 332 253 static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw, 333 254 unsigned long parent_rate) 334 255 { 335 - unsigned long acsr = ACSR; 256 + unsigned long acsr = readl(clk_regs + ACSR); 336 257 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8; 337 258 unsigned int t, xclkcfg; 338 259 ··· 348 269 static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw, 349 270 unsigned long parent_rate) 350 271 { 351 - unsigned long acsr = ACSR; 272 + unsigned long acsr = readl(clk_regs + ACSR); 352 273 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8; 353 274 unsigned int xl = acsr & ACCR_XL_MASK; 354 275 unsigned int t, xclkcfg; ··· 419 340 } 420 341 } 421 342 422 - static void __init pxa3xx_base_clocks_init(void) 343 + static void __init pxa3xx_base_clocks_init(void __iomem *oscc_reg) 423 344 { 424 345 struct clk *clk; 425 346 ··· 429 350 clk_register_clk_pxa3xx_ac97(); 430 351 clk_register_clk_pxa3xx_smemc(); 431 352 clk = clk_register_gate(NULL, "CLK_POUT", 432 - "osc_13mhz", 0, OSCC, 11, 0, NULL); 353 + "osc_13mhz", 0, oscc_reg, 11, 0, NULL); 433 354 clk_register_clkdev(clk, "CLK_POUT", NULL); 434 355 clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL, 435 356 clk_register_fixed_factor(NULL, "os-timer0", 436 357 "osc_13mhz", 0, 1, 4)); 437 358 } 438 359 439 - int __init pxa3xx_clocks_init(void) 360 + int __init pxa3xx_clocks_init(void __iomem *regs, void __iomem *oscc_reg) 440 361 { 441 362 int ret; 442 363 443 - pxa3xx_base_clocks_init(); 364 + clk_regs = regs; 365 + pxa3xx_base_clocks_init(oscc_reg); 444 366 pxa3xx_dummy_clocks_init(); 445 - ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks)); 367 + ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks), regs); 446 368 if (ret) 447 369 return ret; 448 370 if (cpu_is_pxa320()) 449 371 return clk_pxa_cken_init(pxa320_clocks, 450 - ARRAY_SIZE(pxa320_clocks)); 372 + ARRAY_SIZE(pxa320_clocks), regs); 451 373 if (cpu_is_pxa300() || cpu_is_pxa310()) 452 374 return clk_pxa_cken_init(pxa300_310_clocks, 453 - ARRAY_SIZE(pxa300_310_clocks)); 454 - return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks)); 375 + ARRAY_SIZE(pxa300_310_clocks), regs); 376 + return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks), regs); 455 377 } 456 378 457 379 static void __init pxa3xx_dt_clocks_init(struct device_node *np) 458 380 { 459 - pxa3xx_clocks_init(); 381 + pxa3xx_clocks_init(ioremap(0x41340000, 0x10), ioremap(0x41350000, 4)); 460 382 clk_pxa_dt_common_init(np); 461 383 } 462 384 CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);
+7
include/linux/clk/pxa.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 3 + #include <linux/compiler.h> 4 + #include <linux/types.h> 5 + 6 + extern int pxa25x_clocks_init(void __iomem *regs); 7 + extern int pxa27x_clocks_init(void __iomem *regs); 8 + extern int pxa3xx_clocks_init(void __iomem *regs, void __iomem *oscc_reg); 9 + 3 10 #ifdef CONFIG_PXA3xx 4 11 extern unsigned pxa3xx_get_clk_frequency_khz(int); 5 12 extern void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask);