tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: vce use multiple cache surface starting from stoney
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Leo Liu
and committed by
Alex Deucher
3c0ff9f1
d6c29c30
+14
-5
+14
-5
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+14
-5
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
···
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#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
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#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
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+
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
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#define VCE_V3_0_FW_SIZE (384 * 1024)
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#define VCE_V3_0_STACK_SIZE (64 * 1024)
···
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/* set BUSY flag */
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WREG32_P(mmVCE_STATUS, 1, ~1);
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-
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
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~VCE_VCPU_CNTL__CLK_EN_MASK);
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if (adev->asic_type >= CHIP_STONEY)
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WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
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else
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
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~VCE_VCPU_CNTL__CLK_EN_MASK);
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
···
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WREG32(mmVCE_LMI_SWAP_CNTL, 0);
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WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
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WREG32(mmVCE_LMI_VM_CTRL, 0);
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-
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
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if (adev->asic_type >= CHIP_STONEY) {
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
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} else
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WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
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offset = AMDGPU_VCE_FIRMWARE_OFFSET;
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size = VCE_V3_0_FW_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);