Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

pinctrl: stm32: Implement .pin_config_dbg_show()

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Patrice Chotard and committed by
Linus Walleij
3beed93c caee57ec

+174
+174
drivers/pinctrl/stm32/pinctrl-stm32.c
··· 454 454 clk_disable(bank->clk); 455 455 } 456 456 457 + static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, 458 + int pin, u32 *mode, u32 *alt) 459 + { 460 + u32 val; 461 + int alt_shift = (pin % 8) * 4; 462 + int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 463 + unsigned long flags; 464 + 465 + clk_enable(bank->clk); 466 + spin_lock_irqsave(&bank->lock, flags); 467 + 468 + val = readl_relaxed(bank->base + alt_offset); 469 + val &= GENMASK(alt_shift + 3, alt_shift); 470 + *alt = val >> alt_shift; 471 + 472 + val = readl_relaxed(bank->base + STM32_GPIO_MODER); 473 + val &= GENMASK(pin * 2 + 1, pin * 2); 474 + *mode = val >> (pin * 2); 475 + 476 + spin_unlock_irqrestore(&bank->lock, flags); 477 + clk_disable(bank->clk); 478 + } 479 + 457 480 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 458 481 unsigned function, 459 482 unsigned group) ··· 548 525 clk_disable(bank->clk); 549 526 } 550 527 528 + static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 529 + unsigned int offset) 530 + { 531 + unsigned long flags; 532 + u32 val; 533 + 534 + clk_enable(bank->clk); 535 + spin_lock_irqsave(&bank->lock, flags); 536 + 537 + val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 538 + val &= BIT(offset); 539 + 540 + spin_unlock_irqrestore(&bank->lock, flags); 541 + clk_disable(bank->clk); 542 + 543 + return (val >> offset); 544 + } 545 + 551 546 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 552 547 unsigned offset, u32 speed) 553 548 { ··· 584 543 clk_disable(bank->clk); 585 544 } 586 545 546 + static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 547 + unsigned int offset) 548 + { 549 + unsigned long flags; 550 + u32 val; 551 + 552 + clk_enable(bank->clk); 553 + spin_lock_irqsave(&bank->lock, flags); 554 + 555 + val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 556 + val &= GENMASK(offset * 2 + 1, offset * 2); 557 + 558 + spin_unlock_irqrestore(&bank->lock, flags); 559 + clk_disable(bank->clk); 560 + 561 + return (val >> (offset * 2)); 562 + } 563 + 587 564 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 588 565 unsigned offset, u32 bias) 589 566 { ··· 618 559 619 560 spin_unlock_irqrestore(&bank->lock, flags); 620 561 clk_disable(bank->clk); 562 + } 563 + 564 + static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 565 + unsigned int offset) 566 + { 567 + unsigned long flags; 568 + u32 val; 569 + 570 + clk_enable(bank->clk); 571 + spin_lock_irqsave(&bank->lock, flags); 572 + 573 + val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 574 + val &= GENMASK(offset * 2 + 1, offset * 2); 575 + 576 + spin_unlock_irqrestore(&bank->lock, flags); 577 + clk_disable(bank->clk); 578 + 579 + return (val >> (offset * 2)); 580 + } 581 + 582 + static bool stm32_pconf_input_get(struct stm32_gpio_bank *bank, 583 + unsigned int offset) 584 + { 585 + unsigned long flags; 586 + u32 val; 587 + 588 + clk_enable(bank->clk); 589 + spin_lock_irqsave(&bank->lock, flags); 590 + 591 + val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 592 + 593 + spin_unlock_irqrestore(&bank->lock, flags); 594 + clk_disable(bank->clk); 595 + 596 + return val; 597 + } 598 + 599 + static bool stm32_pconf_output_get(struct stm32_gpio_bank *bank, 600 + unsigned int offset) 601 + { 602 + unsigned long flags; 603 + u32 val; 604 + 605 + clk_enable(bank->clk); 606 + spin_lock_irqsave(&bank->lock, flags); 607 + val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & BIT(offset)); 608 + 609 + spin_unlock_irqrestore(&bank->lock, flags); 610 + clk_disable(bank->clk); 611 + 612 + return val; 621 613 } 622 614 623 615 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, ··· 744 634 return 0; 745 635 } 746 636 637 + static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 638 + struct seq_file *s, 639 + unsigned int pin) 640 + { 641 + struct pinctrl_gpio_range *range; 642 + struct stm32_gpio_bank *bank; 643 + int offset; 644 + u32 mode, alt, drive, speed, bias; 645 + static const char * const modes[] = { 646 + "input", "output", "alternate", "analog" }; 647 + static const char * const speeds[] = { 648 + "low", "medium", "high", "very high" }; 649 + static const char * const biasing[] = { 650 + "floating", "pull up", "pull down", "" }; 651 + bool val; 652 + 653 + range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 654 + bank = gpio_range_to_bank(range); 655 + offset = stm32_gpio_pin(pin); 656 + 657 + stm32_pmx_get_mode(bank, offset, &mode, &alt); 658 + bias = stm32_pconf_get_bias(bank, offset); 659 + 660 + seq_printf(s, "%s ", modes[mode]); 661 + 662 + switch (mode) { 663 + /* input */ 664 + case 0: 665 + val = stm32_pconf_input_get(bank, offset); 666 + seq_printf(s, "- %s - %s", 667 + val ? "high" : "low", 668 + biasing[bias]); 669 + break; 670 + 671 + /* output */ 672 + case 1: 673 + drive = stm32_pconf_get_driving(bank, offset); 674 + speed = stm32_pconf_get_speed(bank, offset); 675 + val = stm32_pconf_output_get(bank, offset); 676 + seq_printf(s, "- %s - %s - %s - %s %s", 677 + val ? "high" : "low", 678 + drive ? "open drain" : "push pull", 679 + biasing[bias], 680 + speeds[speed], "speed"); 681 + break; 682 + 683 + /* alternate */ 684 + case 2: 685 + drive = stm32_pconf_get_driving(bank, offset); 686 + speed = stm32_pconf_get_speed(bank, offset); 687 + seq_printf(s, "%d - %s -%s", alt, 688 + drive ? "open drain" : "push pull", 689 + biasing[bias], 690 + speeds[speed], "speed"); 691 + break; 692 + 693 + /* analog */ 694 + case 3: 695 + break; 696 + } 697 + } 698 + 699 + 747 700 static const struct pinconf_ops stm32_pconf_ops = { 748 701 .pin_config_group_get = stm32_pconf_group_get, 749 702 .pin_config_group_set = stm32_pconf_group_set, 703 + .pin_config_dbg_show = stm32_pconf_dbg_show, 750 704 }; 751 705 752 706 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,