tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ucc_geth: use correct UCCE macros

The UCC Event Register (UCCE) already has unambigous macro definitions in qe.h,
so we should not be defining our own in the UCC Ethernet driver.

Removed unused local variable 'dev' from ucc_geth_poll(), which fixes
a warning caused by commit 908a7a16b852ffd618a9127be8d62432182d81b4
("net: Remove unused netdev arg from some NAPI interfaces.").

Replaced in_be/out_be pairs with setbits32 or clrbits32, where applicable.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Timur Tabi and committed by
David S. Miller 3bc53427 649274d9

+64 -170
+43 -85
drivers/net/ucc_geth.c
··· 442 442 { 443 443 struct ucc_fast_private *uccf; 444 444 struct ucc_geth __iomem *ug_regs; 445 - u32 maccfg2, uccm; 446 445 447 446 uccf = ugeth->uccf; 448 447 ug_regs = ugeth->ug_regs; 449 448 450 449 /* Enable interrupts for magic packet detection */ 451 - uccm = in_be32(uccf->p_uccm); 452 - uccm |= UCCE_MPD; 453 - out_be32(uccf->p_uccm, uccm); 450 + setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD); 454 451 455 452 /* Enable magic packet detection */ 456 - maccfg2 = in_be32(&ug_regs->maccfg2); 457 - maccfg2 |= MACCFG2_MPE; 458 - out_be32(&ug_regs->maccfg2, maccfg2); 453 + setbits32(&ug_regs->maccfg2, MACCFG2_MPE); 459 454 } 460 455 461 456 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth) 462 457 { 463 458 struct ucc_fast_private *uccf; 464 459 struct ucc_geth __iomem *ug_regs; 465 - u32 maccfg2, uccm; 466 460 467 461 uccf = ugeth->uccf; 468 462 ug_regs = ugeth->ug_regs; 469 463 470 464 /* Disable interrupts for magic packet detection */ 471 - uccm = in_be32(uccf->p_uccm); 472 - uccm &= ~UCCE_MPD; 473 - out_be32(uccf->p_uccm, uccm); 465 + clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD); 474 466 475 467 /* Disable magic packet detection */ 476 - maccfg2 = in_be32(&ug_regs->maccfg2); 477 - maccfg2 &= ~MACCFG2_MPE; 478 - out_be32(&ug_regs->maccfg2, maccfg2); 468 + clrbits32(&ug_regs->maccfg2, MACCFG2_MPE); 479 469 } 480 470 #endif /* MAGIC_PACKET */ 481 471 ··· 575 585 576 586 /* Hardware only if user handed pointer and driver actually 577 587 gathers hardware statistics */ 578 - if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) { 588 + if (hardware_statistics && 589 + (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 579 590 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 580 591 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 581 592 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); ··· 1172 1181 out_be32(uempr_register, value); 1173 1182 1174 1183 /* Set UPSMR register */ 1175 - value = in_be32(upsmr_register); 1176 - value |= automatic_flow_control_mode; 1177 - out_be32(upsmr_register, value); 1184 + setbits32(upsmr_register, automatic_flow_control_mode); 1178 1185 1179 1186 value = in_be32(maccfg1_register); 1180 1187 if (rx_flow_control_enable) ··· 1189 1200 u32 __iomem *upsmr_register, 1190 1201 u16 __iomem *uescr_register) 1191 1202 { 1192 - u32 upsmr_value = 0; 1193 1203 u16 uescr_value = 0; 1204 + 1194 1205 /* Enable hardware statistics gathering if requested */ 1195 - if (enable_hardware_statistics) { 1196 - upsmr_value = in_be32(upsmr_register); 1197 - upsmr_value |= UPSMR_HSE; 1198 - out_be32(upsmr_register, upsmr_value); 1199 - } 1206 + if (enable_hardware_statistics) 1207 + setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1200 1208 1201 1209 /* Clear hardware statistics counters */ 1202 1210 uescr_value = in_be16(uescr_register); ··· 1219 1233 { 1220 1234 /* Note: this function does not check if */ 1221 1235 /* the parameters it receives are NULL */ 1222 - u16 temoder_value; 1223 - u32 remoder_value; 1224 1236 1225 1237 if (enable_tx_firmware_statistics) { 1226 1238 out_be32(tx_rmon_base_ptr, 1227 1239 tx_firmware_statistics_structure_address); 1228 - temoder_value = in_be16(temoder_register); 1229 - temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE; 1230 - out_be16(temoder_register, temoder_value); 1240 + setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1231 1241 } 1232 1242 1233 1243 if (enable_rx_firmware_statistics) { 1234 1244 out_be32(rx_rmon_base_ptr, 1235 1245 rx_firmware_statistics_structure_address); 1236 - remoder_value = in_be32(remoder_register); 1237 - remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE; 1238 - out_be32(remoder_register, remoder_value); 1246 + setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1239 1247 } 1240 1248 1241 1249 return 0; ··· 1296 1316 static int init_preamble_length(u8 preamble_length, 1297 1317 u32 __iomem *maccfg2_register) 1298 1318 { 1299 - u32 value = 0; 1300 - 1301 1319 if ((preamble_length < 3) || (preamble_length > 7)) 1302 1320 return -EINVAL; 1303 1321 1304 - value = in_be32(maccfg2_register); 1305 - value &= ~MACCFG2_PREL_MASK; 1306 - value |= (preamble_length << MACCFG2_PREL_SHIFT); 1307 - out_be32(maccfg2_register, value); 1322 + clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1323 + preamble_length << MACCFG2_PREL_SHIFT); 1324 + 1308 1325 return 0; 1309 1326 } 1310 1327 ··· 1314 1337 value = in_be32(upsmr_register); 1315 1338 1316 1339 if (reject_broadcast) 1317 - value |= UPSMR_BRO; 1340 + value |= UCC_GETH_UPSMR_BRO; 1318 1341 else 1319 - value &= ~UPSMR_BRO; 1342 + value &= ~UCC_GETH_UPSMR_BRO; 1320 1343 1321 1344 if (receive_short_frames) 1322 - value |= UPSMR_RSH; 1345 + value |= UCC_GETH_UPSMR_RSH; 1323 1346 else 1324 - value &= ~UPSMR_RSH; 1347 + value &= ~UCC_GETH_UPSMR_RSH; 1325 1348 1326 1349 if (promiscuous) 1327 - value |= UPSMR_PRO; 1350 + value |= UCC_GETH_UPSMR_PRO; 1328 1351 else 1329 - value &= ~UPSMR_PRO; 1352 + value &= ~UCC_GETH_UPSMR_PRO; 1330 1353 1331 1354 out_be32(upsmr_register, value); 1332 1355 ··· 1387 1410 1388 1411 /* Set UPSMR */ 1389 1412 upsmr = in_be32(&uf_regs->upsmr); 1390 - upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM); 1413 + upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1414 + UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1391 1415 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1392 1416 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1393 1417 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1394 1418 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1395 1419 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1396 1420 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1397 - upsmr |= UPSMR_RPM; 1421 + upsmr |= UCC_GETH_UPSMR_RPM; 1398 1422 switch (ugeth->max_speed) { 1399 1423 case SPEED_10: 1400 - upsmr |= UPSMR_R10M; 1424 + upsmr |= UCC_GETH_UPSMR_R10M; 1401 1425 /* FALLTHROUGH */ 1402 1426 case SPEED_100: 1403 1427 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1404 - upsmr |= UPSMR_RMM; 1428 + upsmr |= UCC_GETH_UPSMR_RMM; 1405 1429 } 1406 1430 } 1407 1431 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1408 1432 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1409 - upsmr |= UPSMR_TBIM; 1433 + upsmr |= UCC_GETH_UPSMR_TBIM; 1410 1434 } 1411 1435 out_be32(&uf_regs->upsmr, upsmr); 1412 1436 ··· 1495 1517 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1496 1518 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1497 1519 if (phydev->speed == SPEED_10) 1498 - upsmr |= UPSMR_R10M; 1520 + upsmr |= UCC_GETH_UPSMR_R10M; 1499 1521 else 1500 - upsmr &= ~(UPSMR_R10M); 1522 + upsmr &= ~UCC_GETH_UPSMR_R10M; 1501 1523 } 1502 1524 break; 1503 1525 default: ··· 1580 1602 uccf = ugeth->uccf; 1581 1603 1582 1604 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1583 - temp = in_be32(uccf->p_uccm); 1584 - temp &= ~UCCE_GRA; 1585 - out_be32(uccf->p_uccm, temp); 1586 - out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */ 1605 + clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1606 + out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1587 1607 1588 1608 /* Issue host command */ 1589 1609 cecr_subblock = ··· 1593 1617 do { 1594 1618 msleep(10); 1595 1619 temp = in_be32(uccf->p_ucce); 1596 - } while (!(temp & UCCE_GRA) && --i); 1620 + } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1597 1621 1598 1622 uccf->stopped_tx = 1; 1599 1623 ··· 1951 1975 uf_regs = ugeth->uccf->uf_regs; 1952 1976 1953 1977 if (dev->flags & IFF_PROMISC) { 1954 - 1955 - out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr) | UPSMR_PRO); 1956 - 1978 + setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 1957 1979 } else { 1958 - 1959 - out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr)&~UPSMR_PRO); 1980 + clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 1960 1981 1961 1982 p_82xx_addr_filt = 1962 1983 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> ··· 1993 2020 { 1994 2021 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 1995 2022 struct phy_device *phydev = ugeth->phydev; 1996 - u32 tempval; 1997 2023 1998 2024 ugeth_vdbg("%s: IN", __func__); 1999 2025 ··· 2009 2037 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2010 2038 2011 2039 /* Disable Rx and Tx */ 2012 - tempval = in_be32(&ug_regs->maccfg1); 2013 - tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2014 - out_be32(&ug_regs->maccfg1, tempval); 2040 + clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2015 2041 2016 2042 ucc_geth_memclean(ugeth); 2017 2043 } ··· 2123 2153 /* Generate uccm_mask for receive */ 2124 2154 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2125 2155 for (i = 0; i < ug_info->numQueuesRx; i++) 2126 - uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i); 2156 + uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2127 2157 2128 2158 for (i = 0; i < ug_info->numQueuesTx; i++) 2129 - uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i); 2159 + uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2130 2160 /* Initialize the general fast UCC block. */ 2131 2161 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2132 2162 if (netif_msg_probe(ugeth)) ··· 2155 2185 struct ucc_geth __iomem *ug_regs; 2156 2186 int ret_val = -EINVAL; 2157 2187 u32 remoder = UCC_GETH_REMODER_INIT; 2158 - u32 init_enet_pram_offset, cecr_subblock, command, maccfg1; 2188 + u32 init_enet_pram_offset, cecr_subblock, command; 2159 2189 u32 ifstat, i, j, size, l2qt, l3qt, length; 2160 2190 u16 temoder = UCC_GETH_TEMODER_INIT; 2161 2191 u16 test; ··· 2251 2281 &uf_regs->upsmr, 2252 2282 &ug_regs->uempr, &ug_regs->maccfg1); 2253 2283 2254 - maccfg1 = in_be32(&ug_regs->maccfg1); 2255 - maccfg1 |= MACCFG1_ENABLE_RX; 2256 - maccfg1 |= MACCFG1_ENABLE_TX; 2257 - out_be32(&ug_regs->maccfg1, maccfg1); 2284 + setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2258 2285 2259 2286 /* Set IPGIFG */ 2260 2287 /* For more details see the hardware spec. */ ··· 3241 3274 static int ucc_geth_poll(struct napi_struct *napi, int budget) 3242 3275 { 3243 3276 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3244 - struct net_device *dev = ugeth->dev; 3245 3277 struct ucc_geth_info *ug_info; 3246 3278 int howmany, i; 3247 3279 ··· 3251 3285 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3252 3286 3253 3287 if (howmany < budget) { 3254 - struct ucc_fast_private *uccf; 3255 - u32 uccm; 3256 - 3257 3288 netif_rx_complete(napi); 3258 - uccf = ugeth->uccf; 3259 - uccm = in_be32(uccf->p_uccm); 3260 - uccm |= UCCE_RX_EVENTS; 3261 - out_be32(uccf->p_uccm, uccm); 3289 + setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS); 3262 3290 } 3263 3291 3264 3292 return howmany; ··· 3292 3332 /* Tx event processing */ 3293 3333 if (ucce & UCCE_TX_EVENTS) { 3294 3334 spin_lock(&ugeth->lock); 3295 - tx_mask = UCCE_TXBF_SINGLE_MASK; 3335 + tx_mask = UCC_GETH_UCCE_TXB0; 3296 3336 for (i = 0; i < ug_info->numQueuesTx; i++) { 3297 3337 if (ucce & tx_mask) 3298 3338 ucc_geth_tx(dev, i); ··· 3304 3344 3305 3345 /* Errors and other events */ 3306 3346 if (ucce & UCCE_OTHER) { 3307 - if (ucce & UCCE_BSY) { 3347 + if (ucce & UCC_GETH_UCCE_BSY) 3308 3348 dev->stats.rx_errors++; 3309 - } 3310 - if (ucce & UCCE_TXE) { 3349 + if (ucce & UCC_GETH_UCCE_TXE) 3311 3350 dev->stats.tx_errors++; 3312 - } 3313 3351 } 3314 3352 3315 3353 return IRQ_HANDLED;
+21 -85
drivers/net/ucc_geth.h
··· 162 162 boundary */ 163 163 164 164 /* UCC GETH Event Register */ 165 - #define UCCE_MPD 0x80000000 /* Magic packet 166 - detection */ 167 - #define UCCE_SCAR 0x40000000 168 - #define UCCE_GRA 0x20000000 /* Tx graceful 169 - stop 170 - complete */ 171 - #define UCCE_CBPR 0x10000000 172 - #define UCCE_BSY 0x08000000 173 - #define UCCE_RXC 0x04000000 174 - #define UCCE_TXC 0x02000000 175 - #define UCCE_TXE 0x01000000 176 - #define UCCE_TXB7 0x00800000 177 - #define UCCE_TXB6 0x00400000 178 - #define UCCE_TXB5 0x00200000 179 - #define UCCE_TXB4 0x00100000 180 - #define UCCE_TXB3 0x00080000 181 - #define UCCE_TXB2 0x00040000 182 - #define UCCE_TXB1 0x00020000 183 - #define UCCE_TXB0 0x00010000 184 - #define UCCE_RXB7 0x00008000 185 - #define UCCE_RXB6 0x00004000 186 - #define UCCE_RXB5 0x00002000 187 - #define UCCE_RXB4 0x00001000 188 - #define UCCE_RXB3 0x00000800 189 - #define UCCE_RXB2 0x00000400 190 - #define UCCE_RXB1 0x00000200 191 - #define UCCE_RXB0 0x00000100 192 - #define UCCE_RXF7 0x00000080 193 - #define UCCE_RXF6 0x00000040 194 - #define UCCE_RXF5 0x00000020 195 - #define UCCE_RXF4 0x00000010 196 - #define UCCE_RXF3 0x00000008 197 - #define UCCE_RXF2 0x00000004 198 - #define UCCE_RXF1 0x00000002 199 - #define UCCE_RXF0 0x00000001 165 + #define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \ 166 + UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \ 167 + UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \ 168 + UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0) 200 169 201 - #define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0) 202 - #define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0) 170 + #define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \ 171 + UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \ 172 + UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \ 173 + UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0) 203 174 204 - #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\ 205 - UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) 206 - #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\ 207 - UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) 208 - #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\ 209 - UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) 210 - #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\ 211 - UCCE_RXC | UCCE_TXC | UCCE_TXE) 175 + #define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \ 176 + UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \ 177 + UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \ 178 + UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0) 212 179 213 - #define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY) 214 - #define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE) 180 + #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \ 181 + UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \ 182 + UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE) 215 183 216 - /* UCC GETH UPSMR (Protocol Specific Mode Register) */ 217 - #define UPSMR_ECM 0x04000000 /* Enable CAM 218 - Miss or 219 - Enable 220 - Filtering 221 - Miss */ 222 - #define UPSMR_HSE 0x02000000 /* Hardware 223 - Statistics 224 - Enable */ 225 - #define UPSMR_PRO 0x00400000 /* Promiscuous*/ 226 - #define UPSMR_CAP 0x00200000 /* CAM polarity 227 - */ 228 - #define UPSMR_RSH 0x00100000 /* Receive 229 - Short Frames 230 - */ 231 - #define UPSMR_RPM 0x00080000 /* Reduced Pin 232 - Mode 233 - interfaces */ 234 - #define UPSMR_R10M 0x00040000 /* RGMII/RMII 235 - 10 Mode */ 236 - #define UPSMR_RLPB 0x00020000 /* RMII 237 - Loopback 238 - Mode */ 239 - #define UPSMR_TBIM 0x00010000 /* Ten-bit 240 - Interface 241 - Mode */ 242 - #define UPSMR_RMM 0x00001000 /* RMII/RGMII 243 - Mode */ 244 - #define UPSMR_CAM 0x00000400 /* CAM Address 245 - Matching */ 246 - #define UPSMR_BRO 0x00000200 /* Broadcast 247 - Address */ 248 - #define UPSMR_RES1 0x00002000 /* Reserved 249 - feild - must 250 - be 1 */ 184 + #define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY) 185 + #define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE) 251 186 252 187 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ 253 188 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control ··· 880 945 #define UCC_GETH_REMODER_INIT 0 /* bits that must be 881 946 set */ 882 947 #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ 883 - #define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value 884 - for this 885 - register */ 948 + 949 + /* Initial value for UPSMR */ 950 + #define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1 951 + 886 952 #define UCC_GETH_MACCFG1_INIT 0 887 953 #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) 888 954