Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: clock: document 8ULP's SIM LPAV

Add documentation for i.MX8ULP's SIM LPAV module.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Link: https://lore.kernel.org/r/20251104120301.913-3-laurentiumihalcea111@gmail.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

authored by

Laurentiu Mihalcea and committed by
Abel Vesa
3b521bf8 9d97a2fe

+93
+72
Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NXP i.MX8ULP LPAV System Integration Module (SIM) 8 + 9 + maintainers: 10 + - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> 11 + 12 + description: 13 + The i.MX8ULP LPAV subsystem contains a block control module known as 14 + SIM LPAV, which offers functionalities such as clock gating or reset 15 + line assertion/de-assertion. 16 + 17 + properties: 18 + compatible: 19 + const: fsl,imx8ulp-sim-lpav 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + clocks: 25 + maxItems: 3 26 + 27 + clock-names: 28 + items: 29 + - const: bus 30 + - const: core 31 + - const: plat 32 + 33 + '#clock-cells': 34 + const: 1 35 + 36 + '#reset-cells': 37 + const: 1 38 + 39 + mux-controller: 40 + $ref: /schemas/mux/reg-mux.yaml# 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - clocks 46 + - clock-names 47 + - '#clock-cells' 48 + - '#reset-cells' 49 + - mux-controller 50 + 51 + additionalProperties: false 52 + 53 + examples: 54 + - | 55 + #include <dt-bindings/clock/imx8ulp-clock.h> 56 + 57 + clock-controller@2da50000 { 58 + compatible = "fsl,imx8ulp-sim-lpav"; 59 + reg = <0x2da50000 0x10000>; 60 + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, 61 + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, 62 + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; 63 + clock-names = "bus", "core", "plat"; 64 + #clock-cells = <1>; 65 + #reset-cells = <1>; 66 + 67 + mux-controller { 68 + compatible = "reg-mux"; 69 + #mux-control-cells = <1>; 70 + mux-reg-masks = <0x8 0x00000200>; 71 + }; 72 + };
+5
include/dt-bindings/clock/imx8ulp-clock.h
··· 255 255 256 256 #define IMX8ULP_CLK_PCC5_END 56 257 257 258 + /* LPAV SIM */ 259 + #define IMX8ULP_CLK_SIM_LPAV_HIFI_CORE 0 260 + #define IMX8ULP_CLK_SIM_LPAV_HIFI_PBCLK 1 261 + #define IMX8ULP_CLK_SIM_LPAV_HIFI_PLAT 2 262 + 258 263 #endif
+16
include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright 2025 NXP 4 + */ 5 + 6 + #ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H 7 + #define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H 8 + 9 + #define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST 0 10 + #define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST 1 11 + #define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL 2 12 + #define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N 3 13 + #define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N 4 14 + #define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N 5 15 + 16 + #endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */