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ARM: dts: imx6ul-kontron-n6310-s: Move common nodes to a separate file

The baseboard for the Kontron N6310 SoM is also used for other SoMs
such as N6311 and N6411. In order to share the code, we move the
definitions of the baseboard to a separate dtsi file.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Frieder Schrempf and committed by
Shawn Guo 3b5212cc 0ccafdf3

+411 -400
+1 -400
arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
··· 8 8 /dts-v1/; 9 9 10 10 #include "imx6ul-kontron-n6310-som.dtsi" 11 + #include "imx6ul-kontron-n6x1x-s.dtsi" 11 12 12 13 / { 13 14 model = "Kontron N6310 S"; 14 15 compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som", 15 16 "fsl,imx6ul"; 16 - 17 - gpio-leds { 18 - compatible = "gpio-leds"; 19 - pinctrl-names = "default"; 20 - pinctrl-0 = <&pinctrl_gpio_leds>; 21 - 22 - led1 { 23 - label = "debug-led1"; 24 - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 25 - default-state = "off"; 26 - linux,default-trigger = "heartbeat"; 27 - }; 28 - 29 - led2 { 30 - label = "debug-led2"; 31 - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; 32 - default-state = "off"; 33 - }; 34 - 35 - led3 { 36 - label = "debug-led3"; 37 - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 38 - default-state = "off"; 39 - }; 40 - }; 41 - 42 - pwm-beeper { 43 - compatible = "pwm-beeper"; 44 - pwms = <&pwm8 0 5000>; 45 - }; 46 - 47 - reg_3v3: regulator-3v3 { 48 - compatible = "regulator-fixed"; 49 - regulator-name = "3v3"; 50 - regulator-min-microvolt = <3300000>; 51 - regulator-max-microvolt = <3300000>; 52 - }; 53 - 54 - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 55 - compatible = "regulator-fixed"; 56 - regulator-name = "usb_otg1_vbus"; 57 - regulator-min-microvolt = <5000000>; 58 - regulator-max-microvolt = <5000000>; 59 - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 60 - enable-active-high; 61 - }; 62 - 63 - reg_vref_adc: regulator-vref-adc { 64 - compatible = "regulator-fixed"; 65 - regulator-name = "vref-adc"; 66 - regulator-min-microvolt = <3300000>; 67 - regulator-max-microvolt = <3300000>; 68 - }; 69 - }; 70 - 71 - &adc1 { 72 - pinctrl-names = "default"; 73 - pinctrl-0 = <&pinctrl_adc1>; 74 - num-channels = <3>; 75 - vref-supply = <&reg_vref_adc>; 76 - status = "okay"; 77 - }; 78 - 79 - &can2 { 80 - pinctrl-names = "default"; 81 - pinctrl-0 = <&pinctrl_flexcan2>; 82 - status = "okay"; 83 - }; 84 - 85 - &ecspi1 { 86 - cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 87 - pinctrl-names = "default"; 88 - pinctrl-0 = <&pinctrl_ecspi1>; 89 - status = "okay"; 90 - 91 - eeprom@0 { 92 - compatible = "anvo,anv32e61w", "atmel,at25"; 93 - reg = <0>; 94 - spi-max-frequency = <20000000>; 95 - spi-cpha; 96 - spi-cpol; 97 - pagesize = <1>; 98 - size = <8192>; 99 - address-width = <16>; 100 - }; 101 - }; 102 - 103 - &fec1 { 104 - pinctrl-0 = <&pinctrl_enet1>; 105 - /delete-node/ mdio; 106 - }; 107 - 108 - &fec2 { 109 - pinctrl-names = "default"; 110 - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; 111 - phy-mode = "rmii"; 112 - phy-handle = <&ethphy2>; 113 - status = "okay"; 114 - 115 - mdio { 116 - #address-cells = <1>; 117 - #size-cells = <0>; 118 - 119 - ethphy1: ethernet-phy@1 { 120 - reg = <1>; 121 - micrel,led-mode = <0>; 122 - clocks = <&clks IMX6UL_CLK_ENET_REF>; 123 - clock-names = "rmii-ref"; 124 - }; 125 - 126 - ethphy2: ethernet-phy@2 { 127 - reg = <2>; 128 - micrel,led-mode = <0>; 129 - clocks = <&clks IMX6UL_CLK_ENET2_REF>; 130 - clock-names = "rmii-ref"; 131 - }; 132 - }; 133 - }; 134 - 135 - &i2c1 { 136 - clock-frequency = <100000>; 137 - pinctrl-names = "default"; 138 - pinctrl-0 = <&pinctrl_i2c1>; 139 - status = "okay"; 140 - }; 141 - 142 - &i2c4 { 143 - clock-frequency = <100000>; 144 - pinctrl-names = "default"; 145 - pinctrl-0 = <&pinctrl_i2c4>; 146 - status = "okay"; 147 - 148 - rtc@32 { 149 - compatible = "epson,rx8900"; 150 - reg = <0x32>; 151 - }; 152 - }; 153 - 154 - &pwm8 { 155 - pinctrl-names = "default"; 156 - pinctrl-0 = <&pinctrl_pwm8>; 157 - status = "okay"; 158 - }; 159 - 160 - &uart1 { 161 - pinctrl-names = "default"; 162 - pinctrl-0 = <&pinctrl_uart1>; 163 - status = "okay"; 164 - }; 165 - 166 - &uart2 { 167 - pinctrl-names = "default"; 168 - pinctrl-0 = <&pinctrl_uart2>; 169 - linux,rs485-enabled-at-boot-time; 170 - rs485-rx-during-tx; 171 - rs485-rts-active-low; 172 - uart-has-rtscts; 173 - status = "okay"; 174 - }; 175 - 176 - &uart3 { 177 - pinctrl-names = "default"; 178 - pinctrl-0 = <&pinctrl_uart3>; 179 - fsl,uart-has-rtscts; 180 - status = "okay"; 181 - }; 182 - 183 - &uart4 { 184 - pinctrl-names = "default"; 185 - pinctrl-0 = <&pinctrl_uart4>; 186 - status = "okay"; 187 - }; 188 - 189 - &usbotg1 { 190 - pinctrl-names = "default"; 191 - pinctrl-0 = <&pinctrl_usbotg1>; 192 - dr_mode = "otg"; 193 - srp-disable; 194 - hnp-disable; 195 - adp-disable; 196 - vbus-supply = <&reg_usb_otg1_vbus>; 197 - status = "okay"; 198 - }; 199 - 200 - &usbotg2 { 201 - dr_mode = "host"; 202 - disable-over-current; 203 - status = "okay"; 204 - }; 205 - 206 - &usdhc1 { 207 - pinctrl-names = "default"; 208 - pinctrl-0 = <&pinctrl_usdhc1>; 209 - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 210 - keep-power-in-suspend; 211 - wakeup-source; 212 - vmmc-supply = <&reg_3v3>; 213 - voltage-ranges = <3300 3300>; 214 - no-1-8-v; 215 - status = "okay"; 216 - }; 217 - 218 - &usdhc2 { 219 - pinctrl-names = "default", "state_100mhz", "state_200mhz"; 220 - pinctrl-0 = <&pinctrl_usdhc2>; 221 - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 222 - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 223 - non-removable; 224 - keep-power-in-suspend; 225 - wakeup-source; 226 - vmmc-supply = <&reg_3v3>; 227 - voltage-ranges = <3300 3300>; 228 - no-1-8-v; 229 - status = "okay"; 230 - }; 231 - 232 - &wdog1 { 233 - pinctrl-names = "default"; 234 - pinctrl-0 = <&pinctrl_wdog>; 235 - fsl,ext-reset-output; 236 - status = "okay"; 237 - }; 238 - 239 - &iomuxc { 240 - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; 241 - 242 - pinctrl_adc1: adc1grp { 243 - fsl,pins = < 244 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 245 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 246 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 247 - >; 248 - }; 249 - 250 - /* FRAM */ 251 - pinctrl_ecspi1: ecspi1grp { 252 - fsl,pins = < 253 - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 254 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 255 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 256 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ 257 - >; 258 - }; 259 - 260 - pinctrl_enet2: enet2grp { 261 - fsl,pins = < 262 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 263 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 264 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 265 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 266 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 267 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 268 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 269 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 270 - >; 271 - }; 272 - 273 - pinctrl_enet2_mdio: enet2mdiogrp { 274 - fsl,pins = < 275 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 276 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 277 - >; 278 - }; 279 - 280 - pinctrl_flexcan2: flexcan2grp{ 281 - fsl,pins = < 282 - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 283 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 284 - >; 285 - }; 286 - 287 - pinctrl_gpio: gpiogrp { 288 - fsl,pins = < 289 - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ 290 - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ 291 - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ 292 - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ 293 - >; 294 - }; 295 - 296 - pinctrl_gpio_leds: gpioledsgrp { 297 - fsl,pins = < 298 - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ 299 - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ 300 - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ 301 - >; 302 - }; 303 - 304 - pinctrl_i2c1: i2c1grp { 305 - fsl,pins = < 306 - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 307 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 308 - >; 309 - }; 310 - 311 - pinctrl_i2c4: i2c4grp { 312 - fsl,pins = < 313 - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 314 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 315 - >; 316 - }; 317 - 318 - pinctrl_pwm8: pwm8grp { 319 - fsl,pins = < 320 - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 321 - >; 322 - }; 323 - 324 - pinctrl_uart1: uart1grp { 325 - fsl,pins = < 326 - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 327 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 328 - >; 329 - }; 330 - 331 - pinctrl_uart2: uart2grp { 332 - fsl,pins = < 333 - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 334 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 335 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 336 - /* 337 - * mux unused RTS to make sure it doesn't cause 338 - * any interrupts when it is undefined 339 - */ 340 - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 341 - >; 342 - }; 343 - 344 - pinctrl_uart3: uart3grp { 345 - fsl,pins = < 346 - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 347 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 348 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 349 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 350 - >; 351 - }; 352 - 353 - pinctrl_uart4: uart4grp { 354 - fsl,pins = < 355 - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 356 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 357 - >; 358 - }; 359 - 360 - pinctrl_usbotg1: usbotg1 { 361 - fsl,pins = < 362 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 363 - >; 364 - }; 365 - 366 - pinctrl_usdhc1: usdhc1grp { 367 - fsl,pins = < 368 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 369 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 370 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 371 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 372 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 373 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 374 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ 375 - >; 376 - }; 377 - 378 - pinctrl_usdhc2: usdhc2grp { 379 - fsl,pins = < 380 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 381 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 382 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 383 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 384 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 385 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 386 - >; 387 - }; 388 - 389 - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 390 - fsl,pins = < 391 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 392 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 393 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 394 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 395 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 396 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 397 - >; 398 - }; 399 - 400 - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 401 - fsl,pins = < 402 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 403 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 404 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 405 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 406 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 407 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 408 - >; 409 - }; 410 - 411 - pinctrl_wdog: wdoggrp { 412 - fsl,pins = < 413 - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 414 - >; 415 - }; 416 17 };
+410
arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2017 exceet electronics GmbH 4 + * Copyright (C) 2018 Kontron Electronics GmbH 5 + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> 6 + */ 7 + 8 + #include <dt-bindings/gpio/gpio.h> 9 + 10 + / { 11 + gpio-leds { 12 + compatible = "gpio-leds"; 13 + pinctrl-names = "default"; 14 + pinctrl-0 = <&pinctrl_gpio_leds>; 15 + 16 + led1 { 17 + label = "debug-led1"; 18 + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 19 + default-state = "off"; 20 + linux,default-trigger = "heartbeat"; 21 + }; 22 + 23 + led2 { 24 + label = "debug-led2"; 25 + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; 26 + default-state = "off"; 27 + }; 28 + 29 + led3 { 30 + label = "debug-led3"; 31 + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 32 + default-state = "off"; 33 + }; 34 + }; 35 + 36 + pwm-beeper { 37 + compatible = "pwm-beeper"; 38 + pwms = <&pwm8 0 5000>; 39 + }; 40 + 41 + reg_3v3: regulator-3v3 { 42 + compatible = "regulator-fixed"; 43 + regulator-name = "3v3"; 44 + regulator-min-microvolt = <3300000>; 45 + regulator-max-microvolt = <3300000>; 46 + }; 47 + 48 + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 49 + compatible = "regulator-fixed"; 50 + regulator-name = "usb_otg1_vbus"; 51 + regulator-min-microvolt = <5000000>; 52 + regulator-max-microvolt = <5000000>; 53 + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 54 + enable-active-high; 55 + }; 56 + 57 + reg_vref_adc: regulator-vref-adc { 58 + compatible = "regulator-fixed"; 59 + regulator-name = "vref-adc"; 60 + regulator-min-microvolt = <3300000>; 61 + regulator-max-microvolt = <3300000>; 62 + }; 63 + }; 64 + 65 + &adc1 { 66 + pinctrl-names = "default"; 67 + pinctrl-0 = <&pinctrl_adc1>; 68 + num-channels = <3>; 69 + vref-supply = <&reg_vref_adc>; 70 + status = "okay"; 71 + }; 72 + 73 + &can2 { 74 + pinctrl-names = "default"; 75 + pinctrl-0 = <&pinctrl_flexcan2>; 76 + status = "okay"; 77 + }; 78 + 79 + &ecspi1 { 80 + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 81 + pinctrl-names = "default"; 82 + pinctrl-0 = <&pinctrl_ecspi1>; 83 + status = "okay"; 84 + 85 + eeprom@0 { 86 + compatible = "anvo,anv32e61w", "atmel,at25"; 87 + reg = <0>; 88 + spi-max-frequency = <20000000>; 89 + spi-cpha; 90 + spi-cpol; 91 + pagesize = <1>; 92 + size = <8192>; 93 + address-width = <16>; 94 + }; 95 + }; 96 + 97 + &fec1 { 98 + pinctrl-0 = <&pinctrl_enet1>; 99 + /delete-node/ mdio; 100 + }; 101 + 102 + &fec2 { 103 + pinctrl-names = "default"; 104 + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; 105 + phy-mode = "rmii"; 106 + phy-handle = <&ethphy2>; 107 + status = "okay"; 108 + 109 + mdio { 110 + #address-cells = <1>; 111 + #size-cells = <0>; 112 + 113 + ethphy1: ethernet-phy@1 { 114 + reg = <1>; 115 + micrel,led-mode = <0>; 116 + clocks = <&clks IMX6UL_CLK_ENET_REF>; 117 + clock-names = "rmii-ref"; 118 + }; 119 + 120 + ethphy2: ethernet-phy@2 { 121 + reg = <2>; 122 + micrel,led-mode = <0>; 123 + clocks = <&clks IMX6UL_CLK_ENET2_REF>; 124 + clock-names = "rmii-ref"; 125 + }; 126 + }; 127 + }; 128 + 129 + &i2c1 { 130 + clock-frequency = <100000>; 131 + pinctrl-names = "default"; 132 + pinctrl-0 = <&pinctrl_i2c1>; 133 + status = "okay"; 134 + }; 135 + 136 + &i2c4 { 137 + clock-frequency = <100000>; 138 + pinctrl-names = "default"; 139 + pinctrl-0 = <&pinctrl_i2c4>; 140 + status = "okay"; 141 + 142 + rtc@32 { 143 + compatible = "epson,rx8900"; 144 + reg = <0x32>; 145 + }; 146 + }; 147 + 148 + &pwm8 { 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&pinctrl_pwm8>; 151 + status = "okay"; 152 + }; 153 + 154 + &uart1 { 155 + pinctrl-names = "default"; 156 + pinctrl-0 = <&pinctrl_uart1>; 157 + status = "okay"; 158 + }; 159 + 160 + &uart2 { 161 + pinctrl-names = "default"; 162 + pinctrl-0 = <&pinctrl_uart2>; 163 + linux,rs485-enabled-at-boot-time; 164 + rs485-rx-during-tx; 165 + rs485-rts-active-low; 166 + uart-has-rtscts; 167 + status = "okay"; 168 + }; 169 + 170 + &uart3 { 171 + pinctrl-names = "default"; 172 + pinctrl-0 = <&pinctrl_uart3>; 173 + fsl,uart-has-rtscts; 174 + status = "okay"; 175 + }; 176 + 177 + &uart4 { 178 + pinctrl-names = "default"; 179 + pinctrl-0 = <&pinctrl_uart4>; 180 + status = "okay"; 181 + }; 182 + 183 + &usbotg1 { 184 + pinctrl-names = "default"; 185 + pinctrl-0 = <&pinctrl_usbotg1>; 186 + dr_mode = "otg"; 187 + srp-disable; 188 + hnp-disable; 189 + adp-disable; 190 + vbus-supply = <&reg_usb_otg1_vbus>; 191 + status = "okay"; 192 + }; 193 + 194 + &usbotg2 { 195 + dr_mode = "host"; 196 + disable-over-current; 197 + status = "okay"; 198 + }; 199 + 200 + &usdhc1 { 201 + pinctrl-names = "default"; 202 + pinctrl-0 = <&pinctrl_usdhc1>; 203 + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 204 + keep-power-in-suspend; 205 + wakeup-source; 206 + vmmc-supply = <&reg_3v3>; 207 + voltage-ranges = <3300 3300>; 208 + no-1-8-v; 209 + status = "okay"; 210 + }; 211 + 212 + &usdhc2 { 213 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 214 + pinctrl-0 = <&pinctrl_usdhc2>; 215 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 216 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 217 + non-removable; 218 + keep-power-in-suspend; 219 + wakeup-source; 220 + vmmc-supply = <&reg_3v3>; 221 + voltage-ranges = <3300 3300>; 222 + no-1-8-v; 223 + status = "okay"; 224 + }; 225 + 226 + &wdog1 { 227 + pinctrl-names = "default"; 228 + pinctrl-0 = <&pinctrl_wdog>; 229 + fsl,ext-reset-output; 230 + status = "okay"; 231 + }; 232 + 233 + &iomuxc { 234 + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; 235 + 236 + pinctrl_adc1: adc1grp { 237 + fsl,pins = < 238 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 239 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 240 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 241 + >; 242 + }; 243 + 244 + /* FRAM */ 245 + pinctrl_ecspi1: ecspi1grp { 246 + fsl,pins = < 247 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 248 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 249 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 250 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ 251 + >; 252 + }; 253 + 254 + pinctrl_enet2: enet2grp { 255 + fsl,pins = < 256 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 257 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 258 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 259 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 260 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 261 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 262 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 263 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 264 + >; 265 + }; 266 + 267 + pinctrl_enet2_mdio: enet2mdiogrp { 268 + fsl,pins = < 269 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 270 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 271 + >; 272 + }; 273 + 274 + pinctrl_flexcan2: flexcan2grp{ 275 + fsl,pins = < 276 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 277 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 278 + >; 279 + }; 280 + 281 + pinctrl_gpio: gpiogrp { 282 + fsl,pins = < 283 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ 284 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ 285 + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ 286 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ 287 + >; 288 + }; 289 + 290 + pinctrl_gpio_leds: gpioledsgrp { 291 + fsl,pins = < 292 + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ 293 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ 294 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ 295 + >; 296 + }; 297 + 298 + pinctrl_i2c1: i2c1grp { 299 + fsl,pins = < 300 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 301 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 302 + >; 303 + }; 304 + 305 + pinctrl_i2c4: i2c4grp { 306 + fsl,pins = < 307 + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 308 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 309 + >; 310 + }; 311 + 312 + pinctrl_pwm8: pwm8grp { 313 + fsl,pins = < 314 + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 315 + >; 316 + }; 317 + 318 + pinctrl_uart1: uart1grp { 319 + fsl,pins = < 320 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 321 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 322 + >; 323 + }; 324 + 325 + pinctrl_uart2: uart2grp { 326 + fsl,pins = < 327 + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 328 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 329 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 330 + /* 331 + * mux unused RTS to make sure it doesn't cause 332 + * any interrupts when it is undefined 333 + */ 334 + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 335 + >; 336 + }; 337 + 338 + pinctrl_uart3: uart3grp { 339 + fsl,pins = < 340 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 341 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 342 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 343 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 344 + >; 345 + }; 346 + 347 + pinctrl_uart4: uart4grp { 348 + fsl,pins = < 349 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 350 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 351 + >; 352 + }; 353 + 354 + pinctrl_usbotg1: usbotg1 { 355 + fsl,pins = < 356 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 357 + >; 358 + }; 359 + 360 + pinctrl_usdhc1: usdhc1grp { 361 + fsl,pins = < 362 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 363 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 364 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 365 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 366 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 367 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 368 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ 369 + >; 370 + }; 371 + 372 + pinctrl_usdhc2: usdhc2grp { 373 + fsl,pins = < 374 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 375 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 376 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 377 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 378 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 379 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 380 + >; 381 + }; 382 + 383 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 384 + fsl,pins = < 385 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 386 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 387 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 388 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 389 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 390 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 391 + >; 392 + }; 393 + 394 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 395 + fsl,pins = < 396 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 397 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 398 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 399 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 400 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 401 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 402 + >; 403 + }; 404 + 405 + pinctrl_wdog: wdoggrp { 406 + fsl,pins = < 407 + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 408 + >; 409 + }; 410 + };