Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

serial: sh-sci: Add support for RZ/G2L SoC

Add serial support for RZ/G2L SoC with earlycon and
extended mode register support.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Biju Das and committed by
Greg Kroah-Hartman
3b2cd606 d157fca7

+12 -1
+11 -1
drivers/tty/serial/sh-sci.c
··· 289 289 }, 290 290 291 291 /* 292 - * The "SCIFA" that is in RZ/T and RZ/A2. 292 + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 293 293 * It looks like a normal SCIF with FIFO data, but with a 294 294 * compressed address space. Also, the break out of interrupts 295 295 * are different: ERI/BRI, RXI, TXI, TEI, DRI. ··· 306 306 [SCFDR] = { 0x0E, 16 }, 307 307 [SCSPTR] = { 0x10, 16 }, 308 308 [SCLSR] = { 0x12, 16 }, 309 + [SEMR] = { 0x14, 8 }, 309 310 }, 310 311 .fifosize = 16, 311 312 .overrun_reg = SCLSR, ··· 2515 2514 if (termios->c_cflag & PARENB) 2516 2515 bits++; 2517 2516 2517 + if (sci_getreg(port, SEMR)->size) 2518 + serial_port_out(port, SEMR, 0); 2519 + 2518 2520 if (best_clk >= 0) { 2519 2521 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2520 2522 switch (srr + 1) { ··· 3174 3170 .compatible = "renesas,scif-r7s9210", 3175 3171 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3176 3172 }, 3173 + { 3174 + .compatible = "renesas,scif-r9a07g044", 3175 + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3176 + }, 3177 3177 /* Family-specific types */ 3178 3178 { 3179 3179 .compatible = "renesas,rcar-gen1-scif", ··· 3460 3452 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3461 3453 return early_console_setup(device, PORT_SCIF); 3462 3454 } 3455 + 3463 3456 static int __init scifa_early_console_setup(struct earlycon_device *device, 3464 3457 const char *opt) 3465 3458 { ··· 3480 3471 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3481 3472 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3482 3473 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3474 + OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3483 3475 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3484 3476 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3485 3477 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
+1
drivers/tty/serial/sh-sci.h
··· 31 31 SCCKS, /* BRG Clock Select Register */ 32 32 HSRTRGR, /* Rx FIFO Data Count Trigger Register */ 33 33 HSTTRGR, /* Tx FIFO Data Count Trigger Register */ 34 + SEMR, /* Serial extended mode register */ 34 35 35 36 SCIx_NR_REGS, 36 37 };