Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: mtd: Split ECC engine with rawnand controller

Split MediaTek ECC engine with rawnand controller and convert to
YAML schema.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230201021500.26769-2-xiangsheng.hou@mediatek.com

authored by

Xiangsheng Hou and committed by
Miquel Raynal
3af7ade2 b5626525

+218 -177
+155
Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) 8 + 9 + maintainers: 10 + - Xiangsheng Hou <xiangsheng.hou@mediatek.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - mediatek,mt2701-nfc 16 + - mediatek,mt2712-nfc 17 + - mediatek,mt7622-nfc 18 + 19 + reg: 20 + items: 21 + - description: Base physical address and size of NFI. 22 + 23 + interrupts: 24 + items: 25 + - description: NFI interrupt 26 + 27 + clocks: 28 + items: 29 + - description: clock used for the controller 30 + - description: clock used for the pad 31 + 32 + clock-names: 33 + items: 34 + - const: nfi_clk 35 + - const: pad_clk 36 + 37 + ecc-engine: 38 + description: device-tree node of the required ECC engine. 39 + $ref: /schemas/types.yaml#/definitions/phandle 40 + 41 + patternProperties: 42 + "^nand@[a-f0-9]$": 43 + $ref: nand-chip.yaml# 44 + unevaluatedProperties: false 45 + properties: 46 + reg: 47 + maximum: 1 48 + nand-on-flash-bbt: true 49 + nand-ecc-mode: 50 + const: hw 51 + 52 + allOf: 53 + - $ref: nand-controller.yaml# 54 + 55 + - if: 56 + properties: 57 + compatible: 58 + contains: 59 + const: mediatek,mt2701-nfc 60 + then: 61 + patternProperties: 62 + "^nand@[a-f0-9]$": 63 + properties: 64 + nand-ecc-step-size: 65 + enum: [ 512, 1024 ] 66 + nand-ecc-strength: 67 + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 68 + 40, 44, 48, 52, 56, 60] 69 + 70 + - if: 71 + properties: 72 + compatible: 73 + contains: 74 + const: mediatek,mt2712-nfc 75 + then: 76 + patternProperties: 77 + "^nand@[a-f0-9]$": 78 + properties: 79 + nand-ecc-step-size: 80 + enum: [ 512, 1024 ] 81 + nand-ecc-strength: 82 + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 83 + 40, 44, 48, 52, 56, 60, 68, 72, 80] 84 + 85 + - if: 86 + properties: 87 + compatible: 88 + contains: 89 + const: mediatek,mt7622-nfc 90 + then: 91 + patternProperties: 92 + "^nand@[a-f0-9]$": 93 + properties: 94 + nand-ecc-step-size: 95 + const: 512 96 + nand-ecc-strength: 97 + enum: [4, 6, 8, 10, 12] 98 + 99 + required: 100 + - compatible 101 + - reg 102 + - interrupts 103 + - clocks 104 + - clock-names 105 + - ecc-engine 106 + 107 + unevaluatedProperties: false 108 + 109 + examples: 110 + - | 111 + #include <dt-bindings/clock/mt2701-clk.h> 112 + #include <dt-bindings/interrupt-controller/arm-gic.h> 113 + #include <dt-bindings/interrupt-controller/irq.h> 114 + 115 + soc { 116 + #address-cells = <2>; 117 + #size-cells = <2>; 118 + 119 + nand-controller@1100d000 { 120 + compatible = "mediatek,mt2701-nfc"; 121 + reg = <0 0x1100d000 0 0x1000>; 122 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; 123 + clocks = <&pericfg CLK_PERI_NFI>, 124 + <&pericfg CLK_PERI_NFI_PAD>; 125 + clock-names = "nfi_clk", "pad_clk"; 126 + ecc-engine = <&bch>; 127 + #address-cells = <1>; 128 + #size-cells = <0>; 129 + 130 + nand@0 { 131 + reg = <0>; 132 + 133 + nand-on-flash-bbt; 134 + nand-ecc-mode = "hw"; 135 + nand-ecc-step-size = <1024>; 136 + nand-ecc-strength = <24>; 137 + 138 + partitions { 139 + compatible = "fixed-partitions"; 140 + #address-cells = <1>; 141 + #size-cells = <1>; 142 + 143 + preloader@0 { 144 + label = "pl"; 145 + read-only; 146 + reg = <0x0 0x400000>; 147 + }; 148 + android@400000 { 149 + label = "android"; 150 + reg = <0x400000 0x12c00000>; 151 + }; 152 + }; 153 + }; 154 + }; 155 + };
+62
Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MediaTek(MTK) SoCs NAND ECC engine 8 + 9 + maintainers: 10 + - Xiangsheng Hou <xiangsheng.hou@mediatek.com> 11 + 12 + description: | 13 + MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. 14 + 15 + properties: 16 + compatible: 17 + enum: 18 + - mediatek,mt2701-ecc 19 + - mediatek,mt2712-ecc 20 + - mediatek,mt7622-ecc 21 + 22 + reg: 23 + items: 24 + - description: Base physical address and size of ECC. 25 + 26 + interrupts: 27 + items: 28 + - description: ECC interrupt 29 + 30 + clocks: 31 + maxItems: 1 32 + 33 + clock-names: 34 + const: nfiecc_clk 35 + 36 + required: 37 + - compatible 38 + - reg 39 + - interrupts 40 + - clocks 41 + - clock-names 42 + 43 + additionalProperties: false 44 + 45 + examples: 46 + - | 47 + #include <dt-bindings/clock/mt2701-clk.h> 48 + #include <dt-bindings/interrupt-controller/arm-gic.h> 49 + #include <dt-bindings/interrupt-controller/irq.h> 50 + 51 + soc { 52 + #address-cells = <2>; 53 + #size-cells = <2>; 54 + 55 + bch: ecc@1100e000 { 56 + compatible = "mediatek,mt2701-ecc"; 57 + reg = <0 0x1100e000 0 0x1000>; 58 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 59 + clocks = <&pericfg CLK_PERI_NFI_ECC>; 60 + clock-names = "nfiecc_clk"; 61 + }; 62 + };
-176
Documentation/devicetree/bindings/mtd/mtk-nand.txt
··· 1 - MTK SoCs NAND FLASH controller (NFC) DT binding 2 - 3 - This file documents the device tree bindings for MTK SoCs NAND controllers. 4 - The functional split of the controller requires two drivers to operate: 5 - the nand controller interface driver and the ECC engine driver. 6 - 7 - The hardware description for both devices must be captured as device 8 - tree nodes. 9 - 10 - 1) NFC NAND Controller Interface (NFI): 11 - ======================================= 12 - 13 - The first part of NFC is NAND Controller Interface (NFI) HW. 14 - Required NFI properties: 15 - - compatible: Should be one of 16 - "mediatek,mt2701-nfc", 17 - "mediatek,mt2712-nfc", 18 - "mediatek,mt7622-nfc". 19 - - reg: Base physical address and size of NFI. 20 - - interrupts: Interrupts of NFI. 21 - - clocks: NFI required clocks. 22 - - clock-names: NFI clocks internal name. 23 - - ecc-engine: Required ECC Engine node. 24 - - #address-cells: NAND chip index, should be 1. 25 - - #size-cells: Should be 0. 26 - 27 - Example: 28 - 29 - nandc: nfi@1100d000 { 30 - compatible = "mediatek,mt2701-nfc"; 31 - reg = <0 0x1100d000 0 0x1000>; 32 - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; 33 - clocks = <&pericfg CLK_PERI_NFI>, 34 - <&pericfg CLK_PERI_NFI_PAD>; 35 - clock-names = "nfi_clk", "pad_clk"; 36 - ecc-engine = <&bch>; 37 - #address-cells = <1>; 38 - #size-cells = <0>; 39 - }; 40 - 41 - Platform related properties, should be set in {platform_name}.dts: 42 - - children nodes: NAND chips. 43 - 44 - Children nodes properties: 45 - - reg: Chip Select Signal, default 0. 46 - Set as reg = <0>, <1> when need 2 CS. 47 - Optional: 48 - - nand-on-flash-bbt: Store BBT on NAND Flash. 49 - - nand-ecc-mode: the NAND ecc mode (check driver for supported modes) 50 - - nand-ecc-step-size: Number of data bytes covered by a single ECC step. 51 - valid values: 52 - 512 and 1024 on mt2701 and mt2712. 53 - 512 only on mt7622. 54 - 1024 is recommended for large page NANDs. 55 - - nand-ecc-strength: Number of bits to correct per ECC step. 56 - The valid values that each controller supports: 57 - mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 58 - 32, 36, 40, 44, 48, 52, 56, 60. 59 - mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 60 - 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. 61 - mt7622: 4, 6, 8, 10, 12, 14, 16. 62 - The strength should be calculated as follows: 63 - E = (S - F) * 8 / B 64 - S = O / (P / Q) 65 - E : nand-ecc-strength. 66 - S : spare size per sector. 67 - F : FDM size, should be in the range [1,8]. 68 - It is used to store free oob data. 69 - O : oob size. 70 - P : page size. 71 - Q : nand-ecc-step-size. 72 - B : number of parity bits needed to correct 73 - 1 bitflip. 74 - According to MTK NAND controller design, 75 - this number depends on max ecc step size 76 - that MTK NAND controller supports. 77 - If max ecc step size supported is 1024, 78 - then it should be always 14. And if max 79 - ecc step size is 512, then it should be 80 - always 13. 81 - If the result does not match any one of the listed 82 - choices above, please select the smaller valid value from 83 - the list. 84 - (otherwise the driver will do the adjustment at runtime) 85 - - pinctrl-names: Default NAND pin GPIO setting name. 86 - - pinctrl-0: GPIO setting node. 87 - 88 - Example: 89 - &pio { 90 - nand_pins_default: nanddefault { 91 - pins_dat { 92 - pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>, 93 - <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>, 94 - <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>, 95 - <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>, 96 - <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>, 97 - <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>, 98 - <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>, 99 - <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>, 100 - <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>; 101 - input-enable; 102 - drive-strength = <MTK_DRIVE_8mA>; 103 - bias-pull-up; 104 - }; 105 - 106 - pins_we { 107 - pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>; 108 - drive-strength = <MTK_DRIVE_8mA>; 109 - bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 110 - }; 111 - 112 - pins_ale { 113 - pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>; 114 - drive-strength = <MTK_DRIVE_8mA>; 115 - bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 116 - }; 117 - }; 118 - }; 119 - 120 - &nandc { 121 - status = "okay"; 122 - pinctrl-names = "default"; 123 - pinctrl-0 = <&nand_pins_default>; 124 - nand@0 { 125 - reg = <0>; 126 - nand-on-flash-bbt; 127 - nand-ecc-mode = "hw"; 128 - nand-ecc-strength = <24>; 129 - nand-ecc-step-size = <1024>; 130 - }; 131 - }; 132 - 133 - NAND chip optional subnodes: 134 - - Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml 135 - 136 - Example: 137 - nand@0 { 138 - partitions { 139 - compatible = "fixed-partitions"; 140 - #address-cells = <1>; 141 - #size-cells = <1>; 142 - 143 - preloader@0 { 144 - label = "pl"; 145 - read-only; 146 - reg = <0x00000000 0x00400000>; 147 - }; 148 - android@00400000 { 149 - label = "android"; 150 - reg = <0x00400000 0x12c00000>; 151 - }; 152 - }; 153 - }; 154 - 155 - 2) ECC Engine: 156 - ============== 157 - 158 - Required BCH properties: 159 - - compatible: Should be one of 160 - "mediatek,mt2701-ecc", 161 - "mediatek,mt2712-ecc", 162 - "mediatek,mt7622-ecc". 163 - - reg: Base physical address and size of ECC. 164 - - interrupts: Interrupts of ECC. 165 - - clocks: ECC required clocks. 166 - - clock-names: ECC clocks internal name. 167 - 168 - Example: 169 - 170 - bch: ecc@1100e000 { 171 - compatible = "mediatek,mt2701-ecc"; 172 - reg = <0 0x1100e000 0 0x1000>; 173 - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 174 - clocks = <&pericfg CLK_PERI_NFI_ECC>; 175 - clock-names = "nfiecc_clk"; 176 - };
+1 -1
MAINTAINERS
··· 13213 13213 MEDIATEK NAND CONTROLLER DRIVER 13214 13214 L: linux-mtd@lists.infradead.org 13215 13215 S: Orphan 13216 - F: Documentation/devicetree/bindings/mtd/mtk-nand.txt 13216 + F: Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml 13217 13217 F: drivers/mtd/nand/raw/mtk_* 13218 13218 13219 13219 MEDIATEK PMIC LED DRIVER