dt: Add bindings for IDT VersaClock 5P49V5925

IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.

Signed-off-by: Vladimir Barinov <[e-mail]>
Acked-by: Rob Herring <[e-mail]>
Reviewed-by: Marek Vasut <[e-mail]>
Signed-off-by: Stephen Boyd <[e-mail]>

Documentation/devicetree/bindings/clock/idt,versaclock5.txt

···
 Required properties:
 - compatible:	shall be one of
 		"idt,5p49v5923"
+		"idt,5p49v5925"
 		"idt,5p49v5933"
 		"idt,5p49v5935"
 		"idt,5p49v6901"
···
 - #clock-cells:	from common clock binding; shall be set to 1.
 - clocks:	from common clock binding; list of parent clock handles,
 		- 5p49v5923 and
+		  5p49v5925 and
 		  5p49v6901: (required) either or both of XTAL or CLKIN
 					reference clock.
 		- 5p49v5933 and
···
 					clock.
 - clock-names:	from common clock binding; clock input names, can be
 		- 5p49v5923 and
+		  5p49v5925 and
 		  5p49v6901: (required) either or both of "xin", "clkin".
 		- 5p49v5933 and
 		- 5p49v5935: (optional) property not present or "clkin".
···
 	1 -- OUT1
 	2 -- OUT4
 
+5P49V5925 and
 5P49V5935:
 	0 -- OUT0_SEL_I2CB
 	1 -- OUT1