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kernel os linux

media: cedrus: h265: Fix configuring bitstream size

bit_size field holds size of slice, not slice + header. Because of HW
quirks, driver can't program in just slice, but also preceding header.
But that means that currently used bit_size is wrong (too small).
Instead, just use size of whole buffer. There is no harm in doing this.

Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support")
Suggested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

authored by

Jernej Skrabec and committed by
Hans Verkuil
3a11887f 1b69c938

+4 -6
+4 -6
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
··· 427 427 unsigned int ctb_addr_x, ctb_addr_y; 428 428 struct cedrus_buffer *cedrus_buf; 429 429 dma_addr_t src_buf_addr; 430 - dma_addr_t src_buf_end_addr; 431 430 u32 chroma_log2_weight_denom; 432 431 u32 num_entry_point_offsets; 433 432 u32 output_pic_list_index; 434 433 u32 pic_order_cnt[2]; 434 + size_t slice_bytes; 435 435 u8 padding; 436 436 int count; 437 437 u32 reg; ··· 443 443 pred_weight_table = &slice_params->pred_weight_table; 444 444 num_entry_point_offsets = slice_params->num_entry_point_offsets; 445 445 cedrus_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); 446 + slice_bytes = vb2_get_plane_payload(&run->src->vb2_buf, 0); 446 447 447 448 /* 448 449 * If entry points offsets are present, we should get them ··· 491 490 492 491 cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0); 493 492 494 - reg = slice_params->bit_size; 493 + reg = slice_bytes * 8; 495 494 cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); 496 495 497 496 /* Source beginning and end addresses. */ ··· 505 504 506 505 cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg); 507 506 508 - src_buf_end_addr = src_buf_addr + 509 - DIV_ROUND_UP(slice_params->bit_size, 8); 510 - 511 - reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); 507 + reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_addr + slice_bytes); 512 508 cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); 513 509 514 510 /* Coding tree block address */