tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc

* 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
ARM: Consolidate the clkdev header files
ARM: set vga memory base at run-time
ARM: convert PCI defines to variables
ARM: pci: make pcibios_assign_all_busses use pci_has_flag
ARM: remove unnecessary mach/hardware.h includes
pci: move microblaze and powerpc pci flag functions into asm-generic
powerpc: rename ppc_pci_*_flags to pci_*_flags

Fix up conflicts in arch/microblaze/include/asm/pci-bridge.h

Linus Torvalds 3960ef32 62c9072b

+212 -577
+6
arch/arm/Kconfig
··· 242 242 select ARM_AMBA 243 243 select ARCH_HAS_CPUFREQ 244 244 select CLKDEV_LOOKUP 245 + select HAVE_MACH_CLKDEV 245 246 select ICST 246 247 select GENERIC_CLOCKEVENTS 247 248 select PLAT_VERSATILE ··· 254 253 bool "ARM Ltd. RealView family" 255 254 select ARM_AMBA 256 255 select CLKDEV_LOOKUP 256 + select HAVE_MACH_CLKDEV 257 257 select ICST 258 258 select GENERIC_CLOCKEVENTS 259 259 select ARCH_WANT_OPTIONAL_GPIOLIB ··· 270 268 select ARM_AMBA 271 269 select ARM_VIC 272 270 select CLKDEV_LOOKUP 271 + select HAVE_MACH_CLKDEV 273 272 select ICST 274 273 select GENERIC_CLOCKEVENTS 275 274 select ARCH_WANT_OPTIONAL_GPIOLIB ··· 287 284 select ARM_AMBA 288 285 select ARM_TIMER_SP804 289 286 select CLKDEV_LOOKUP 287 + select HAVE_MACH_CLKDEV 290 288 select GENERIC_CLOCKEVENTS 291 289 select HAVE_CLK 292 290 select HAVE_PATA_PLATFORM ··· 650 646 bool "Renesas SH-Mobile / R-Mobile" 651 647 select HAVE_CLK 652 648 select CLKDEV_LOOKUP 649 + select HAVE_MACH_CLKDEV 653 650 select GENERIC_CLOCKEVENTS 654 651 select NO_IOPORT 655 652 select SPARSE_IRQ ··· 830 825 select ARM_VIC 831 826 select GENERIC_CLOCKEVENTS 832 827 select CLKDEV_LOOKUP 828 + select HAVE_MACH_CLKDEV 833 829 select GENERIC_GPIO 834 830 help 835 831 Support for ST-Ericsson U300 series mobile platforms.
+5
arch/arm/include/asm/clkdev.h
··· 14 14 15 15 #include <linux/slab.h> 16 16 17 + #ifdef CONFIG_HAVE_MACH_CLKDEV 17 18 #include <mach/clkdev.h> 19 + #else 20 + #define __clk_get(clk) ({ 1; }) 21 + #define __clk_put(clk) do { } while (0) 22 + #endif 18 23 19 24 static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) 20 25 {
+11 -1
arch/arm/include/asm/pci.h
··· 3 3 4 4 #ifdef __KERNEL__ 5 5 #include <asm-generic/pci-dma-compat.h> 6 + #include <asm-generic/pci-bridge.h> 6 7 7 8 #include <asm/mach/pci.h> /* for pci_sys_data */ 8 - #include <mach/hardware.h> /* for PCIBIOS_MIN_* */ 9 + 10 + extern unsigned long pcibios_min_io; 11 + #define PCIBIOS_MIN_IO pcibios_min_io 12 + extern unsigned long pcibios_min_mem; 13 + #define PCIBIOS_MIN_MEM pcibios_min_mem 14 + 15 + static inline int pcibios_assign_all_busses(void) 16 + { 17 + return pci_has_flag(PCI_REASSIGN_ALL_RSRC); 18 + } 9 19 10 20 #ifdef CONFIG_PCI_DOMAINS 11 21 static inline int pci_domain_nr(struct pci_bus *bus)
+3 -2
arch/arm/include/asm/vga.h
··· 2 2 #define ASMARM_VGA_H 3 3 4 4 #include <linux/io.h> 5 - #include <mach/hardware.h> 6 5 7 - #define VGA_MAP_MEM(x,s) (PCIMEM_BASE + (x)) 6 + extern unsigned long vga_base; 7 + 8 + #define VGA_MAP_MEM(x,s) (vga_base + (x)) 8 9 9 10 #define vga_readb(x) (*((volatile unsigned char *)x)) 10 11 #define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x))
-1
arch/arm/lib/ecard.S
··· 12 12 */ 13 13 #include <linux/linkage.h> 14 14 #include <asm/assembler.h> 15 - #include <mach/hardware.h> 16 15 17 16 #define CPSR2SPSR(rt) \ 18 17 mrs rt, cpsr; \
-1
arch/arm/lib/io-readsw-armv3.S
··· 9 9 */ 10 10 #include <linux/linkage.h> 11 11 #include <asm/assembler.h> 12 - #include <mach/hardware.h> 13 12 14 13 .Linsw_bad_alignment: 15 14 adr r0, .Linsw_bad_align_msg
-1
arch/arm/lib/io-writesw-armv3.S
··· 9 9 */ 10 10 #include <linux/linkage.h> 11 11 #include <asm/assembler.h> 12 - #include <mach/hardware.h> 13 12 14 13 .Loutsw_bad_alignment: 15 14 adr r0, .Loutsw_bad_align_msg
-7
arch/arm/mach-at91/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-7
arch/arm/mach-bcmring/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-2
arch/arm/mach-bcmring/include/mach/hardware.h
··· 36 36 #define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED) 37 37 #define RAM_BASE PAGE_OFFSET 38 38 39 - #define pcibios_assign_all_busses() 1 40 - 41 39 /* Macros to make managing spinlocks a bit more controlled in terms of naming. */ 42 40 /* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */ 43 41 #if defined(__KERNEL__)
-1
arch/arm/mach-cns3xxx/cns3420vb.c
··· 29 29 #include <asm/mach/arch.h> 30 30 #include <asm/mach/map.h> 31 31 #include <asm/mach/time.h> 32 - #include <mach/hardware.h> 33 32 #include <mach/cns3xxx.h> 34 33 #include <mach/irqs.h> 35 34 #include "core.h"
-22
arch/arm/mach-cns3xxx/include/mach/hardware.h
··· 1 - /* 2 - * This file contains the hardware definitions of the Cavium Networks boards. 3 - * 4 - * Copyright 2003 ARM Limited. 5 - * Copyright 2008 Cavium Networks 6 - * 7 - * This file is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License, Version 2, as 9 - * published by the Free Software Foundation. 10 - */ 11 - 12 - #ifndef __MACH_HARDWARE_H 13 - #define __MACH_HARDWARE_H 14 - 15 - #include <asm/sizes.h> 16 - 17 - /* macro to get at IO space when running virtually */ 18 - #define PCIBIOS_MIN_IO 0x00000000 19 - #define PCIBIOS_MIN_MEM 0x00000000 20 - #define pcibios_assign_all_busses() 1 21 - 22 - #endif
+3
arch/arm/mach-cns3xxx/pcie.c
··· 369 369 { 370 370 int i; 371 371 372 + pcibios_min_io = 0; 373 + pcibios_min_mem = 0; 374 + 372 375 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, 373 376 "imprecise external abort"); 374 377
-15
arch/arm/mach-davinci/include/mach/clkdev.h
··· 1 - #ifndef __MACH_CLKDEV_H 2 - #define __MACH_CLKDEV_H 3 - 4 - struct clk; 5 - 6 - static inline int __clk_get(struct clk *clk) 7 - { 8 - return 1; 9 - } 10 - 11 - static inline void __clk_put(struct clk *clk) 12 - { 13 - } 14 - 15 - #endif
-7
arch/arm/mach-dove/include/mach/hardware.h
··· 11 11 12 12 #include "dove.h" 13 13 14 - #define pcibios_assign_all_busses() 1 15 - 16 - #define PCIBIOS_MIN_IO 0x1000 17 - #define PCIBIOS_MIN_MEM 0x01000000 18 - #define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE 19 - 20 - 21 14 /* Macros below are required for compatibility with PXA AC'97 driver. */ 22 15 #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ 23 16 DOVE_SB_REGS_VIRT_BASE)))
+3
arch/arm/mach-dove/pcie.c
··· 11 11 #include <linux/kernel.h> 12 12 #include <linux/pci.h> 13 13 #include <linux/mbus.h> 14 + #include <video/vga.h> 14 15 #include <asm/mach/pci.h> 15 16 #include <asm/mach/arch.h> 16 17 #include <asm/setup.h> ··· 229 228 230 229 void __init dove_pcie_init(int init_port0, int init_port1) 231 230 { 231 + vga_base = DOVE_PCIE0_MEM_PHYS_BASE; 232 + 232 233 if (init_port0) 233 234 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); 234 235
-11
arch/arm/mach-ep93xx/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-ep93xx/include/mach/clkdev.h 3 - */ 4 - 5 - #ifndef __ASM_MACH_CLKDEV_H 6 - #define __ASM_MACH_CLKDEV_H 7 - 8 - #define __clk_get(clk) ({ 1; }) 9 - #define __clk_put(clk) do { } while (0) 10 - 11 - #endif
-2
arch/arm/mach-ep93xx/include/mach/hardware.h
··· 8 8 #include <mach/ep93xx-regs.h> 9 9 #include <mach/platform.h> 10 10 11 - #define pcibios_assign_all_busses() 0 12 - 13 11 /* 14 12 * The EP93xx has two external crystal oscillators. To generate the 15 13 * required high-frequency clocks, the processor uses two phase-locked-
+3
arch/arm/mach-footbridge/dc21285.c
··· 295 295 unsigned int mem_size, mem_mask; 296 296 int cfn_mode; 297 297 298 + pcibios_min_mem = 0x81000000; 299 + vga_base = PCIMEM_BASE; 300 + 298 301 mem_size = (unsigned int)high_memory - PAGE_OFFSET; 299 302 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) 300 303 if (mem_mask >= mem_size)
-5
arch/arm/mach-footbridge/include/mach/hardware.h
··· 100 100 extern void nw_cpld_modify(unsigned int mask, unsigned int set); 101 101 #endif 102 102 103 - #define pcibios_assign_all_busses() 1 104 - 105 - #define PCIBIOS_MIN_IO 0x1000 106 - #define PCIBIOS_MIN_MEM 0x81000000 107 - 108 103 #endif
-7
arch/arm/mach-integrator/include/mach/hardware.h
··· 32 32 #define IO_SIZE 0x0B000000 // How much? 33 33 #define IO_START INTEGRATOR_HDR_BASE // PA of IO 34 34 35 - #define PCIMEM_BASE PCI_MEMORY_VADDR 36 - 37 - #define pcibios_assign_all_busses() 1 38 - 39 - #define PCIBIOS_MIN_IO 0x6000 40 - #define PCIBIOS_MIN_MEM 0x00100000 41 - 42 35 /* macro to get at IO space when running virtually */ 43 36 #ifdef CONFIG_MMU 44 37 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
+5
arch/arm/mach-integrator/pci_v3.c
··· 27 27 #include <linux/spinlock.h> 28 28 #include <linux/init.h> 29 29 #include <linux/io.h> 30 + #include <video/vga.h> 30 31 31 32 #include <mach/hardware.h> 32 33 #include <mach/platform.h> ··· 502 501 unsigned long flags; 503 502 unsigned int temp; 504 503 int ret; 504 + 505 + pcibios_min_io = 0x6000; 506 + pcibios_min_mem = 0x00100000; 507 + vga_base = PCI_MEMORY_VADDR; 505 508 506 509 /* 507 510 * Hook in our fault handler for PCI errors
-7
arch/arm/mach-iop13xx/include/mach/hardware.h
··· 2 2 #define __ASM_ARCH_HARDWARE_H 3 3 #include <asm/types.h> 4 4 5 - #define pcibios_assign_all_busses() 1 6 - 7 5 #ifndef __ASSEMBLY__ 8 - extern unsigned long iop13xx_pcibios_min_io; 9 - extern unsigned long iop13xx_pcibios_min_mem; 10 6 extern u16 iop13xx_dev_id(void); 11 7 extern void iop13xx_set_atu_mmr_bases(void); 12 8 #endif 13 - 14 - #define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io) 15 - #define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem) 16 9 17 10 /* 18 11 * Generic chipset bits
+2 -3
arch/arm/mach-iop13xx/pci.c
··· 39 39 u32 iop13xx_atux_mem_base; 40 40 size_t iop13xx_atue_mem_size; 41 41 size_t iop13xx_atux_mem_size; 42 - unsigned long iop13xx_pcibios_min_io = 0; 43 - unsigned long iop13xx_pcibios_min_mem = 0; 44 42 45 43 EXPORT_SYMBOL(iop13xx_atue_mem_base); 46 44 EXPORT_SYMBOL(iop13xx_atux_mem_base); ··· 969 971 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); 970 972 971 973 /* Setup the Min Address for PCI memory... */ 972 - iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 974 + pcibios_min_io = 0; 975 + pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 973 976 974 977 /* if Linux is given control of an ATU 975 978 * clear out its prior configuration,
-3
arch/arm/mach-iop32x/include/mach/hardware.h
··· 18 18 * but when we read them, we convert them to virtual addresses. See 19 19 * arch/arm/plat-iop/pci.c. 20 20 */ 21 - #define pcibios_assign_all_busses() 1 22 - #define PCIBIOS_MIN_IO 0x00000000 23 - #define PCIBIOS_MIN_MEM 0x00000000 24 21 25 22 #ifndef __ASSEMBLY__ 26 23 void iop32x_init_irq(void);
-3
arch/arm/mach-iop33x/include/mach/hardware.h
··· 18 18 * but when we read them, we convert them to virtual addresses. See 19 19 * arch/arm/mach-iop3xx/iop3xx-pci.c 20 20 */ 21 - #define pcibios_assign_all_busses() 1 22 - #define PCIBIOS_MIN_IO 0x00000000 23 - #define PCIBIOS_MIN_MEM 0x00000000 24 21 25 22 #ifndef __ASSEMBLY__ 26 23 void iop33x_init_irq(void);
-8
arch/arm/mach-ixp2000/include/mach/hardware.h
··· 19 19 #ifndef __ASM_ARCH_HARDWARE_H__ 20 20 #define __ASM_ARCH_HARDWARE_H__ 21 21 22 - /* 23 - * This needs to be platform-specific? 24 - */ 25 - #define PCIBIOS_MIN_IO 0x00000000 26 - #define PCIBIOS_MIN_MEM 0x00000000 27 - 28 22 #include "ixp2000-regs.h" /* Chipset Registers */ 29 - 30 - #define pcibios_assign_all_busses() 0 31 23 32 24 /* 33 25 * Platform helper functions
+5
arch/arm/mach-ixp2000/pci.c
··· 196 196 void __init 197 197 ixp2000_pci_preinit(void) 198 198 { 199 + pci_set_flags(0); 200 + 201 + pcibios_min_io = 0; 202 + pcibios_min_mem = 0; 203 + 199 204 #ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO 200 205 /* 201 206 * Configure the PCI unit to properly byteswap I/O transactions,
-4
arch/arm/mach-ixp23xx/include/mach/hardware.h
··· 15 15 #define __ASM_ARCH_HARDWARE_H 16 16 17 17 /* PCI IO info */ 18 - #define PCIBIOS_MIN_IO 0x00000000 19 - #define PCIBIOS_MIN_MEM 0xe0000000 20 18 21 19 #include "ixp23xx.h" 22 - 23 - #define pcibios_assign_all_busses() 0 24 20 25 21 /* 26 22 * Platform helper functions
+5
arch/arm/mach-ixp23xx/pci.c
··· 227 227 228 228 void __init ixp23xx_pci_preinit(void) 229 229 { 230 + pcibios_min_io = 0; 231 + pcibios_min_mem = 0xe0000000; 232 + 233 + pci_set_flags(0); 234 + 230 235 ixp23xx_pci_common_init(); 231 236 232 237 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
+5
arch/arm/mach-ixp4xx/common-pci.c
··· 346 346 { 347 347 unsigned long cpuid = read_cpuid_id(); 348 348 349 + #ifdef CONFIG_IXP4XX_INDIRECT_PCI 350 + pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */ 351 + #else 352 + pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */ 353 + #endif 349 354 /* 350 355 * Determine which PCI read method to use. 351 356 * Rev 0 IXP425 requires workaround.
-5
arch/arm/mach-ixp4xx/include/mach/hardware.h
··· 17 17 #ifndef __ASM_ARCH_HARDWARE_H__ 18 18 #define __ASM_ARCH_HARDWARE_H__ 19 19 20 - #define PCIBIOS_MIN_IO 0x00001000 21 20 #ifdef CONFIG_IXP4XX_INDIRECT_PCI 22 - #define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */ 23 21 #define PCIBIOS_MAX_MEM 0x4FFFFFFF 24 22 #else 25 - #define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */ 26 23 #define PCIBIOS_MAX_MEM 0x4BFFFFFF 27 24 #endif 28 25 29 26 #define ARCH_HAS_DMA_SET_COHERENT_MASK 30 - 31 - #define pcibios_assign_all_busses() 1 32 27 33 28 /* Register locations and bits */ 34 29 #include "ixp4xx-regs.h"
-7
arch/arm/mach-kirkwood/include/mach/hardware.h
··· 11 11 12 12 #include "kirkwood.h" 13 13 14 - #define pcibios_assign_all_busses() 1 15 - 16 - #define PCIBIOS_MIN_IO 0x00001000 17 - #define PCIBIOS_MIN_MEM 0x01000000 18 - #define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */ 19 - 20 - 21 14 #endif
+3
arch/arm/mach-kirkwood/pcie.c
··· 12 12 #include <linux/pci.h> 13 13 #include <linux/slab.h> 14 14 #include <linux/mbus.h> 15 + #include <video/vga.h> 15 16 #include <asm/irq.h> 16 17 #include <asm/mach/pci.h> 17 18 #include <plat/pcie.h> ··· 272 271 273 272 void __init kirkwood_pcie_init(unsigned int portmask) 274 273 { 274 + vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; 275 + 275 276 if (portmask & KW_PCIE0) 276 277 add_pcie_port(0, PCIE_VIRT_BASE); 277 278
-9
arch/arm/mach-ks8695/include/mach/hardware.h
··· 42 42 #define KS8695_PCIIO_PA 0x80000000 43 43 #define KS8695_PCIIO_SIZE SZ_64K 44 44 45 - 46 - /* 47 - * PCI support 48 - */ 49 - #define pcibios_assign_all_busses() 1 50 - 51 - #define PCIBIOS_MIN_IO 0 52 - #define PCIBIOS_MIN_MEM 0 53 - 54 45 #endif
+3
arch/arm/mach-ks8695/pci.c
··· 317 317 return; 318 318 } 319 319 320 + pcibios_min_io = 0; 321 + pcibios_min_mem = 0; 322 + 320 323 printk(KERN_INFO "PCI: Initialising\n"); 321 324 ks8695_show_pciregs(); 322 325
-25
arch/arm/mach-lpc32xx/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-lpc32xx/include/mach/clkdev.h 3 - * 4 - * Author: Kevin Wells <kevin.wells@nxp.com> 5 - * 6 - * Copyright (C) 2010 NXP Semiconductors 7 - * 8 - * This program is free software; you can redistribute it and/or modify 9 - * it under the terms of the GNU General Public License as published by 10 - * the Free Software Foundation; either version 2 of the License, or 11 - * (at your option) any later version. 12 - * 13 - * This program is distributed in the hope that it will be useful, 14 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 - * GNU General Public License for more details. 17 - */ 18 - 19 - #ifndef __ASM_ARCH_CLKDEV_H 20 - #define __ASM_ARCH_CLKDEV_H 21 - 22 - #define __clk_get(clk) ({ 1; }) 23 - #define __clk_put(clk) do { } while (0) 24 - 25 - #endif
-7
arch/arm/mach-mmp/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif /* __ASM_MACH_CLKDEV_H */
-19
arch/arm/mach-msm/include/mach/clkdev.h
··· 1 - /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. 2 - * 3 - * This program is free software; you can redistribute it and/or modify 4 - * it under the terms of the GNU General Public License version 2 and 5 - * only version 2 as published by the Free Software Foundation. 6 - * 7 - * This program is distributed in the hope that it will be useful, 8 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 - * GNU General Public License for more details. 11 - */ 12 - #ifndef __ASM_ARCH_MSM_CLKDEV_H 13 - #define __ASM_ARCH_MSM_CLKDEV_H 14 - 15 - struct clk; 16 - 17 - static inline int __clk_get(struct clk *clk) { return 1; } 18 - static inline void __clk_put(struct clk *clk) { } 19 - #endif
-7
arch/arm/mach-mv78xx0/include/mach/hardware.h
··· 11 11 12 12 #include "mv78xx0.h" 13 13 14 - #define pcibios_assign_all_busses() 1 15 - 16 - #define PCIBIOS_MIN_IO 0x00001000 17 - #define PCIBIOS_MIN_MEM 0x01000000 18 - #define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */ 19 - 20 - 21 14 #endif
+3
arch/arm/mach-mv78xx0/pcie.c
··· 11 11 #include <linux/kernel.h> 12 12 #include <linux/pci.h> 13 13 #include <linux/mbus.h> 14 + #include <video/vga.h> 14 15 #include <asm/irq.h> 15 16 #include <asm/mach/pci.h> 16 17 #include <plat/pcie.h> ··· 298 297 299 298 void __init mv78xx0_pcie_init(int init_port0, int init_port1) 300 299 { 300 + vga_base = MV78XX0_PCIE_MEM_PHYS_BASE; 301 + 301 302 if (init_port0) { 302 303 add_pcie_port(0, 0, PCIE00_VIRT_BASE); 303 304 if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
-7
arch/arm/mach-mxs/include/mach/clkdev.h
··· 1 - #ifndef __MACH_MXS_CLKDEV_H__ 2 - #define __MACH_MXS_CLKDEV_H__ 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-7
arch/arm/mach-nomadik/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-7
arch/arm/mach-nuc93x/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-5
arch/arm/mach-omap1/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-omap1/include/mach/clkdev.h 3 - */ 4 - 5 - #include <plat/clkdev.h>
-5
arch/arm/mach-omap2/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-omap2/include/mach/clkdev.h 3 - */ 4 - 5 - #include <plat/clkdev.h>
-7
arch/arm/mach-orion5x/include/mach/hardware.h
··· 11 11 12 12 #include "orion5x.h" 13 13 14 - #define pcibios_assign_all_busses() 1 15 - 16 - #define PCIBIOS_MIN_IO 0x00001000 17 - #define PCIBIOS_MIN_MEM 0x01000000 18 - #define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE 19 - 20 - 21 14 #endif
+2
arch/arm/mach-orion5x/pci.c
··· 560 560 { 561 561 int ret = 0; 562 562 563 + vga_base = ORION5X_PCIE_MEM_PHYS_BASE; 564 + 563 565 if (nr == 0) { 564 566 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 565 567 ret = pcie_setup(sys);
-7
arch/arm/mach-pnx4008/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
+3
arch/arm/mach-pxa/cm-x2xx-pci.c
··· 125 125 { 126 126 pr_info("Initializing CM-X2XX PCI subsystem\n"); 127 127 128 + pcibios_min_io = 0; 129 + pcibios_min_mem = 0; 130 + 128 131 __raw_writel(0x800, IT8152_PCI_CFG_ADDR); 129 132 if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { 130 133 pr_info("PCI Bridge found.\n");
-7
arch/arm/mach-pxa/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-3
arch/arm/mach-pxa/include/mach/hardware.h
··· 337 337 #endif 338 338 339 339 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 340 - #define PCIBIOS_MIN_IO 0 341 - #define PCIBIOS_MIN_MEM 0 342 - #define pcibios_assign_all_busses() 1 343 340 #define ARCH_HAS_DMA_SET_COHERENT_MASK 344 341 #endif 345 342
-8
arch/arm/mach-sa1100/include/mach/hardware.h
··· 76 76 #include "SA-1101.h" 77 77 #endif 78 78 79 - #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI) 80 - #define PCIBIOS_MIN_IO 0 81 - #define PCIBIOS_MIN_MEM 0 82 - #define pcibios_assign_all_busses() 1 83 - #define HAVE_ARCH_PCI_SET_DMA_MASK 1 84 - #endif 85 - 86 - 87 79 #endif /* _ASM_ARCH_HARDWARE_H */
+3
arch/arm/mach-sa1100/pci-nanoengine.c
··· 252 252 { 253 253 int ret = 0; 254 254 255 + pcibios_min_io = 0; 256 + pcibios_min_mem = 0; 257 + 255 258 if (nr == 0) { 256 259 sys->mem_offset = NANO_PCI_MEM_RW_PHYS; 257 260 sys->io_offset = 0x400;
-6
arch/arm/mach-shark/include/mach/hardware.h
··· 12 12 13 13 #define UNCACHEABLE_ADDR 0xdf010000 14 14 15 - #define pcibios_assign_all_busses() 1 16 - 17 - #define PCIBIOS_MIN_IO 0x6000 18 - #define PCIBIOS_MIN_MEM 0x50000000 19 - #define PCIMEM_BASE 0xe8000000 20 - 21 15 #endif 22 16
+10 -2
arch/arm/mach-shark/pci.c
··· 8 8 #include <linux/kernel.h> 9 9 #include <linux/pci.h> 10 10 #include <linux/init.h> 11 + #include <video/vga.h> 11 12 12 13 #include <asm/irq.h> 13 14 #include <asm/mach/pci.h> ··· 38 37 39 38 static int __init shark_pci_init(void) 40 39 { 41 - if (machine_is_shark()) 42 - pci_common_init(&shark_pci); 40 + if (!machine_is_shark()) 41 + return; 42 + 43 + pcibios_min_io = 0x6000; 44 + pcibios_min_mem = 0x50000000; 45 + vga_base = 0xe8000000; 46 + 47 + pci_common_init(&shark_pci); 48 + 43 49 return 0; 44 50 } 45 51
-19
arch/arm/mach-spear3xx/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-spear3xx/include/mach/clkdev.h 3 - * 4 - * Clock Dev framework definitions for SPEAr3xx machine family 5 - * 6 - * Copyright (C) 2009 ST Microelectronics 7 - * Viresh Kumar<viresh.kumar@st.com> 8 - * 9 - * This file is licensed under the terms of the GNU General Public 10 - * License version 2. This program is licensed "as is" without any 11 - * warranty of any kind, whether express or implied. 12 - */ 13 - 14 - #ifndef __MACH_CLKDEV_H 15 - #define __MACH_CLKDEV_H 16 - 17 - #include <plat/clkdev.h> 18 - 19 - #endif /* __MACH_CLKDEV_H */
-19
arch/arm/mach-spear6xx/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-spear6xx/include/mach/clkdev.h 3 - * 4 - * Clock Dev framework definitions for SPEAr6xx machine family 5 - * 6 - * Copyright (C) 2009 ST Microelectronics 7 - * Viresh Kumar<viresh.kumar@st.com> 8 - * 9 - * This file is licensed under the terms of the GNU General Public 10 - * License version 2. This program is licensed "as is" without any 11 - * warranty of any kind, whether express or implied. 12 - */ 13 - 14 - #ifndef __MACH_CLKDEV_H 15 - #define __MACH_CLKDEV_H 16 - 17 - #include <plat/clkdev.h> 18 - 19 - #endif /* __MACH_CLKDEV_H */
-34
arch/arm/mach-tegra/include/mach/clkdev.h
··· 1 - /* 2 - * arch/arm/mach-tegra/include/mach/clkdev.h 3 - * 4 - * Copyright (C) 2010 Google, Inc. 5 - * 6 - * Author: 7 - * Colin Cross <ccross@google.com> 8 - * 9 - * This software is licensed under the terms of the GNU General Public 10 - * License version 2, as published by the Free Software Foundation, and 11 - * may be copied, distributed, and modified under those terms. 12 - * 13 - * This program is distributed in the hope that it will be useful, 14 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 - * GNU General Public License for more details. 17 - * 18 - */ 19 - 20 - #ifndef __MACH_CLKDEV_H 21 - #define __MACH_CLKDEV_H 22 - 23 - struct clk; 24 - 25 - static inline int __clk_get(struct clk *clk) 26 - { 27 - return 1; 28 - } 29 - 30 - static inline void __clk_put(struct clk *clk) 31 - { 32 - } 33 - 34 - #endif
-28
arch/arm/mach-tegra/include/mach/hardware.h
··· 1 - /* 2 - * arch/arm/mach-tegra/include/mach/hardware.h 3 - * 4 - * Copyright (C) 2010 Google, Inc. 5 - * 6 - * Author: 7 - * Colin Cross <ccross@google.com> 8 - * Erik Gilling <konkers@google.com> 9 - * 10 - * This software is licensed under the terms of the GNU General Public 11 - * License version 2, as published by the Free Software Foundation, and 12 - * may be copied, distributed, and modified under those terms. 13 - * 14 - * This program is distributed in the hope that it will be useful, 15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 - * GNU General Public License for more details. 18 - * 19 - */ 20 - 21 - #ifndef __MACH_TEGRA_HARDWARE_H 22 - #define __MACH_TEGRA_HARDWARE_H 23 - 24 - #define PCIBIOS_MIN_IO 0x1000 25 - #define PCIBIOS_MIN_MEM 0 26 - #define pcibios_assign_all_busses() 1 27 - 28 - #endif
-1
arch/arm/mach-tegra/include/mach/system.h
··· 21 21 #ifndef __MACH_TEGRA_SYSTEM_H 22 22 #define __MACH_TEGRA_SYSTEM_H 23 23 24 - #include <mach/hardware.h> 25 24 #include <mach/iomap.h> 26 25 27 26 extern void (*arch_reset)(char mode, const char *cmd);
-1
arch/arm/mach-tegra/io.c
··· 24 24 #include <linux/mm.h> 25 25 #include <linux/io.h> 26 26 27 - #include <mach/hardware.h> 28 27 #include <asm/page.h> 29 28 #include <asm/mach/map.h> 30 29
+2
arch/arm/mach-tegra/pcie.c
··· 912 912 if (!(init_port0 || init_port1)) 913 913 return -ENODEV; 914 914 915 + pcibios_min_mem = 0; 916 + 915 917 err = tegra_pcie_get_resources(); 916 918 if (err) 917 919 return err;
-1
arch/arm/mach-tegra/platsmp.c
··· 21 21 22 22 #include <asm/cacheflush.h> 23 23 #include <asm/hardware/gic.h> 24 - #include <mach/hardware.h> 25 24 #include <asm/mach-types.h> 26 25 #include <asm/smp_scu.h> 27 26
-7
arch/arm/mach-ux500/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-6
arch/arm/mach-versatile/include/mach/hardware.h
··· 30 30 #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul 31 31 #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul 32 32 33 - /* CIK guesswork */ 34 - #define PCIBIOS_MIN_IO 0x44000000 35 - #define PCIBIOS_MIN_MEM 0x50000000 36 - 37 - #define pcibios_assign_all_busses() 1 38 - 39 33 /* macro to get at IO space when running virtually */ 40 34 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) 41 35
+3
arch/arm/mach-versatile/pci.c
··· 311 311 312 312 void __init pci_versatile_preinit(void) 313 313 { 314 + pcibios_min_io = 0x44000000; 315 + pcibios_min_mem = 0x50000000; 316 + 314 317 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); 315 318 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1); 316 319 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
-7
arch/arm/mach-w90x900/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
+12
arch/arm/mm/iomap.c
··· 9 9 #include <linux/ioport.h> 10 10 #include <linux/io.h> 11 11 12 + unsigned long vga_base; 13 + EXPORT_SYMBOL(vga_base); 14 + 12 15 #ifdef __io 13 16 void __iomem *ioport_map(unsigned long port, unsigned int nr) 14 17 { ··· 26 23 #endif 27 24 28 25 #ifdef CONFIG_PCI 26 + unsigned long pcibios_min_io = 0x1000; 27 + EXPORT_SYMBOL(pcibios_min_io); 28 + 29 + unsigned long pcibios_min_mem = 0x01000000; 30 + EXPORT_SYMBOL(pcibios_min_mem); 31 + 32 + unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC; 33 + EXPORT_SYMBOL(pci_flags); 34 + 29 35 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 30 36 { 31 37 resource_size_t start = pci_resource_start(dev, bar);
-1
arch/arm/mm/proc-xsc3.S
··· 28 28 #include <linux/init.h> 29 29 #include <asm/assembler.h> 30 30 #include <asm/hwcap.h> 31 - #include <mach/hardware.h> 32 31 #include <asm/pgtable.h> 33 32 #include <asm/pgtable-hwdef.h> 34 33 #include <asm/page.h>
+3
arch/arm/plat-iop/pci.c
··· 374 374 375 375 void __init iop3xx_pci_preinit(void) 376 376 { 377 + pcibios_min_io = 0; 378 + pcibios_min_mem = 0; 379 + 377 380 iop3xx_atu_disable(); 378 381 iop3xx_atu_setup(); 379 382 iop3xx_atu_debug();
-7
arch/arm/plat-mxc/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
-13
arch/arm/plat-omap/include/plat/clkdev.h
··· 1 - #ifndef __MACH_CLKDEV_H 2 - #define __MACH_CLKDEV_H 3 - 4 - static inline int __clk_get(struct clk *clk) 5 - { 6 - return 1; 7 - } 8 - 9 - static inline void __clk_put(struct clk *clk) 10 - { 11 - } 12 - 13 - #endif
-20
arch/arm/plat-spear/include/plat/clkdev.h
··· 1 - /* 2 - * arch/arm/plat-spear/include/plat/clkdev.h 3 - * 4 - * Clock Dev framework definitions for SPEAr platform 5 - * 6 - * Copyright (C) 2009 ST Microelectronics 7 - * Viresh Kumar<viresh.kumar@st.com> 8 - * 9 - * This file is licensed under the terms of the GNU General Public 10 - * License version 2. This program is licensed "as is" without any 11 - * warranty of any kind, whether express or implied. 12 - */ 13 - 14 - #ifndef __PLAT_CLKDEV_H 15 - #define __PLAT_CLKDEV_H 16 - 17 - #define __clk_get(clk) ({ 1; }) 18 - #define __clk_put(clk) do { } while (0) 19 - 20 - #endif /* __PLAT_CLKDEV_H */
-7
arch/arm/plat-tcc/include/mach/clkdev.h
··· 1 - #ifndef __ASM_MACH_CLKDEV_H 2 - #define __ASM_MACH_CLKDEV_H 3 - 4 - #define __clk_get(clk) ({ 1; }) 5 - #define __clk_put(clk) do { } while (0) 6 - 7 - #endif
+10 -54
arch/microblaze/include/asm/pci-bridge.h
··· 10 10 #include <linux/pci.h> 11 11 #include <linux/list.h> 12 12 #include <linux/ioport.h> 13 + #include <asm-generic/pci-bridge.h> 13 14 14 15 struct device_node; 15 16 16 - enum { 17 - /* Force re-assigning all resources (ignore firmware 18 - * setup completely) 19 - */ 20 - PCI_REASSIGN_ALL_RSRC = 0x00000001, 21 - 22 - /* Do not try to assign, just use existing setup */ 23 - PCI_PROBE_ONLY = 0x00000004, 24 - 25 - /* Don't bother with ISA alignment unless the bridge has 26 - * ISA forwarding enabled 27 - */ 28 - PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, 29 - 30 - /* Enable domain numbers in /proc */ 31 - PCI_ENABLE_PROC_DOMAINS = 0x00000010, 32 - /* ... except for domain 0 */ 33 - PCI_COMPAT_DOMAIN_0 = 0x00000020, 34 - }; 17 + #ifdef CONFIG_PCI 18 + extern struct list_head hose_list; 19 + extern int pcibios_vaddr_is_ioport(void __iomem *address); 20 + #else 21 + static inline int pcibios_vaddr_is_ioport(void __iomem *address) 22 + { 23 + return 0; 24 + } 25 + #endif 35 26 36 27 /* 37 28 * Structure of a PCI controller (host bridge) ··· 141 150 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 142 151 extern void pcibios_free_controller(struct pci_controller *phb); 143 152 extern void pcibios_setup_phb_resources(struct pci_controller *hose); 144 - 145 - #ifdef CONFIG_PCI 146 - extern unsigned int pci_flags; 147 - 148 - static inline void pci_set_flags(int flags) 149 - { 150 - pci_flags = flags; 151 - } 152 - 153 - static inline void pci_add_flags(int flags) 154 - { 155 - pci_flags |= flags; 156 - } 157 - 158 - static inline int pci_has_flag(int flag) 159 - { 160 - return pci_flags & flag; 161 - } 162 - 163 - extern struct list_head hose_list; 164 - 165 - extern int pcibios_vaddr_is_ioport(void __iomem *address); 166 - #else 167 - static inline int pcibios_vaddr_is_ioport(void __iomem *address) 168 - { 169 - return 0; 170 - } 171 - 172 - static inline void pci_set_flags(int flags) { } 173 - static inline void pci_add_flags(int flags) { } 174 - static inline int pci_has_flag(int flag) 175 - { 176 - return 0; 177 - } 178 - #endif /* CONFIG_PCI */ 179 153 180 154 #endif /* __KERNEL__ */ 181 155 #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
+1 -49
arch/powerpc/include/asm/pci-bridge.h
··· 10 10 #include <linux/pci.h> 11 11 #include <linux/list.h> 12 12 #include <linux/ioport.h> 13 + #include <asm-generic/pci-bridge.h> 13 14 14 15 struct device_node; 15 - 16 - enum { 17 - /* Force re-assigning all resources (ignore firmware 18 - * setup completely) 19 - */ 20 - PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001, 21 - 22 - /* Re-assign all bus numbers */ 23 - PPC_PCI_REASSIGN_ALL_BUS = 0x00000002, 24 - 25 - /* Do not try to assign, just use existing setup */ 26 - PPC_PCI_PROBE_ONLY = 0x00000004, 27 - 28 - /* Don't bother with ISA alignment unless the bridge has 29 - * ISA forwarding enabled 30 - */ 31 - PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, 32 - 33 - /* Enable domain numbers in /proc */ 34 - PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010, 35 - /* ... except for domain 0 */ 36 - PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020, 37 - }; 38 - #ifdef CONFIG_PCI 39 - extern unsigned int ppc_pci_flags; 40 - 41 - static inline void ppc_pci_set_flags(int flags) 42 - { 43 - ppc_pci_flags = flags; 44 - } 45 - 46 - static inline void ppc_pci_add_flags(int flags) 47 - { 48 - ppc_pci_flags |= flags; 49 - } 50 - 51 - static inline int ppc_pci_has_flag(int flag) 52 - { 53 - return (ppc_pci_flags & flag); 54 - } 55 - #else 56 - static inline void ppc_pci_set_flags(int flags) { } 57 - static inline void ppc_pci_add_flags(int flags) { } 58 - static inline int ppc_pci_has_flag(int flag) 59 - { 60 - return 0; 61 - } 62 - #endif 63 - 64 16 65 17 /* 66 18 * Structure of a PCI controller (host bridge)
+1 -1
arch/powerpc/include/asm/pci.h
··· 44 44 * bus numbers (don't do that on ppc64 yet !) 45 45 */ 46 46 #define pcibios_assign_all_busses() \ 47 - (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS)) 47 + (pci_has_flag(PCI_REASSIGN_ALL_BUS)) 48 48 49 49 static inline void pcibios_set_master(struct pci_dev *dev) 50 50 {
+11 -11
arch/powerpc/kernel/pci-common.c
··· 50 50 resource_size_t isa_mem_base; 51 51 52 52 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ 53 - unsigned int ppc_pci_flags = 0; 53 + unsigned int pci_flags = 0; 54 54 55 55 56 56 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; ··· 842 842 { 843 843 struct pci_controller *hose = pci_bus_to_host(bus); 844 844 845 - if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) 845 + if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 846 846 return 0; 847 - if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) 847 + if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 848 848 return hose->global_number != 0; 849 849 return 1; 850 850 } ··· 920 920 struct resource *res = dev->resource + i; 921 921 if (!res->flags) 922 922 continue; 923 - /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't 923 + /* On platforms that have PCI_PROBE_ONLY set, we don't 924 924 * consider 0 as an unassigned BAR value. It's technically 925 925 * a valid value, but linux doesn't like it... so when we can 926 926 * re-assign things, we do so, but if we can't, we keep it 927 927 * around and hope for the best... 928 928 */ 929 - if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 929 + if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) { 930 930 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", 931 931 pci_name(dev), i, 932 932 (unsigned long long)res->start, ··· 973 973 int i; 974 974 975 975 /* We don't do anything if PCI_PROBE_ONLY is set */ 976 - if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) 976 + if (pci_has_flag(PCI_PROBE_ONLY)) 977 977 return 0; 978 978 979 979 /* Job is a bit different between memory and IO */ ··· 1143 1143 1144 1144 static int skip_isa_ioresource_align(struct pci_dev *dev) 1145 1145 { 1146 - if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && 1146 + if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1147 1147 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1148 1148 return 1; 1149 1149 return 0; ··· 1271 1271 * and as such ensure proper re-allocation 1272 1272 * later. 1273 1273 */ 1274 - if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) 1274 + if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 1275 1275 goto clear_resource; 1276 1276 pr = pci_find_parent_resource(bus->self, res); 1277 1277 if (pr == res) { ··· 1456 1456 list_for_each_entry(b, &pci_root_buses, node) 1457 1457 pcibios_allocate_bus_resources(b); 1458 1458 1459 - if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { 1459 + if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1460 1460 pcibios_allocate_resources(0); 1461 1461 pcibios_allocate_resources(1); 1462 1462 } ··· 1465 1465 * the low IO area and the VGA memory area if they intersect the 1466 1466 * bus available resources to avoid allocating things on top of them 1467 1467 */ 1468 - if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1468 + if (!pci_has_flag(PCI_PROBE_ONLY)) { 1469 1469 list_for_each_entry(b, &pci_root_buses, node) 1470 1470 pcibios_reserve_legacy_regions(b); 1471 1471 } ··· 1473 1473 /* Now, if the platform didn't decide to blindly trust the firmware, 1474 1474 * we proceed to assigning things that were left unassigned 1475 1475 */ 1476 - if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { 1476 + if (!pci_has_flag(PCI_PROBE_ONLY)) { 1477 1477 pr_debug("PCI: Assigning unassigned resources...\n"); 1478 1478 pci_assign_unassigned_resources(); 1479 1479 }
+1 -1
arch/powerpc/kernel/pci_32.c
··· 230 230 231 231 printk(KERN_INFO "PCI: Probing PCI hardware\n"); 232 232 233 - if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS) 233 + if (pci_has_flag(PCI_REASSIGN_ALL_BUS)) 234 234 pci_assign_all_buses = 1; 235 235 236 236 /* Scan all of the recorded PCI controllers. */
+2 -2
arch/powerpc/kernel/pci_64.c
··· 55 55 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 56 56 57 57 if (pci_probe_only) 58 - ppc_pci_flags |= PPC_PCI_PROBE_ONLY; 58 + pci_add_flags(PCI_PROBE_ONLY); 59 59 60 60 /* On ppc64, we always enable PCI domains and we keep domain 0 61 61 * backward compatible in /proc for video cards 62 62 */ 63 - ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; 63 + pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 64 64 65 65 /* Scan all of the recorded PCI controllers. */ 66 66 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+1 -1
arch/powerpc/kernel/rtas_pci.c
··· 291 291 prop = of_get_property(of_chosen, 292 292 "linux,pci-assign-all-buses", NULL); 293 293 if (prop && *prop) 294 - ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS; 294 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 295 295 #endif /* CONFIG_PPC32 */ 296 296 } 297 297 }
+1 -1
arch/powerpc/platforms/40x/ep405.c
··· 100 100 /* Find & init the BCSR CPLD */ 101 101 ep405_init_bcsr(); 102 102 103 - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); 103 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 104 104 } 105 105 106 106 static int __init ep405_probe(void)
+1 -1
arch/powerpc/platforms/40x/ppc40x_simple.c
··· 61 61 static int __init ppc40x_probe(void) 62 62 { 63 63 if (of_flat_dt_match(of_get_flat_dt_root(), board)) { 64 - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); 64 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 65 65 return 1; 66 66 } 67 67
+1 -1
arch/powerpc/platforms/40x/walnut.c
··· 51 51 if (!of_flat_dt_is_compatible(root, "ibm,walnut")) 52 52 return 0; 53 53 54 - ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC; 54 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 55 55 56 56 return 1; 57 57 }
+1 -1
arch/powerpc/platforms/44x/canyonlands.c
··· 55 55 { 56 56 unsigned long root = of_get_flat_dt_root(); 57 57 if (of_flat_dt_is_compatible(root, "amcc,canyonlands")) { 58 - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); 58 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 59 59 return 1; 60 60 } 61 61 return 0;
+1 -1
arch/powerpc/platforms/44x/ebony.c
··· 54 54 if (!of_flat_dt_is_compatible(root, "ibm,ebony")) 55 55 return 0; 56 56 57 - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); 57 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 58 58 59 59 return 1; 60 60 }
+1 -1
arch/powerpc/platforms/44x/ppc44x_simple.c
··· 72 72 73 73 for (i = 0; i < ARRAY_SIZE(board); i++) { 74 74 if (of_flat_dt_is_compatible(root, board[i])) { 75 - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); 75 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 76 76 return 1; 77 77 } 78 78 }
+1 -1
arch/powerpc/platforms/44x/sam440ep.c
··· 51 51 if (!of_flat_dt_is_compatible(root, "acube,sam440ep")) 52 52 return 0; 53 53 54 - ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); 54 + pci_set_flags(PCI_REASSIGN_ALL_RSRC); 55 55 56 56 return 1; 57 57 }
+1 -1
arch/powerpc/platforms/52xx/mpc52xx_pci.c
··· 371 371 372 372 pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name); 373 373 374 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 374 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 375 375 376 376 if (of_address_to_resource(node, 0, &rsrc) != 0) { 377 377 printk(KERN_ERR "Can't get %s resources\n", node->full_name);
+1 -1
arch/powerpc/platforms/82xx/pq2.c
··· 53 53 if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) 54 54 goto err; 55 55 56 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 56 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 57 57 58 58 hose = pcibios_alloc_controller(np); 59 59 if (!hose)
+1 -1
arch/powerpc/platforms/chrp/pci.c
··· 199 199 printk ("RTAS supporting Pegasos OF not found, please upgrade" 200 200 " your firmware\n"); 201 201 } 202 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 202 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 203 203 /* keep the reference to the root node */ 204 204 } 205 205
+3 -3
arch/powerpc/platforms/powermac/pci.c
··· 732 732 static int __init setup_uninorth(struct pci_controller *hose, 733 733 struct resource *addr) 734 734 { 735 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 735 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 736 736 has_uninorth = 1; 737 737 hose->ops = &macrisc_pci_ops; 738 738 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); ··· 998 998 struct device_node *np, *root; 999 999 struct device_node *ht = NULL; 1000 1000 1001 - ppc_pci_set_flags(PPC_PCI_CAN_SKIP_ISA_ALIGN); 1001 + pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN); 1002 1002 1003 1003 root = of_find_node_by_path("/"); 1004 1004 if (root == NULL) { ··· 1057 1057 * some offset between bus number and domains for now when we 1058 1058 * assign all busses should help for now 1059 1059 */ 1060 - if (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS)) 1060 + if (pci_has_flag(PCI_REASSIGN_ALL_BUS)) 1061 1061 pcibios_assign_bus_offset = 0x10; 1062 1062 #endif 1063 1063 }
+2 -2
arch/powerpc/sysdev/fsl_pci.c
··· 351 351 printk(KERN_WARNING "Can't get bus-range for %s, assume" 352 352 " bus 0\n", dev->full_name); 353 353 354 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 354 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 355 355 hose = pcibios_alloc_controller(dev); 356 356 if (!hose) 357 357 return -ENOMEM; ··· 640 640 " bus 0\n", dev->full_name); 641 641 } 642 642 643 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 643 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 644 644 hose = pcibios_alloc_controller(dev); 645 645 if (!hose) 646 646 return -ENOMEM;
+1 -1
arch/powerpc/sysdev/grackle.c
··· 57 57 { 58 58 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); 59 59 if (of_machine_is_compatible("PowerMac1,1")) 60 - ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 60 + pci_add_flags(PCI_REASSIGN_ALL_BUS); 61 61 if (of_machine_is_compatible("AAPL,PowerBook1998")) 62 62 grackle_set_loop_snoop(hose, 1); 63 63 #if 0 /* Disabled for now, HW problems ??? */
+1 -1
arch/powerpc/sysdev/ppc4xx_pci.c
··· 1977 1977 { 1978 1978 struct device_node *np; 1979 1979 1980 - ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; 1980 + pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); 1981 1981 1982 1982 #ifdef CONFIG_PPC4xx_PCI_EXPRESS 1983 1983 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
+3
drivers/clk/Kconfig
··· 2 2 config CLKDEV_LOOKUP 3 3 bool 4 4 select HAVE_CLK 5 + 6 + config HAVE_MACH_CLKDEV 7 + bool
+62
include/asm-generic/pci-bridge.h
··· 1 + /* 2 + * This program is free software; you can redistribute it and/or 3 + * modify it under the terms of the GNU General Public License 4 + * as published by the Free Software Foundation; either version 5 + * 2 of the License, or (at your option) any later version. 6 + */ 7 + #ifndef _ASM_GENERIC_PCI_BRIDGE_H 8 + #define _ASM_GENERIC_PCI_BRIDGE_H 9 + 10 + #ifdef __KERNEL__ 11 + 12 + enum { 13 + /* Force re-assigning all resources (ignore firmware 14 + * setup completely) 15 + */ 16 + PCI_REASSIGN_ALL_RSRC = 0x00000001, 17 + 18 + /* Re-assign all bus numbers */ 19 + PCI_REASSIGN_ALL_BUS = 0x00000002, 20 + 21 + /* Do not try to assign, just use existing setup */ 22 + PCI_PROBE_ONLY = 0x00000004, 23 + 24 + /* Don't bother with ISA alignment unless the bridge has 25 + * ISA forwarding enabled 26 + */ 27 + PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, 28 + 29 + /* Enable domain numbers in /proc */ 30 + PCI_ENABLE_PROC_DOMAINS = 0x00000010, 31 + /* ... except for domain 0 */ 32 + PCI_COMPAT_DOMAIN_0 = 0x00000020, 33 + }; 34 + 35 + #ifdef CONFIG_PCI 36 + extern unsigned int pci_flags; 37 + 38 + static inline void pci_set_flags(int flags) 39 + { 40 + pci_flags = flags; 41 + } 42 + 43 + static inline void pci_add_flags(int flags) 44 + { 45 + pci_flags |= flags; 46 + } 47 + 48 + static inline int pci_has_flag(int flag) 49 + { 50 + return pci_flags & flag; 51 + } 52 + #else 53 + static inline void pci_set_flags(int flags) { } 54 + static inline void pci_add_flags(int flags) { } 55 + static inline int pci_has_flag(int flag) 56 + { 57 + return 0; 58 + } 59 + #endif /* CONFIG_PCI */ 60 + 61 + #endif /* __KERNEL__ */ 62 + #endif /* _ASM_GENERIC_PCI_BRIDGE_H */