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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
[ARM] 4487/1: ns9xxx: complete definition of GPIO related registers
I changed the naming to be more obvious---unfortunately the HRM
doesn't specify these.
Moreover the numbering is changed to be zero indexed as this is more
natural.
Adjust all callers.
Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by Uwe Kleine-König and committed by Russell King 3945a567 f4ae6413
+1
-2
arch/arm/mach-ns9xxx/board-a9m9750dev.c
+1
-2
arch/arm/mach-ns9xxx/board-a9m9750dev.c
···
91
* use GPIO 11, because GPIO 32 is used for the LCD
92
*/
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/* XXX: proper GPIO handling */
94
-
BBU_GC(2) &= ~0x2000;
95
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for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
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set_irq_chip(i, &a9m9750dev_fpga_chip);
···
196
platform_add_devices(board_a9m9750dev_devices,
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ARRAY_SIZE(board_a9m9750dev_devices));
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}
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-
···
91
* use GPIO 11, because GPIO 32 is used for the LCD
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*/
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/* XXX: proper GPIO handling */
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+
BBU_GCONFb1(1) &= ~0x2000;
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for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
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set_irq_chip(i, &a9m9750dev_fpga_chip);
···
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platform_add_devices(board_a9m9750dev_devices,
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ARRAY_SIZE(board_a9m9750dev_devices));
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}
+26
-2
include/asm-arm/arch-ns9xxx/regs-bbu.h
+26
-2
include/asm-arm/arch-ns9xxx/regs-bbu.h
···
15
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/* BBus Utility */
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+
/* GPIO Configuration Registers block 1 */
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+
/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
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+
* at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register
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+
* #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
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+
#define BBU_GCONFb1(x) __REG2(0x90600010, (x))
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+
#define BBU_GCONFb2(x) __REG2(0x90600100, (x))
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+
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+
#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2))
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+
#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
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+
#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1)
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+
#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2))
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+
#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0)
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+
#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1)
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+
#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
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+
#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0)
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+
#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1)
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+
#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2)
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+
#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3)
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+
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+
#define BBU_GCTRL1 __REG(0x90600030)
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+
#define BBU_GCTRL2 __REG(0x90600034)
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+
#define BBU_GCTRL3 __REG(0x90600120)
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+
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+
#define BBU_GSTAT1 __REG(0x90600040)
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+
#define BBU_GSTAT2 __REG(0x90600044)
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+
#define BBU_GSTAT3 __REG(0x90600130)
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#endif /* ifndef __ASM_ARCH_REGSBBU_H */