tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: cbb: Changes for v6.1-rc1
This introduces the CBB driver that is used to provide (a lot of)
information about SErrors when things go wrong, instead of the kernel
just crashing or hanging.
* tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: cbb: Add support for Tegra241 (Grace)
soc/tegra: cbb: Add driver for Tegra234 CBB 2.0
soc/tegra: cbb: Add CBB 1.0 driver for Tegra194
soc/tegra: Set ERD bit to mask inband errors
Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+3766
-2
+9
drivers/soc/tegra/Kconfig
+9
drivers/soc/tegra/Kconfig
···
161
161
bool "Voltage scaling support for Tegra30 SoCs"
162
162
depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
163
163
depends on REGULATOR
164
+
165
+
config SOC_TEGRA_CBB
166
+
tristate "Tegra driver to handle error from CBB"
167
+
depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
168
+
default y
169
+
help
170
+
Support for handling error from Tegra Control Backbone(CBB).
171
+
This driver handles the errors from CBB and prints debug
172
+
information about the failed transactions.
+1
drivers/soc/tegra/Makefile
+1
drivers/soc/tegra/Makefile
+9
drivers/soc/tegra/cbb/Makefile
+9
drivers/soc/tegra/cbb/Makefile
+190
drivers/soc/tegra/cbb/tegra-cbb.c
+190
drivers/soc/tegra/cbb/tegra-cbb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
4
+
*/
5
+
6
+
#include <linux/clk.h>
7
+
#include <linux/cpufeature.h>
8
+
#include <linux/debugfs.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/device.h>
14
+
#include <linux/io.h>
15
+
#include <linux/of_irq.h>
16
+
#include <linux/of_address.h>
17
+
#include <linux/interrupt.h>
18
+
#include <linux/ioport.h>
19
+
#include <linux/version.h>
20
+
#include <soc/tegra/fuse.h>
21
+
#include <soc/tegra/tegra-cbb.h>
22
+
23
+
void tegra_cbb_print_err(struct seq_file *file, const char *fmt, ...)
24
+
{
25
+
struct va_format vaf;
26
+
va_list args;
27
+
28
+
va_start(args, fmt);
29
+
30
+
if (file) {
31
+
seq_vprintf(file, fmt, args);
32
+
} else {
33
+
vaf.fmt = fmt;
34
+
vaf.va = &args;
35
+
pr_crit("%pV", &vaf);
36
+
}
37
+
38
+
va_end(args);
39
+
}
40
+
41
+
void tegra_cbb_print_cache(struct seq_file *file, u32 cache)
42
+
{
43
+
const char *buff_str, *mod_str, *rd_str, *wr_str;
44
+
45
+
buff_str = (cache & BIT(0)) ? "Bufferable " : "";
46
+
mod_str = (cache & BIT(1)) ? "Modifiable " : "";
47
+
rd_str = (cache & BIT(2)) ? "Read-Allocate " : "";
48
+
wr_str = (cache & BIT(3)) ? "Write-Allocate" : "";
49
+
50
+
if (cache == 0x0)
51
+
buff_str = "Device Non-Bufferable";
52
+
53
+
tegra_cbb_print_err(file, "\t Cache\t\t\t: 0x%x -- %s%s%s%s\n",
54
+
cache, buff_str, mod_str, rd_str, wr_str);
55
+
}
56
+
57
+
void tegra_cbb_print_prot(struct seq_file *file, u32 prot)
58
+
{
59
+
const char *data_str, *secure_str, *priv_str;
60
+
61
+
data_str = (prot & 0x4) ? "Instruction" : "Data";
62
+
secure_str = (prot & 0x2) ? "Non-Secure" : "Secure";
63
+
priv_str = (prot & 0x1) ? "Privileged" : "Unprivileged";
64
+
65
+
tegra_cbb_print_err(file, "\t Protection\t\t: 0x%x -- %s, %s, %s Access\n",
66
+
prot, priv_str, secure_str, data_str);
67
+
}
68
+
69
+
static int tegra_cbb_err_show(struct seq_file *file, void *data)
70
+
{
71
+
struct tegra_cbb *cbb = file->private;
72
+
73
+
return cbb->ops->debugfs_show(cbb, file, data);
74
+
}
75
+
76
+
static int tegra_cbb_err_open(struct inode *inode, struct file *file)
77
+
{
78
+
return single_open(file, tegra_cbb_err_show, inode->i_private);
79
+
}
80
+
81
+
static const struct file_operations tegra_cbb_err_fops = {
82
+
.open = tegra_cbb_err_open,
83
+
.read = seq_read,
84
+
.llseek = seq_lseek,
85
+
.release = single_release
86
+
};
87
+
88
+
static int tegra_cbb_err_debugfs_init(struct tegra_cbb *cbb)
89
+
{
90
+
static struct dentry *root;
91
+
92
+
if (!root) {
93
+
root = debugfs_create_file("tegra_cbb_err", 0444, NULL, cbb, &tegra_cbb_err_fops);
94
+
if (IS_ERR_OR_NULL(root)) {
95
+
pr_err("%s(): could not create debugfs node\n", __func__);
96
+
return PTR_ERR(root);
97
+
}
98
+
}
99
+
100
+
return 0;
101
+
}
102
+
103
+
void tegra_cbb_stall_enable(struct tegra_cbb *cbb)
104
+
{
105
+
if (cbb->ops->stall_enable)
106
+
cbb->ops->stall_enable(cbb);
107
+
}
108
+
109
+
void tegra_cbb_fault_enable(struct tegra_cbb *cbb)
110
+
{
111
+
if (cbb->ops->fault_enable)
112
+
cbb->ops->fault_enable(cbb);
113
+
}
114
+
115
+
void tegra_cbb_error_clear(struct tegra_cbb *cbb)
116
+
{
117
+
if (cbb->ops->error_clear)
118
+
cbb->ops->error_clear(cbb);
119
+
}
120
+
121
+
u32 tegra_cbb_get_status(struct tegra_cbb *cbb)
122
+
{
123
+
if (cbb->ops->get_status)
124
+
return cbb->ops->get_status(cbb);
125
+
126
+
return 0;
127
+
}
128
+
129
+
int tegra_cbb_get_irq(struct platform_device *pdev, unsigned int *nonsec_irq,
130
+
unsigned int *sec_irq)
131
+
{
132
+
unsigned int index = 0;
133
+
int num_intr = 0, irq;
134
+
135
+
num_intr = platform_irq_count(pdev);
136
+
if (!num_intr)
137
+
return -EINVAL;
138
+
139
+
if (num_intr == 2) {
140
+
irq = platform_get_irq(pdev, index);
141
+
if (irq <= 0) {
142
+
dev_err(&pdev->dev, "failed to get non-secure IRQ: %d\n", irq);
143
+
return -ENOENT;
144
+
}
145
+
146
+
*nonsec_irq = irq;
147
+
index++;
148
+
}
149
+
150
+
irq = platform_get_irq(pdev, index);
151
+
if (irq <= 0) {
152
+
dev_err(&pdev->dev, "failed to get secure IRQ: %d\n", irq);
153
+
return -ENOENT;
154
+
}
155
+
156
+
*sec_irq = irq;
157
+
158
+
if (num_intr == 1)
159
+
dev_dbg(&pdev->dev, "secure IRQ: %u\n", *sec_irq);
160
+
161
+
if (num_intr == 2)
162
+
dev_dbg(&pdev->dev, "secure IRQ: %u, non-secure IRQ: %u\n", *sec_irq, *nonsec_irq);
163
+
164
+
return 0;
165
+
}
166
+
167
+
int tegra_cbb_register(struct tegra_cbb *cbb)
168
+
{
169
+
int ret;
170
+
171
+
if (IS_ENABLED(CONFIG_DEBUG_FS)) {
172
+
ret = tegra_cbb_err_debugfs_init(cbb);
173
+
if (ret) {
174
+
dev_err(cbb->dev, "failed to create debugfs\n");
175
+
return ret;
176
+
}
177
+
}
178
+
179
+
/* register interrupt handler for errors due to different initiators */
180
+
ret = cbb->ops->interrupt_enable(cbb);
181
+
if (ret < 0) {
182
+
dev_err(cbb->dev, "Failed to register CBB Interrupt ISR");
183
+
return ret;
184
+
}
185
+
186
+
cbb->ops->error_enable(cbb);
187
+
dsb(sy);
188
+
189
+
return 0;
190
+
}
+2364
drivers/soc/tegra/cbb/tegra194-cbb.c
+2364
drivers/soc/tegra/cbb/tegra194-cbb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
4
+
*
5
+
* The driver handles Error's from Control Backbone(CBB) generated due to
6
+
* illegal accesses. When an error is reported from a NOC within CBB,
7
+
* the driver checks ErrVld status of all three Error Logger's of that NOC.
8
+
* It then prints debug information about failed transaction using ErrLog
9
+
* registers of error logger which has ErrVld set. Currently, SLV, DEC,
10
+
* TMO, SEC, UNS are the codes which are supported by CBB.
11
+
*/
12
+
13
+
#include <linux/clk.h>
14
+
#include <linux/cpufeature.h>
15
+
#include <linux/debugfs.h>
16
+
#include <linux/module.h>
17
+
#include <linux/of.h>
18
+
#include <linux/of_device.h>
19
+
#include <linux/platform_device.h>
20
+
#include <linux/device.h>
21
+
#include <linux/io.h>
22
+
#include <linux/of_irq.h>
23
+
#include <linux/of_address.h>
24
+
#include <linux/interrupt.h>
25
+
#include <linux/ioport.h>
26
+
#include <linux/version.h>
27
+
#include <soc/tegra/fuse.h>
28
+
#include <soc/tegra/tegra-cbb.h>
29
+
30
+
#define ERRLOGGER_0_ID_COREID_0 0x00000000
31
+
#define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
32
+
#define ERRLOGGER_0_FAULTEN_0 0x00000008
33
+
#define ERRLOGGER_0_ERRVLD_0 0x0000000c
34
+
#define ERRLOGGER_0_ERRCLR_0 0x00000010
35
+
#define ERRLOGGER_0_ERRLOG0_0 0x00000014
36
+
#define ERRLOGGER_0_ERRLOG1_0 0x00000018
37
+
#define ERRLOGGER_0_RSVD_00_0 0x0000001c
38
+
#define ERRLOGGER_0_ERRLOG3_0 0x00000020
39
+
#define ERRLOGGER_0_ERRLOG4_0 0x00000024
40
+
#define ERRLOGGER_0_ERRLOG5_0 0x00000028
41
+
#define ERRLOGGER_0_STALLEN_0 0x00000038
42
+
43
+
#define ERRLOGGER_1_ID_COREID_0 0x00000080
44
+
#define ERRLOGGER_1_ID_REVISIONID_0 0x00000084
45
+
#define ERRLOGGER_1_FAULTEN_0 0x00000088
46
+
#define ERRLOGGER_1_ERRVLD_0 0x0000008c
47
+
#define ERRLOGGER_1_ERRCLR_0 0x00000090
48
+
#define ERRLOGGER_1_ERRLOG0_0 0x00000094
49
+
#define ERRLOGGER_1_ERRLOG1_0 0x00000098
50
+
#define ERRLOGGER_1_RSVD_00_0 0x0000009c
51
+
#define ERRLOGGER_1_ERRLOG3_0 0x000000a0
52
+
#define ERRLOGGER_1_ERRLOG4_0 0x000000a4
53
+
#define ERRLOGGER_1_ERRLOG5_0 0x000000a8
54
+
#define ERRLOGGER_1_STALLEN_0 0x000000b8
55
+
56
+
#define ERRLOGGER_2_ID_COREID_0 0x00000100
57
+
#define ERRLOGGER_2_ID_REVISIONID_0 0x00000104
58
+
#define ERRLOGGER_2_FAULTEN_0 0x00000108
59
+
#define ERRLOGGER_2_ERRVLD_0 0x0000010c
60
+
#define ERRLOGGER_2_ERRCLR_0 0x00000110
61
+
#define ERRLOGGER_2_ERRLOG0_0 0x00000114
62
+
#define ERRLOGGER_2_ERRLOG1_0 0x00000118
63
+
#define ERRLOGGER_2_RSVD_00_0 0x0000011c
64
+
#define ERRLOGGER_2_ERRLOG3_0 0x00000120
65
+
#define ERRLOGGER_2_ERRLOG4_0 0x00000124
66
+
#define ERRLOGGER_2_ERRLOG5_0 0x00000128
67
+
#define ERRLOGGER_2_STALLEN_0 0x00000138
68
+
69
+
#define CBB_NOC_INITFLOW GENMASK(23, 20)
70
+
#define CBB_NOC_TARGFLOW GENMASK(19, 16)
71
+
#define CBB_NOC_TARG_SUBRANGE GENMASK(15, 9)
72
+
#define CBB_NOC_SEQID GENMASK(8, 0)
73
+
74
+
#define BPMP_NOC_INITFLOW GENMASK(20, 18)
75
+
#define BPMP_NOC_TARGFLOW GENMASK(17, 13)
76
+
#define BPMP_NOC_TARG_SUBRANGE GENMASK(12, 9)
77
+
#define BPMP_NOC_SEQID GENMASK(8, 0)
78
+
79
+
#define AON_NOC_INITFLOW GENMASK(22, 21)
80
+
#define AON_NOC_TARGFLOW GENMASK(20, 15)
81
+
#define AON_NOC_TARG_SUBRANGE GENMASK(14, 9)
82
+
#define AON_NOC_SEQID GENMASK(8, 0)
83
+
84
+
#define SCE_NOC_INITFLOW GENMASK(21, 19)
85
+
#define SCE_NOC_TARGFLOW GENMASK(18, 14)
86
+
#define SCE_NOC_TARG_SUBRANGE GENMASK(13, 9)
87
+
#define SCE_NOC_SEQID GENMASK(8, 0)
88
+
89
+
#define CBB_NOC_AXCACHE GENMASK(3, 0)
90
+
#define CBB_NOC_NON_MOD GENMASK(4, 4)
91
+
#define CBB_NOC_AXPROT GENMASK(7, 5)
92
+
#define CBB_NOC_FALCONSEC GENMASK(9, 8)
93
+
#define CBB_NOC_GRPSEC GENMASK(16, 10)
94
+
#define CBB_NOC_VQC GENMASK(18, 17)
95
+
#define CBB_NOC_MSTR_ID GENMASK(22, 19)
96
+
#define CBB_NOC_AXI_ID GENMASK(30, 23)
97
+
98
+
#define CLUSTER_NOC_AXCACHE GENMASK(3, 0)
99
+
#define CLUSTER_NOC_AXPROT GENMASK(6, 4)
100
+
#define CLUSTER_NOC_FALCONSEC GENMASK(8, 7)
101
+
#define CLUSTER_NOC_GRPSEC GENMASK(15, 9)
102
+
#define CLUSTER_NOC_VQC GENMASK(17, 16)
103
+
#define CLUSTER_NOC_MSTR_ID GENMASK(21, 18)
104
+
105
+
#define USRBITS_MSTR_ID GENMASK(21, 18)
106
+
107
+
#define CBB_ERR_OPC GENMASK(4, 1)
108
+
#define CBB_ERR_ERRCODE GENMASK(10, 8)
109
+
#define CBB_ERR_LEN1 GENMASK(27, 16)
110
+
111
+
#define DMAAPB_X_RAW_INTERRUPT_STATUS 0x2ec
112
+
113
+
struct tegra194_cbb_packet_header {
114
+
bool lock; // [0]
115
+
u8 opc; // [4:1]
116
+
u8 errcode; // [10:8]= RD, RDW, RDL, RDX, WR, WRW, WRC, PRE, URG
117
+
u16 len1; // [27:16]
118
+
bool format; // [31] = 1 -> FlexNoC versions 2.7 & above
119
+
};
120
+
121
+
struct tegra194_cbb_aperture {
122
+
u8 initflow;
123
+
u8 targflow;
124
+
u8 targ_subrange;
125
+
u8 init_mapping;
126
+
u32 init_localaddress;
127
+
u8 targ_mapping;
128
+
u32 targ_localaddress;
129
+
u16 seqid;
130
+
};
131
+
132
+
struct tegra194_cbb_userbits {
133
+
u8 axcache;
134
+
u8 non_mod;
135
+
u8 axprot;
136
+
u8 falconsec;
137
+
u8 grpsec;
138
+
u8 vqc;
139
+
u8 mstr_id;
140
+
u8 axi_id;
141
+
};
142
+
143
+
struct tegra194_cbb_noc_data {
144
+
const char *name;
145
+
bool erd_mask_inband_err;
146
+
const char * const *master_id;
147
+
unsigned int max_aperture;
148
+
const struct tegra194_cbb_aperture *noc_aperture;
149
+
const char * const *routeid_initflow;
150
+
const char * const *routeid_targflow;
151
+
void (*parse_routeid)(struct tegra194_cbb_aperture *info, u64 routeid);
152
+
void (*parse_userbits)(struct tegra194_cbb_userbits *usrbits, u32 elog_5);
153
+
};
154
+
155
+
struct tegra194_axi2apb_bridge {
156
+
struct resource res;
157
+
void __iomem *base;
158
+
};
159
+
160
+
struct tegra194_cbb {
161
+
struct tegra_cbb base;
162
+
163
+
const struct tegra194_cbb_noc_data *noc;
164
+
struct resource *res;
165
+
166
+
void __iomem *regs;
167
+
unsigned int num_intr;
168
+
unsigned int sec_irq;
169
+
unsigned int nonsec_irq;
170
+
u32 errlog0;
171
+
u32 errlog1;
172
+
u32 errlog2;
173
+
u32 errlog3;
174
+
u32 errlog4;
175
+
u32 errlog5;
176
+
177
+
struct tegra194_axi2apb_bridge *bridges;
178
+
unsigned int num_bridges;
179
+
};
180
+
181
+
static inline struct tegra194_cbb *to_tegra194_cbb(struct tegra_cbb *cbb)
182
+
{
183
+
return container_of(cbb, struct tegra194_cbb, base);
184
+
}
185
+
186
+
static LIST_HEAD(cbb_list);
187
+
static DEFINE_SPINLOCK(cbb_lock);
188
+
189
+
static const char * const tegra194_cbb_trantype[] = {
190
+
"RD - Read, Incrementing",
191
+
"RDW - Read, Wrap", /* Not Supported */
192
+
"RDX - Exclusive Read", /* Not Supported */
193
+
"RDL - Linked Read", /* Not Supported */
194
+
"WR - Write, Incrementing",
195
+
"WRW - Write, Wrap", /* Not Supported */
196
+
"WRC - Exclusive Write", /* Not Supported */
197
+
"PRE - Preamble Sequence for Fixed Accesses"
198
+
};
199
+
200
+
static const char * const tegra194_axi2apb_error[] = {
201
+
"SFIFONE - Status FIFO Not Empty interrupt",
202
+
"SFIFOF - Status FIFO Full interrupt",
203
+
"TIM - Timer(Timeout) interrupt",
204
+
"SLV - SLVERR interrupt",
205
+
"NULL",
206
+
"ERBF - Early response buffer Full interrupt",
207
+
"NULL",
208
+
"RDFIFOF - Read Response FIFO Full interrupt",
209
+
"WRFIFOF - Write Response FIFO Full interrupt",
210
+
"CH0DFIFOF - Ch0 Data FIFO Full interrupt",
211
+
"CH1DFIFOF - Ch1 Data FIFO Full interrupt",
212
+
"CH2DFIFOF - Ch2 Data FIFO Full interrupt",
213
+
"UAT - Unsupported alignment type error",
214
+
"UBS - Unsupported burst size error",
215
+
"UBE - Unsupported Byte Enable error",
216
+
"UBT - Unsupported burst type error",
217
+
"BFS - Block Firewall security error",
218
+
"ARFS - Address Range Firewall security error",
219
+
"CH0RFIFOF - Ch0 Request FIFO Full interrupt",
220
+
"CH1RFIFOF - Ch1 Request FIFO Full interrupt",
221
+
"CH2RFIFOF - Ch2 Request FIFO Full interrupt"
222
+
};
223
+
224
+
static const char * const tegra194_master_id[] = {
225
+
[0x0] = "CCPLEX",
226
+
[0x1] = "CCPLEX_DPMU",
227
+
[0x2] = "BPMP",
228
+
[0x3] = "AON",
229
+
[0x4] = "SCE",
230
+
[0x5] = "GPCDMA_PERIPHERAL",
231
+
[0x6] = "TSECA",
232
+
[0x7] = "TSECB",
233
+
[0x8] = "JTAGM_DFT",
234
+
[0x9] = "CORESIGHT_AXIAP",
235
+
[0xa] = "APE",
236
+
[0xb] = "PEATR",
237
+
[0xc] = "NVDEC",
238
+
[0xd] = "RCE",
239
+
[0xe] = "NVDEC1"
240
+
};
241
+
242
+
static const struct tegra_cbb_error tegra194_cbb_errors[] = {
243
+
{
244
+
.code = "SLV",
245
+
.source = "Target",
246
+
.desc = "Target error detected by CBB slave"
247
+
}, {
248
+
.code = "DEC",
249
+
.source = "Initiator NIU",
250
+
.desc = "Address decode error"
251
+
}, {
252
+
.code = "UNS",
253
+
.source = "Target NIU",
254
+
.desc = "Unsupported request. Not a valid transaction"
255
+
}, {
256
+
.code = "DISC", /* Not Supported by CBB */
257
+
.source = "Power Disconnect",
258
+
.desc = "Disconnected target or domain"
259
+
}, {
260
+
.code = "SEC",
261
+
.source = "Initiator NIU or Firewall",
262
+
.desc = "Security violation. Firewall error"
263
+
}, {
264
+
.code = "HIDE", /* Not Supported by CBB */
265
+
.source = "Firewall",
266
+
.desc = "Hidden security violation, reported as OK to initiator"
267
+
}, {
268
+
.code = "TMO",
269
+
.source = "Target NIU",
270
+
.desc = "Target time-out error"
271
+
}, {
272
+
.code = "RSV",
273
+
.source = "None",
274
+
.desc = "Reserved"
275
+
}
276
+
};
277
+
278
+
/*
279
+
* CBB NOC aperture lookup table as per file "cbb_central_noc_Structure.info".
280
+
*/
281
+
static const char * const tegra194_cbbcentralnoc_routeid_initflow[] = {
282
+
[0x0] = "aon_p2ps/I/aon",
283
+
[0x1] = "ape_p2ps/I/ape_p2ps",
284
+
[0x2] = "bpmp_p2ps/I/bpmp_p2ps",
285
+
[0x3] = "ccroc_p2ps/I/ccroc_p2ps",
286
+
[0x4] = "csite_p2ps/I/0",
287
+
[0x5] = "gpcdma_mmio_p2ps/I/0",
288
+
[0x6] = "jtag_p2ps/I/0",
289
+
[0x7] = "nvdec1_p2ps/I/0",
290
+
[0x8] = "nvdec_p2ps/I/0",
291
+
[0x9] = "rce_p2ps/I/rce_p2ps",
292
+
[0xa] = "sce_p2ps/I/sce_p2ps",
293
+
[0xb] = "tseca_p2ps/I/0",
294
+
[0xc] = "tsecb_p2ps/I/0",
295
+
[0xd] = "RESERVED",
296
+
[0xe] = "RESERVED",
297
+
[0xf] = "RESERVED"
298
+
};
299
+
300
+
static const char * const tegra194_cbbcentralnoc_routeid_targflow[] = {
301
+
[0x0] = "SVC/T/intreg",
302
+
[0x1] = "axis_satellite_axi2apb_p2pm/T/axis_satellite_axi2apb_p2pm",
303
+
[0x2] = "axis_satellite_grout/T/axis_satellite_grout",
304
+
[0x3] = "cbb_firewall/T/cbb_firewall",
305
+
[0x4] = "gpu_p2pm/T/gpu_p2pm",
306
+
[0x5] = "host1x_p2pm/T/host1x_p2pm",
307
+
[0x6] = "sapb_3_p2pm/T/sapb_3_p2pm",
308
+
[0x7] = "smmu0_p2pm/T/smmu0_p2pm",
309
+
[0x8] = "smmu1_p2pm/T/smmu1_p2pm",
310
+
[0x9] = "smmu2_p2pm/T/smmu2_p2pm",
311
+
[0xa] = "stm_p2pm/T/stm_p2pm",
312
+
[0xb] = "RESERVED",
313
+
[0xc] = "RESERVED",
314
+
[0xd] = "RESERVED",
315
+
[0xe] = "RESERVED",
316
+
[0xf] = "RESERVED"
317
+
};
318
+
319
+
/*
320
+
* Fields of CBB NOC lookup table:
321
+
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
322
+
* Targ mapping, Targ localAddress
323
+
* ----------------------------------------------------------------------------
324
+
*/
325
+
static const struct tegra194_cbb_aperture tegra194_cbbcentralnoc_apert_lookup[] = {
326
+
{ 0x0, 0x0, 0x00, 0x0, 0x02300000, 0, 0x00000000 },
327
+
{ 0x0, 0x1, 0x00, 0x0, 0x02003000, 0, 0x02003000 },
328
+
{ 0x0, 0x1, 0x01, 0x0, 0x02006000, 2, 0x02006000 },
329
+
{ 0x0, 0x1, 0x02, 0x0, 0x02016000, 3, 0x02016000 },
330
+
{ 0x0, 0x1, 0x03, 0x0, 0x0201d000, 4, 0x0201d000 },
331
+
{ 0x0, 0x1, 0x04, 0x0, 0x0202b000, 6, 0x0202b000 },
332
+
{ 0x0, 0x1, 0x05, 0x0, 0x02434000, 20, 0x02434000 },
333
+
{ 0x0, 0x1, 0x06, 0x0, 0x02436000, 21, 0x02436000 },
334
+
{ 0x0, 0x1, 0x07, 0x0, 0x02438000, 22, 0x02438000 },
335
+
{ 0x0, 0x1, 0x08, 0x0, 0x02445000, 24, 0x02445000 },
336
+
{ 0x0, 0x1, 0x09, 0x0, 0x02446000, 25, 0x02446000 },
337
+
{ 0x0, 0x1, 0x0a, 0x0, 0x02004000, 1, 0x02004000 },
338
+
{ 0x0, 0x1, 0x0b, 0x0, 0x0201e000, 5, 0x0201e000 },
339
+
{ 0x0, 0x1, 0x0c, 0x0, 0x0202c000, 7, 0x0202c000 },
340
+
{ 0x0, 0x1, 0x0d, 0x0, 0x02204000, 8, 0x02204000 },
341
+
{ 0x0, 0x1, 0x0e, 0x0, 0x02214000, 9, 0x02214000 },
342
+
{ 0x0, 0x1, 0x0f, 0x0, 0x02224000, 10, 0x02224000 },
343
+
{ 0x0, 0x1, 0x10, 0x0, 0x02234000, 11, 0x02234000 },
344
+
{ 0x0, 0x1, 0x11, 0x0, 0x02244000, 12, 0x02244000 },
345
+
{ 0x0, 0x1, 0x12, 0x0, 0x02254000, 13, 0x02254000 },
346
+
{ 0x0, 0x1, 0x13, 0x0, 0x02264000, 14, 0x02264000 },
347
+
{ 0x0, 0x1, 0x14, 0x0, 0x02274000, 15, 0x02274000 },
348
+
{ 0x0, 0x1, 0x15, 0x0, 0x02284000, 16, 0x02284000 },
349
+
{ 0x0, 0x1, 0x16, 0x0, 0x0243a000, 23, 0x0243a000 },
350
+
{ 0x0, 0x1, 0x17, 0x0, 0x02370000, 17, 0x02370000 },
351
+
{ 0x0, 0x1, 0x18, 0x0, 0x023d0000, 18, 0x023d0000 },
352
+
{ 0x0, 0x1, 0x19, 0x0, 0x023e0000, 19, 0x023e0000 },
353
+
{ 0x0, 0x1, 0x1a, 0x0, 0x02450000, 26, 0x02450000 },
354
+
{ 0x0, 0x1, 0x1b, 0x0, 0x02460000, 27, 0x02460000 },
355
+
{ 0x0, 0x1, 0x1c, 0x0, 0x02490000, 28, 0x02490000 },
356
+
{ 0x0, 0x1, 0x1d, 0x0, 0x03130000, 31, 0x03130000 },
357
+
{ 0x0, 0x1, 0x1e, 0x0, 0x03160000, 32, 0x03160000 },
358
+
{ 0x0, 0x1, 0x1f, 0x0, 0x03270000, 33, 0x03270000 },
359
+
{ 0x0, 0x1, 0x20, 0x0, 0x032e0000, 35, 0x032e0000 },
360
+
{ 0x0, 0x1, 0x21, 0x0, 0x03300000, 36, 0x03300000 },
361
+
{ 0x0, 0x1, 0x22, 0x0, 0x13090000, 40, 0x13090000 },
362
+
{ 0x0, 0x1, 0x23, 0x0, 0x20120000, 43, 0x20120000 },
363
+
{ 0x0, 0x1, 0x24, 0x0, 0x20170000, 44, 0x20170000 },
364
+
{ 0x0, 0x1, 0x25, 0x0, 0x20190000, 45, 0x20190000 },
365
+
{ 0x0, 0x1, 0x26, 0x0, 0x201b0000, 46, 0x201b0000 },
366
+
{ 0x0, 0x1, 0x27, 0x0, 0x20250000, 47, 0x20250000 },
367
+
{ 0x0, 0x1, 0x28, 0x0, 0x20260000, 48, 0x20260000 },
368
+
{ 0x0, 0x1, 0x29, 0x0, 0x20420000, 49, 0x20420000 },
369
+
{ 0x0, 0x1, 0x2a, 0x0, 0x20460000, 50, 0x20460000 },
370
+
{ 0x0, 0x1, 0x2b, 0x0, 0x204f0000, 51, 0x204f0000 },
371
+
{ 0x0, 0x1, 0x2c, 0x0, 0x20520000, 52, 0x20520000 },
372
+
{ 0x0, 0x1, 0x2d, 0x0, 0x20580000, 53, 0x20580000 },
373
+
{ 0x0, 0x1, 0x2e, 0x0, 0x205a0000, 54, 0x205a0000 },
374
+
{ 0x0, 0x1, 0x2f, 0x0, 0x205c0000, 55, 0x205c0000 },
375
+
{ 0x0, 0x1, 0x30, 0x0, 0x20690000, 56, 0x20690000 },
376
+
{ 0x0, 0x1, 0x31, 0x0, 0x20770000, 57, 0x20770000 },
377
+
{ 0x0, 0x1, 0x32, 0x0, 0x20790000, 58, 0x20790000 },
378
+
{ 0x0, 0x1, 0x33, 0x0, 0x20880000, 59, 0x20880000 },
379
+
{ 0x0, 0x1, 0x34, 0x0, 0x20990000, 62, 0x20990000 },
380
+
{ 0x0, 0x1, 0x35, 0x0, 0x20e10000, 65, 0x20e10000 },
381
+
{ 0x0, 0x1, 0x36, 0x0, 0x20e70000, 66, 0x20e70000 },
382
+
{ 0x0, 0x1, 0x37, 0x0, 0x20e80000, 67, 0x20e80000 },
383
+
{ 0x0, 0x1, 0x38, 0x0, 0x20f30000, 68, 0x20f30000 },
384
+
{ 0x0, 0x1, 0x39, 0x0, 0x20f50000, 69, 0x20f50000 },
385
+
{ 0x0, 0x1, 0x3a, 0x0, 0x20fc0000, 70, 0x20fc0000 },
386
+
{ 0x0, 0x1, 0x3b, 0x0, 0x21110000, 72, 0x21110000 },
387
+
{ 0x0, 0x1, 0x3c, 0x0, 0x21270000, 73, 0x21270000 },
388
+
{ 0x0, 0x1, 0x3d, 0x0, 0x21290000, 74, 0x21290000 },
389
+
{ 0x0, 0x1, 0x3e, 0x0, 0x21840000, 75, 0x21840000 },
390
+
{ 0x0, 0x1, 0x3f, 0x0, 0x21880000, 76, 0x21880000 },
391
+
{ 0x0, 0x1, 0x40, 0x0, 0x218d0000, 77, 0x218d0000 },
392
+
{ 0x0, 0x1, 0x41, 0x0, 0x21950000, 78, 0x21950000 },
393
+
{ 0x0, 0x1, 0x42, 0x0, 0x21960000, 79, 0x21960000 },
394
+
{ 0x0, 0x1, 0x43, 0x0, 0x21a10000, 80, 0x21a10000 },
395
+
{ 0x0, 0x1, 0x44, 0x0, 0x024a0000, 29, 0x024a0000 },
396
+
{ 0x0, 0x1, 0x45, 0x0, 0x024c0000, 30, 0x024c0000 },
397
+
{ 0x0, 0x1, 0x46, 0x0, 0x032c0000, 34, 0x032c0000 },
398
+
{ 0x0, 0x1, 0x47, 0x0, 0x03400000, 37, 0x03400000 },
399
+
{ 0x0, 0x1, 0x48, 0x0, 0x130a0000, 41, 0x130a0000 },
400
+
{ 0x0, 0x1, 0x49, 0x0, 0x130c0000, 42, 0x130c0000 },
401
+
{ 0x0, 0x1, 0x4a, 0x0, 0x208a0000, 60, 0x208a0000 },
402
+
{ 0x0, 0x1, 0x4b, 0x0, 0x208c0000, 61, 0x208c0000 },
403
+
{ 0x0, 0x1, 0x4c, 0x0, 0x209a0000, 63, 0x209a0000 },
404
+
{ 0x0, 0x1, 0x4d, 0x0, 0x21a40000, 81, 0x21a40000 },
405
+
{ 0x0, 0x1, 0x4e, 0x0, 0x03440000, 38, 0x03440000 },
406
+
{ 0x0, 0x1, 0x4f, 0x0, 0x20d00000, 64, 0x20d00000 },
407
+
{ 0x0, 0x1, 0x50, 0x0, 0x21000000, 71, 0x21000000 },
408
+
{ 0x0, 0x1, 0x51, 0x0, 0x0b000000, 39, 0x0b000000 },
409
+
{ 0x0, 0x2, 0x00, 0x0, 0x00000000, 0, 0x00000000 },
410
+
{ 0x0, 0x3, 0x00, 0x0, 0x02340000, 0, 0x00000000 },
411
+
{ 0x0, 0x4, 0x00, 0x0, 0x17000000, 0, 0x17000000 },
412
+
{ 0x0, 0x4, 0x01, 0x0, 0x18000000, 1, 0x18000000 },
413
+
{ 0x0, 0x5, 0x00, 0x0, 0x13e80000, 1, 0x13e80000 },
414
+
{ 0x0, 0x5, 0x01, 0x0, 0x15810000, 12, 0x15810000 },
415
+
{ 0x0, 0x5, 0x02, 0x0, 0x15840000, 14, 0x15840000 },
416
+
{ 0x0, 0x5, 0x03, 0x0, 0x15a40000, 17, 0x15a40000 },
417
+
{ 0x0, 0x5, 0x04, 0x0, 0x13f00000, 3, 0x13f00000 },
418
+
{ 0x0, 0x5, 0x05, 0x0, 0x15820000, 13, 0x15820000 },
419
+
{ 0x0, 0x5, 0x06, 0x0, 0x13ec0000, 2, 0x13ec0000 },
420
+
{ 0x0, 0x5, 0x07, 0x0, 0x15200000, 6, 0x15200000 },
421
+
{ 0x0, 0x5, 0x08, 0x0, 0x15340000, 7, 0x15340000 },
422
+
{ 0x0, 0x5, 0x09, 0x0, 0x15380000, 8, 0x15380000 },
423
+
{ 0x0, 0x5, 0x0a, 0x0, 0x15500000, 10, 0x15500000 },
424
+
{ 0x0, 0x5, 0x0b, 0x0, 0x155c0000, 11, 0x155c0000 },
425
+
{ 0x0, 0x5, 0x0c, 0x0, 0x15a00000, 16, 0x15a00000 },
426
+
{ 0x0, 0x5, 0x0d, 0x0, 0x13e00000, 0, 0x13e00000 },
427
+
{ 0x0, 0x5, 0x0e, 0x0, 0x15100000, 5, 0x15100000 },
428
+
{ 0x0, 0x5, 0x0f, 0x0, 0x15480000, 9, 0x15480000 },
429
+
{ 0x0, 0x5, 0x10, 0x0, 0x15880000, 15, 0x15880000 },
430
+
{ 0x0, 0x5, 0x11, 0x0, 0x15a80000, 18, 0x15a80000 },
431
+
{ 0x0, 0x5, 0x12, 0x0, 0x15b00000, 19, 0x15b00000 },
432
+
{ 0x0, 0x5, 0x13, 0x0, 0x14800000, 4, 0x14800000 },
433
+
{ 0x0, 0x5, 0x14, 0x0, 0x15c00000, 20, 0x15c00000 },
434
+
{ 0x0, 0x5, 0x15, 0x0, 0x16000000, 21, 0x16000000 },
435
+
{ 0x0, 0x6, 0x00, 0x0, 0x02000000, 4, 0x02000000 },
436
+
{ 0x0, 0x6, 0x01, 0x0, 0x02007000, 5, 0x02007000 },
437
+
{ 0x0, 0x6, 0x02, 0x0, 0x02008000, 6, 0x02008000 },
438
+
{ 0x0, 0x6, 0x03, 0x0, 0x02013000, 7, 0x02013000 },
439
+
{ 0x0, 0x6, 0x04, 0x0, 0x0201c000, 8, 0x0201c000 },
440
+
{ 0x0, 0x6, 0x05, 0x0, 0x02020000, 9, 0x02020000 },
441
+
{ 0x0, 0x6, 0x06, 0x0, 0x0202a000, 10, 0x0202a000 },
442
+
{ 0x0, 0x6, 0x07, 0x0, 0x0202e000, 11, 0x0202e000 },
443
+
{ 0x0, 0x6, 0x08, 0x0, 0x06400000, 33, 0x06400000 },
444
+
{ 0x0, 0x6, 0x09, 0x0, 0x02038000, 12, 0x02038000 },
445
+
{ 0x0, 0x6, 0x0a, 0x0, 0x00100000, 0, 0x00100000 },
446
+
{ 0x0, 0x6, 0x0b, 0x0, 0x023b0000, 13, 0x023b0000 },
447
+
{ 0x0, 0x6, 0x0c, 0x0, 0x02800000, 16, 0x02800000 },
448
+
{ 0x0, 0x6, 0x0d, 0x0, 0x030e0000, 22, 0x030e0000 },
449
+
{ 0x0, 0x6, 0x0e, 0x0, 0x03800000, 23, 0x03800000 },
450
+
{ 0x0, 0x6, 0x0f, 0x0, 0x03980000, 25, 0x03980000 },
451
+
{ 0x0, 0x6, 0x10, 0x0, 0x03a60000, 26, 0x03a60000 },
452
+
{ 0x0, 0x6, 0x11, 0x0, 0x03d80000, 31, 0x03d80000 },
453
+
{ 0x0, 0x6, 0x12, 0x0, 0x20000000, 36, 0x20000000 },
454
+
{ 0x0, 0x6, 0x13, 0x0, 0x20050000, 38, 0x20050000 },
455
+
{ 0x0, 0x6, 0x14, 0x0, 0x201e0000, 40, 0x201e0000 },
456
+
{ 0x0, 0x6, 0x15, 0x0, 0x20280000, 42, 0x20280000 },
457
+
{ 0x0, 0x6, 0x16, 0x0, 0x202c0000, 43, 0x202c0000 },
458
+
{ 0x0, 0x6, 0x17, 0x0, 0x20390000, 44, 0x20390000 },
459
+
{ 0x0, 0x6, 0x18, 0x0, 0x20430000, 45, 0x20430000 },
460
+
{ 0x0, 0x6, 0x19, 0x0, 0x20440000, 46, 0x20440000 },
461
+
{ 0x0, 0x6, 0x1a, 0x0, 0x204e0000, 47, 0x204e0000 },
462
+
{ 0x0, 0x6, 0x1b, 0x0, 0x20550000, 48, 0x20550000 },
463
+
{ 0x0, 0x6, 0x1c, 0x0, 0x20570000, 49, 0x20570000 },
464
+
{ 0x0, 0x6, 0x1d, 0x0, 0x20590000, 50, 0x20590000 },
465
+
{ 0x0, 0x6, 0x1e, 0x0, 0x20730000, 52, 0x20730000 },
466
+
{ 0x0, 0x6, 0x1f, 0x0, 0x209f0000, 54, 0x209f0000 },
467
+
{ 0x0, 0x6, 0x20, 0x0, 0x20e20000, 55, 0x20e20000 },
468
+
{ 0x0, 0x6, 0x21, 0x0, 0x20ed0000, 56, 0x20ed0000 },
469
+
{ 0x0, 0x6, 0x22, 0x0, 0x20fd0000, 57, 0x20fd0000 },
470
+
{ 0x0, 0x6, 0x23, 0x0, 0x21120000, 59, 0x21120000 },
471
+
{ 0x0, 0x6, 0x24, 0x0, 0x211a0000, 60, 0x211a0000 },
472
+
{ 0x0, 0x6, 0x25, 0x0, 0x21850000, 61, 0x21850000 },
473
+
{ 0x0, 0x6, 0x26, 0x0, 0x21860000, 62, 0x21860000 },
474
+
{ 0x0, 0x6, 0x27, 0x0, 0x21890000, 63, 0x21890000 },
475
+
{ 0x0, 0x6, 0x28, 0x0, 0x21970000, 64, 0x21970000 },
476
+
{ 0x0, 0x6, 0x29, 0x0, 0x21990000, 65, 0x21990000 },
477
+
{ 0x0, 0x6, 0x2a, 0x0, 0x21a00000, 66, 0x21a00000 },
478
+
{ 0x0, 0x6, 0x2b, 0x0, 0x21a90000, 68, 0x21a90000 },
479
+
{ 0x0, 0x6, 0x2c, 0x0, 0x21ac0000, 70, 0x21ac0000 },
480
+
{ 0x0, 0x6, 0x2d, 0x0, 0x01f80000, 3, 0x01f80000 },
481
+
{ 0x0, 0x6, 0x2e, 0x0, 0x024e0000, 14, 0x024e0000 },
482
+
{ 0x0, 0x6, 0x2f, 0x0, 0x030c0000, 21, 0x030c0000 },
483
+
{ 0x0, 0x6, 0x30, 0x0, 0x03820000, 24, 0x03820000 },
484
+
{ 0x0, 0x6, 0x31, 0x0, 0x03aa0000, 27, 0x03aa0000 },
485
+
{ 0x0, 0x6, 0x32, 0x0, 0x03c80000, 29, 0x03c80000 },
486
+
{ 0x0, 0x6, 0x33, 0x0, 0x130e0000, 34, 0x130e0000 },
487
+
{ 0x0, 0x6, 0x34, 0x0, 0x20020000, 37, 0x20020000 },
488
+
{ 0x0, 0x6, 0x35, 0x0, 0x20060000, 39, 0x20060000 },
489
+
{ 0x0, 0x6, 0x36, 0x0, 0x20200000, 41, 0x20200000 },
490
+
{ 0x0, 0x6, 0x37, 0x0, 0x206a0000, 51, 0x206a0000 },
491
+
{ 0x0, 0x6, 0x38, 0x0, 0x20740000, 53, 0x20740000 },
492
+
{ 0x0, 0x6, 0x39, 0x0, 0x20fe0000, 58, 0x20fe0000 },
493
+
{ 0x0, 0x6, 0x3a, 0x0, 0x21a20000, 67, 0x21a20000 },
494
+
{ 0x0, 0x6, 0x3b, 0x0, 0x21aa0000, 69, 0x21aa0000 },
495
+
{ 0x0, 0x6, 0x3c, 0x0, 0x02b80000, 17, 0x02b80000 },
496
+
{ 0x0, 0x6, 0x3d, 0x0, 0x03080000, 20, 0x03080000 },
497
+
{ 0x0, 0x6, 0x3e, 0x0, 0x13100000, 35, 0x13100000 },
498
+
{ 0x0, 0x6, 0x3f, 0x0, 0x01f00000, 2, 0x01f00000 },
499
+
{ 0x0, 0x6, 0x40, 0x0, 0x03000000, 19, 0x03000000 },
500
+
{ 0x0, 0x6, 0x41, 0x0, 0x03c00000, 28, 0x03c00000 },
501
+
{ 0x0, 0x6, 0x42, 0x0, 0x03d00000, 30, 0x03d00000 },
502
+
{ 0x0, 0x6, 0x43, 0x0, 0x01700000, 1, 0x01700000 },
503
+
{ 0x0, 0x6, 0x44, 0x0, 0x02c00000, 18, 0x02c00000 },
504
+
{ 0x0, 0x6, 0x45, 0x0, 0x02600000, 15, 0x02600000 },
505
+
{ 0x0, 0x6, 0x46, 0x0, 0x06000000, 32, 0x06000000 },
506
+
{ 0x0, 0x6, 0x47, 0x0, 0x24000000, 71, 0x24000000 },
507
+
{ 0x0, 0x7, 0x00, 0x0, 0x12000000, 0, 0x12000000 },
508
+
{ 0x0, 0x8, 0x00, 0x0, 0x11000000, 0, 0x11000000 },
509
+
{ 0x0, 0x9, 0x00, 0x0, 0x10000000, 0, 0x10000000 },
510
+
{ 0x0, 0xa, 0x00, 0x0, 0x22000000, 0, 0x22000000 }
511
+
};
512
+
513
+
/*
514
+
* BPMP NOC aperture lookup table as per file "BPMP_NOC_Structure.info".
515
+
*/
516
+
static const char * const tegra194_bpmpnoc_routeid_initflow[] = {
517
+
[0x0] = "cbb_i/I/0",
518
+
[0x1] = "cpu_m_i/I/0",
519
+
[0x2] = "cpu_p_i/I/0",
520
+
[0x3] = "cvc_i/I/0",
521
+
[0x4] = "dma_m_i/I/0",
522
+
[0x5] = "dma_p_i/I/0",
523
+
[0x6] = "RESERVED",
524
+
[0x7] = "RESERVED"
525
+
};
526
+
527
+
static const char * const tegra194_bpmpnoc_routeid_targflow[] = {
528
+
[0x00] = "multiport0_t/T/actmon",
529
+
[0x01] = "multiport0_t/T/ast_0",
530
+
[0x02] = "multiport0_t/T/ast_1",
531
+
[0x03] = "multiport0_t/T/atcm_cfg",
532
+
[0x04] = "multiport0_t/T/car",
533
+
[0x05] = "multiport0_t/T/central_pwr_mgr",
534
+
[0x06] = "multiport0_t/T/central_vtg_ctlr",
535
+
[0x07] = "multiport0_t/T/cfg",
536
+
[0x08] = "multiport0_t/T/dma",
537
+
[0x09] = "multiport0_t/T/err_collator",
538
+
[0x0a] = "multiport0_t/T/err_collator_car",
539
+
[0x0b] = "multiport0_t/T/fpga_misc",
540
+
[0x0c] = "multiport0_t/T/fpga_uart",
541
+
[0x0d] = "multiport0_t/T/gte",
542
+
[0x0e] = "multiport0_t/T/hsp",
543
+
[0x0f] = "multiport0_t/T/misc",
544
+
[0x10] = "multiport0_t/T/pm",
545
+
[0x11] = "multiport0_t/T/simon0",
546
+
[0x12] = "multiport0_t/T/simon1",
547
+
[0x13] = "multiport0_t/T/simon2",
548
+
[0x14] = "multiport0_t/T/simon3",
549
+
[0x15] = "multiport0_t/T/simon4",
550
+
[0x16] = "multiport0_t/T/soc_therm",
551
+
[0x17] = "multiport0_t/T/tke",
552
+
[0x18] = "multiport0_t/T/vic_0",
553
+
[0x19] = "multiport0_t/T/vic_1",
554
+
[0x1a] = "ast0_t/T/0",
555
+
[0x1b] = "ast1_t/T/0",
556
+
[0x1c] = "bpmp_noc_firewall/T/0",
557
+
[0x1d] = "cbb_t/T/0",
558
+
[0x1e] = "cpu_t/T/0",
559
+
[0x1f] = "svc_t/T/0"
560
+
};
561
+
562
+
/*
563
+
* Fields of BPMP NOC lookup table:
564
+
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
565
+
* Targ mapping, Targ localAddress
566
+
* ----------------------------------------------------------------------------
567
+
*/
568
+
static const struct tegra194_cbb_aperture tegra194_bpmpnoc_apert_lookup[] = {
569
+
{ 0x0, 0x1c, 0x0, 0x0, 0x0d640000, 0, 0x00000000 },
570
+
{ 0x0, 0x1e, 0x0, 0x0, 0x0d400000, 0, 0x0d400000 },
571
+
{ 0x0, 0x00, 0x0, 0x0, 0x0d230000, 0, 0x00000000 },
572
+
{ 0x0, 0x01, 0x0, 0x0, 0x0d040000, 0, 0x00000000 },
573
+
{ 0x0, 0x02, 0x0, 0x0, 0x0d050000, 0, 0x00000000 },
574
+
{ 0x0, 0x03, 0x0, 0x0, 0x0d000000, 0, 0x00000000 },
575
+
{ 0x0, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0x000e0000 },
576
+
{ 0x0, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0x000c0000 },
577
+
{ 0x0, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x00080000 },
578
+
{ 0x0, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 },
579
+
{ 0x0, 0x05, 0x0, 0x0, 0x0d2a0000, 0, 0x00000000 },
580
+
{ 0x0, 0x06, 0x0, 0x0, 0x0d290000, 0, 0x00000000 },
581
+
{ 0x0, 0x07, 0x0, 0x0, 0x0d2c0000, 0, 0x00000000 },
582
+
{ 0x0, 0x08, 0x0, 0x0, 0x0d0e0000, 4, 0x00080000 },
583
+
{ 0x0, 0x08, 0x1, 0x0, 0x0d060000, 0, 0x00000000 },
584
+
{ 0x0, 0x08, 0x2, 0x0, 0x0d080000, 1, 0x00020000 },
585
+
{ 0x0, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 },
586
+
{ 0x0, 0x08, 0x4, 0x0, 0x0d0c0000, 3, 0x00060000 },
587
+
{ 0x0, 0x09, 0x0, 0x0, 0x0d650000, 0, 0x00000000 },
588
+
{ 0x0, 0x0a, 0x0, 0x0, 0x20af0000, 0, 0x00000000 },
589
+
{ 0x0, 0x0b, 0x0, 0x0, 0x0d3e0000, 0, 0x00000000 },
590
+
{ 0x0, 0x0c, 0x0, 0x0, 0x0d3d0000, 0, 0x00000000 },
591
+
{ 0x0, 0x0d, 0x0, 0x0, 0x0d1e0000, 0, 0x00000000 },
592
+
{ 0x0, 0x0e, 0x0, 0x0, 0x0d150000, 0, 0x00000000 },
593
+
{ 0x0, 0x0e, 0x1, 0x0, 0x0d160000, 1, 0x00010000 },
594
+
{ 0x0, 0x0e, 0x2, 0x0, 0x0d170000, 2, 0x00020000 },
595
+
{ 0x0, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 },
596
+
{ 0x0, 0x0e, 0x4, 0x0, 0x0d190000, 4, 0x00040000 },
597
+
{ 0x0, 0x0e, 0x5, 0x0, 0x0d1a0000, 5, 0x00050000 },
598
+
{ 0x0, 0x0e, 0x6, 0x0, 0x0d1b0000, 6, 0x00060000 },
599
+
{ 0x0, 0x0e, 0x7, 0x0, 0x0d1c0000, 7, 0x00070000 },
600
+
{ 0x0, 0x0e, 0x8, 0x0, 0x0d1d0000, 8, 0x00080000 },
601
+
{ 0x0, 0x0f, 0x0, 0x0, 0x0d660000, 0, 0x00000000 },
602
+
{ 0x0, 0x10, 0x0, 0x0, 0x0d1f0000, 0, 0x00000000 },
603
+
{ 0x0, 0x10, 0x1, 0x0, 0x0d200000, 1, 0x00010000 },
604
+
{ 0x0, 0x10, 0x2, 0x0, 0x0d210000, 2, 0x00020000 },
605
+
{ 0x0, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 },
606
+
{ 0x0, 0x11, 0x0, 0x0, 0x0d240000, 0, 0x00000000 },
607
+
{ 0x0, 0x12, 0x0, 0x0, 0x0d250000, 0, 0x00000000 },
608
+
{ 0x0, 0x13, 0x0, 0x0, 0x0d260000, 0, 0x00000000 },
609
+
{ 0x0, 0x14, 0x0, 0x0, 0x0d270000, 0, 0x00000000 },
610
+
{ 0x0, 0x15, 0x0, 0x0, 0x0d2b0000, 0, 0x00000000 },
611
+
{ 0x0, 0x16, 0x0, 0x0, 0x0d280000, 0, 0x00000000 },
612
+
{ 0x0, 0x17, 0x0, 0x0, 0x0d0f0000, 0, 0x00000000 },
613
+
{ 0x0, 0x17, 0x1, 0x0, 0x0d100000, 1, 0x00010000 },
614
+
{ 0x0, 0x17, 0x2, 0x0, 0x0d110000, 2, 0x00020000 },
615
+
{ 0x0, 0x17, 0x3, 0x0, 0x0d120000, 3, 0x00030000 },
616
+
{ 0x0, 0x17, 0x4, 0x0, 0x0d130000, 4, 0x00040000 },
617
+
{ 0x0, 0x17, 0x5, 0x0, 0x0d140000, 5, 0x00050000 },
618
+
{ 0x0, 0x18, 0x0, 0x0, 0x0d020000, 0, 0x00000000 },
619
+
{ 0x0, 0x19, 0x0, 0x0, 0x0d030000, 0, 0x00000000 },
620
+
{ 0x0, 0x1f, 0x0, 0x0, 0x0d600000, 0, 0x00000000 },
621
+
{ 0x0, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
622
+
{ 0x1, 0x1a, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
623
+
{ 0x1, 0x1a, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
624
+
{ 0x1, 0x1a, 0x2, 0x0, 0x00000000, 0, 0x00000000 },
625
+
{ 0x2, 0x1c, 0x0, 0x0, 0x0d640000, 0, 0x00000000 },
626
+
{ 0x2, 0x1d, 0x0, 0x0, 0x20b00000, 8, 0x20b00000 },
627
+
{ 0x2, 0x1d, 0x1, 0x0, 0x20800000, 7, 0x20800000 },
628
+
{ 0x2, 0x1d, 0x2, 0x0, 0x20c00000, 9, 0x20c00000 },
629
+
{ 0x2, 0x1d, 0x3, 0x0, 0x0d800000, 3, 0x0d800000 },
630
+
{ 0x2, 0x1d, 0x4, 0x0, 0x20000000, 6, 0x20000000 },
631
+
{ 0x2, 0x1d, 0x5, 0x0, 0x0c000000, 2, 0x0c000000 },
632
+
{ 0x2, 0x1d, 0x6, 0x0, 0x21000000, 10, 0x21000000 },
633
+
{ 0x2, 0x1d, 0x7, 0x0, 0x0e000000, 4, 0x0e000000 },
634
+
{ 0x2, 0x1d, 0x8, 0x0, 0x22000000, 11, 0x22000000 },
635
+
{ 0x2, 0x1d, 0x9, 0x0, 0x08000000, 1, 0x08000000 },
636
+
{ 0x2, 0x1d, 0xa, 0x0, 0x24000000, 12, 0x24000000 },
637
+
{ 0x2, 0x1d, 0xb, 0x0, 0x00000000, 0, 0x00000000 },
638
+
{ 0x2, 0x1d, 0xc, 0x0, 0x28000000, 13, 0x28000000 },
639
+
{ 0x2, 0x1d, 0xd, 0x0, 0x10000000, 5, 0x10000000 },
640
+
{ 0x2, 0x1d, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
641
+
{ 0x2, 0x00, 0x0, 0x0, 0x0d230000, 0, 0x00000000 },
642
+
{ 0x2, 0x01, 0x0, 0x0, 0x0d040000, 0, 0x00000000 },
643
+
{ 0x2, 0x02, 0x0, 0x0, 0x0d050000, 0, 0x00000000 },
644
+
{ 0x2, 0x03, 0x0, 0x0, 0x0d000000, 0, 0x00000000 },
645
+
{ 0x2, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0x000e0000 },
646
+
{ 0x2, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0x000c0000 },
647
+
{ 0x2, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x00080000 },
648
+
{ 0x2, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 },
649
+
{ 0x2, 0x05, 0x0, 0x0, 0x0d2a0000, 0, 0x00000000 },
650
+
{ 0x2, 0x06, 0x0, 0x0, 0x0d290000, 0, 0x00000000 },
651
+
{ 0x2, 0x07, 0x0, 0x0, 0x0d2c0000, 0, 0x00000000 },
652
+
{ 0x2, 0x08, 0x0, 0x0, 0x0d0e0000, 4, 0x00080000 },
653
+
{ 0x2, 0x08, 0x1, 0x0, 0x0d060000, 0, 0x00000000 },
654
+
{ 0x2, 0x08, 0x2, 0x0, 0x0d080000, 1, 0x00020000 },
655
+
{ 0x2, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 },
656
+
{ 0x2, 0x08, 0x4, 0x0, 0x0d0c0000, 3, 0x00060000 },
657
+
{ 0x2, 0x09, 0x0, 0x0, 0x0d650000, 0, 0x00000000 },
658
+
{ 0x2, 0x0a, 0x0, 0x0, 0x20af0000, 0, 0x00000000 },
659
+
{ 0x2, 0x0b, 0x0, 0x0, 0x0d3e0000, 0, 0x00000000 },
660
+
{ 0x2, 0x0c, 0x0, 0x0, 0x0d3d0000, 0, 0x00000000 },
661
+
{ 0x2, 0x0d, 0x0, 0x0, 0x0d1e0000, 0, 0x00000000 },
662
+
{ 0x2, 0x0e, 0x0, 0x0, 0x0d150000, 0, 0x00000000 },
663
+
{ 0x2, 0x0e, 0x1, 0x0, 0x0d160000, 1, 0x00010000 },
664
+
{ 0x2, 0x0e, 0x2, 0x0, 0x0d170000, 2, 0x00020000 },
665
+
{ 0x2, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 },
666
+
{ 0x2, 0x0e, 0x4, 0x0, 0x0d190000, 4, 0x00040000 },
667
+
{ 0x2, 0x0e, 0x5, 0x0, 0x0d1a0000, 5, 0x00050000 },
668
+
{ 0x2, 0x0e, 0x6, 0x0, 0x0d1b0000, 6, 0x00060000 },
669
+
{ 0x2, 0x0e, 0x7, 0x0, 0x0d1c0000, 7, 0x00070000 },
670
+
{ 0x2, 0x0e, 0x8, 0x0, 0x0d1d0000, 8, 0x00080000 },
671
+
{ 0x2, 0x0f, 0x0, 0x0, 0x0d660000, 0, 0x00000000 },
672
+
{ 0x2, 0x10, 0x0, 0x0, 0x0d1f0000, 0, 0x00000000 },
673
+
{ 0x2, 0x10, 0x1, 0x0, 0x0d200000, 1, 0x00010000 },
674
+
{ 0x2, 0x10, 0x2, 0x0, 0x0d210000, 2, 0x00020000 },
675
+
{ 0x2, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 },
676
+
{ 0x2, 0x11, 0x0, 0x0, 0x0d240000, 0, 0x00000000 },
677
+
{ 0x2, 0x12, 0x0, 0x0, 0x0d250000, 0, 0x00000000 },
678
+
{ 0x2, 0x13, 0x0, 0x0, 0x0d260000, 0, 0x00000000 },
679
+
{ 0x2, 0x14, 0x0, 0x0, 0x0d270000, 0, 0x00000000 },
680
+
{ 0x2, 0x15, 0x0, 0x0, 0x0d2b0000, 0, 0x00000000 },
681
+
{ 0x2, 0x16, 0x0, 0x0, 0x0d280000, 0, 0x00000000 },
682
+
{ 0x2, 0x17, 0x0, 0x0, 0x0d0f0000, 0, 0x00000000 },
683
+
{ 0x2, 0x17, 0x1, 0x0, 0x0d100000, 1, 0x00010000 },
684
+
{ 0x2, 0x17, 0x2, 0x0, 0x0d110000, 2, 0x00020000 },
685
+
{ 0x2, 0x17, 0x3, 0x0, 0x0d120000, 3, 0x00030000 },
686
+
{ 0x2, 0x17, 0x4, 0x0, 0x0d130000, 4, 0x00040000 },
687
+
{ 0x2, 0x17, 0x5, 0x0, 0x0d140000, 5, 0x00050000 },
688
+
{ 0x2, 0x18, 0x0, 0x0, 0x0d020000, 0, 0x00000000 },
689
+
{ 0x2, 0x19, 0x0, 0x0, 0x0d030000, 0, 0x00000000 },
690
+
{ 0x2, 0x1f, 0x0, 0x0, 0x0d600000, 0, 0x00000000 },
691
+
{ 0x2, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
692
+
{ 0x3, 0x1b, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
693
+
{ 0x3, 0x1b, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
694
+
{ 0x3, 0x1c, 0x0, 0x2, 0x0d640000, 0, 0x00000000 },
695
+
{ 0x3, 0x1d, 0x0, 0x2, 0x20b00000, 8, 0x20b00000 },
696
+
{ 0x3, 0x1d, 0x1, 0x2, 0x20800000, 7, 0x20800000 },
697
+
{ 0x3, 0x1d, 0x2, 0x2, 0x20c00000, 9, 0x20c00000 },
698
+
{ 0x3, 0x1d, 0x3, 0x2, 0x0d800000, 3, 0x0d800000 },
699
+
{ 0x3, 0x1d, 0x4, 0x2, 0x20000000, 6, 0x20000000 },
700
+
{ 0x3, 0x1d, 0x5, 0x2, 0x0c000000, 2, 0x0c000000 },
701
+
{ 0x3, 0x1d, 0x6, 0x2, 0x21000000, 10, 0x21000000 },
702
+
{ 0x3, 0x1d, 0x7, 0x2, 0x0e000000, 4, 0x0e000000 },
703
+
{ 0x3, 0x1d, 0x8, 0x2, 0x22000000, 11, 0x22000000 },
704
+
{ 0x3, 0x1d, 0x9, 0x2, 0x08000000, 1, 0x08000000 },
705
+
{ 0x3, 0x1d, 0xa, 0x2, 0x24000000, 12, 0x24000000 },
706
+
{ 0x3, 0x1d, 0xb, 0x2, 0x00000000, 0, 0x00000000 },
707
+
{ 0x3, 0x1d, 0xc, 0x2, 0x28000000, 13, 0x28000000 },
708
+
{ 0x3, 0x1d, 0xd, 0x2, 0x10000000, 5, 0x10000000 },
709
+
{ 0x3, 0x1d, 0xe, 0x2, 0x30000000, 14, 0x30000000 },
710
+
{ 0x3, 0x1e, 0x0, 0x2, 0x0d400000, 0, 0x0d400000 },
711
+
{ 0x3, 0x00, 0x0, 0x2, 0x0d230000, 0, 0x00000000 },
712
+
{ 0x3, 0x01, 0x0, 0x2, 0x0d040000, 0, 0x00000000 },
713
+
{ 0x3, 0x02, 0x0, 0x2, 0x0d050000, 0, 0x00000000 },
714
+
{ 0x3, 0x03, 0x0, 0x2, 0x0d000000, 0, 0x00000000 },
715
+
{ 0x3, 0x04, 0x0, 0x2, 0x20ae0000, 3, 0x000e0000 },
716
+
{ 0x3, 0x04, 0x1, 0x2, 0x20ac0000, 2, 0x000c0000 },
717
+
{ 0x3, 0x04, 0x2, 0x2, 0x20a80000, 1, 0x00080000 },
718
+
{ 0x3, 0x04, 0x3, 0x2, 0x20a00000, 0, 0x00000000 },
719
+
{ 0x3, 0x05, 0x0, 0x2, 0x0d2a0000, 0, 0x00000000 },
720
+
{ 0x3, 0x06, 0x0, 0x2, 0x0d290000, 0, 0x00000000 },
721
+
{ 0x3, 0x07, 0x0, 0x2, 0x0d2c0000, 0, 0x00000000 },
722
+
{ 0x3, 0x08, 0x0, 0x2, 0x0d0e0000, 4, 0x00080000 },
723
+
{ 0x3, 0x08, 0x1, 0x2, 0x0d060000, 0, 0x00000000 },
724
+
{ 0x3, 0x08, 0x2, 0x2, 0x0d080000, 1, 0x00020000 },
725
+
{ 0x3, 0x08, 0x3, 0x2, 0x0d0a0000, 2, 0x00040000 },
726
+
{ 0x3, 0x08, 0x4, 0x2, 0x0d0c0000, 3, 0x00060000 },
727
+
{ 0x3, 0x09, 0x0, 0x2, 0x0d650000, 0, 0x00000000 },
728
+
{ 0x3, 0x0a, 0x0, 0x2, 0x20af0000, 0, 0x00000000 },
729
+
{ 0x3, 0x0b, 0x0, 0x2, 0x0d3e0000, 0, 0x00000000 },
730
+
{ 0x3, 0x0c, 0x0, 0x2, 0x0d3d0000, 0, 0x00000000 },
731
+
{ 0x3, 0x0d, 0x0, 0x2, 0x0d1e0000, 0, 0x00000000 },
732
+
{ 0x3, 0x0e, 0x0, 0x2, 0x0d150000, 0, 0x00000000 },
733
+
{ 0x3, 0x0e, 0x1, 0x2, 0x0d160000, 1, 0x00010000 },
734
+
{ 0x3, 0x0e, 0x2, 0x2, 0x0d170000, 2, 0x00020000 },
735
+
{ 0x3, 0x0e, 0x3, 0x2, 0x0d180000, 3, 0x00030000 },
736
+
{ 0x3, 0x0e, 0x4, 0x2, 0x0d190000, 4, 0x00040000 },
737
+
{ 0x3, 0x0e, 0x5, 0x2, 0x0d1a0000, 5, 0x00050000 },
738
+
{ 0x3, 0x0e, 0x6, 0x2, 0x0d1b0000, 6, 0x00060000 },
739
+
{ 0x3, 0x0e, 0x7, 0x2, 0x0d1c0000, 7, 0x00070000 },
740
+
{ 0x3, 0x0e, 0x8, 0x2, 0x0d1d0000, 8, 0x00080000 },
741
+
{ 0x3, 0x0f, 0x0, 0x2, 0x0d660000, 0, 0x00000000 },
742
+
{ 0x3, 0x10, 0x0, 0x2, 0x0d1f0000, 0, 0x00000000 },
743
+
{ 0x3, 0x10, 0x1, 0x2, 0x0d200000, 1, 0x00010000 },
744
+
{ 0x3, 0x10, 0x2, 0x2, 0x0d210000, 2, 0x00020000 },
745
+
{ 0x3, 0x10, 0x3, 0x2, 0x0d220000, 3, 0x00030000 },
746
+
{ 0x3, 0x11, 0x0, 0x2, 0x0d240000, 0, 0x00000000 },
747
+
{ 0x3, 0x12, 0x0, 0x2, 0x0d250000, 0, 0x00000000 },
748
+
{ 0x3, 0x13, 0x0, 0x2, 0x0d260000, 0, 0x00000000 },
749
+
{ 0x3, 0x14, 0x0, 0x2, 0x0d270000, 0, 0x00000000 },
750
+
{ 0x3, 0x15, 0x0, 0x2, 0x0d2b0000, 0, 0x00000000 },
751
+
{ 0x3, 0x16, 0x0, 0x2, 0x0d280000, 0, 0x00000000 },
752
+
{ 0x3, 0x17, 0x0, 0x2, 0x0d0f0000, 0, 0x00000000 },
753
+
{ 0x3, 0x17, 0x1, 0x2, 0x0d100000, 1, 0x00010000 },
754
+
{ 0x3, 0x17, 0x2, 0x2, 0x0d110000, 2, 0x00020000 },
755
+
{ 0x3, 0x17, 0x3, 0x2, 0x0d120000, 3, 0x00030000 },
756
+
{ 0x3, 0x17, 0x4, 0x2, 0x0d130000, 4, 0x00040000 },
757
+
{ 0x3, 0x17, 0x5, 0x2, 0x0d140000, 5, 0x00050000 },
758
+
{ 0x3, 0x18, 0x0, 0x2, 0x0d020000, 0, 0x00000000 },
759
+
{ 0x3, 0x19, 0x0, 0x2, 0x0d030000, 0, 0x00000000 },
760
+
{ 0x3, 0x1f, 0x0, 0x2, 0x0d600000, 0, 0x00000000 },
761
+
{ 0x3, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
762
+
{ 0x4, 0x1b, 0x0, 0x0, 0x40000000, 0, 0x40000000 },
763
+
{ 0x4, 0x1b, 0x1, 0x1, 0x80000000, 1, 0x80000000 },
764
+
{ 0x4, 0x1e, 0x0, 0x2, 0x0d400000, 0, 0x0d400000 },
765
+
{ 0x4, 0x1e, 0x1, 0x0, 0x00000000, 0, 0x00000000 },
766
+
{ 0x5, 0x1c, 0x0, 0x0, 0x0d640000, 0, 0x00000000 },
767
+
{ 0x5, 0x1d, 0x0, 0x0, 0x20b00000, 8, 0x20b00000 },
768
+
{ 0x5, 0x1d, 0x1, 0x0, 0x20800000, 7, 0x20800000 },
769
+
{ 0x5, 0x1d, 0x2, 0x0, 0x20c00000, 9, 0x20c00000 },
770
+
{ 0x5, 0x1d, 0x3, 0x0, 0x0d800000, 3, 0x0d800000 },
771
+
{ 0x5, 0x1d, 0x4, 0x0, 0x20000000, 6, 0x20000000 },
772
+
{ 0x5, 0x1d, 0x5, 0x0, 0x0c000000, 2, 0x0c000000 },
773
+
{ 0x5, 0x1d, 0x6, 0x0, 0x21000000, 10, 0x21000000 },
774
+
{ 0x5, 0x1d, 0x7, 0x0, 0x0e000000, 4, 0x0e000000 },
775
+
{ 0x5, 0x1d, 0x8, 0x0, 0x22000000, 11, 0x22000000 },
776
+
{ 0x5, 0x1d, 0x9, 0x0, 0x08000000, 1, 0x08000000 },
777
+
{ 0x5, 0x1d, 0xa, 0x0, 0x24000000, 12, 0x24000000 },
778
+
{ 0x5, 0x1d, 0xb, 0x0, 0x00000000, 0, 0x00000000 },
779
+
{ 0x5, 0x1d, 0xc, 0x0, 0x28000000, 13, 0x28000000 },
780
+
{ 0x5, 0x1d, 0xd, 0x0, 0x10000000, 5, 0x10000000 },
781
+
{ 0x5, 0x1d, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
782
+
{ 0x5, 0x00, 0x0, 0x0, 0x0d230000, 0, 0x00000000 },
783
+
{ 0x5, 0x01, 0x0, 0x0, 0x0d040000, 0, 0x00000000 },
784
+
{ 0x5, 0x02, 0x0, 0x0, 0x0d050000, 0, 0x00000000 },
785
+
{ 0x5, 0x03, 0x0, 0x0, 0x0d000000, 0, 0x00000000 },
786
+
{ 0x5, 0x04, 0x0, 0x0, 0x20ae0000, 3, 0x000e0000 },
787
+
{ 0x5, 0x04, 0x1, 0x0, 0x20ac0000, 2, 0x000c0000 },
788
+
{ 0x5, 0x04, 0x2, 0x0, 0x20a80000, 1, 0x00080000 },
789
+
{ 0x5, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 },
790
+
{ 0x5, 0x05, 0x0, 0x0, 0x0d2a0000, 0, 0x00000000 },
791
+
{ 0x5, 0x06, 0x0, 0x0, 0x0d290000, 0, 0x00000000 },
792
+
{ 0x5, 0x07, 0x0, 0x0, 0x0d2c0000, 0, 0x00000000 },
793
+
{ 0x5, 0x08, 0x0, 0x0, 0x0d0e0000, 4, 0x00080000 },
794
+
{ 0x5, 0x08, 0x1, 0x0, 0x0d060000, 0, 0x00000000 },
795
+
{ 0x5, 0x08, 0x2, 0x0, 0x0d080000, 1, 0x00020000 },
796
+
{ 0x5, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 },
797
+
{ 0x5, 0x08, 0x4, 0x0, 0x0d0c0000, 3, 0x00060000 },
798
+
{ 0x5, 0x09, 0x0, 0x0, 0x0d650000, 0, 0x00000000 },
799
+
{ 0x5, 0x0a, 0x0, 0x0, 0x20af0000, 0, 0x00000000 },
800
+
{ 0x5, 0x0b, 0x0, 0x0, 0x0d3e0000, 0, 0x00000000 },
801
+
{ 0x5, 0x0c, 0x0, 0x0, 0x0d3d0000, 0, 0x00000000 },
802
+
{ 0x5, 0x0d, 0x0, 0x0, 0x0d1e0000, 0, 0x00000000 },
803
+
{ 0x5, 0x0e, 0x0, 0x0, 0x0d150000, 0, 0x00000000 },
804
+
{ 0x5, 0x0e, 0x1, 0x0, 0x0d160000, 1, 0x00010000 },
805
+
{ 0x5, 0x0e, 0x2, 0x0, 0x0d170000, 2, 0x00020000 },
806
+
{ 0x5, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 },
807
+
{ 0x5, 0x0e, 0x4, 0x0, 0x0d190000, 4, 0x00040000 },
808
+
{ 0x5, 0x0e, 0x5, 0x0, 0x0d1a0000, 5, 0x00050000 },
809
+
{ 0x5, 0x0e, 0x6, 0x0, 0x0d1b0000, 6, 0x00060000 },
810
+
{ 0x5, 0x0e, 0x7, 0x0, 0x0d1c0000, 7, 0x00070000 },
811
+
{ 0x5, 0x0e, 0x8, 0x0, 0x0d1d0000, 8, 0x00080000 },
812
+
{ 0x5, 0x0f, 0x0, 0x0, 0x0d660000, 0, 0x00000000 },
813
+
{ 0x5, 0x10, 0x0, 0x0, 0x0d1f0000, 0, 0x00000000 },
814
+
{ 0x5, 0x10, 0x1, 0x0, 0x0d200000, 1, 0x00010000 },
815
+
{ 0x5, 0x10, 0x2, 0x0, 0x0d210000, 2, 0x00020000 },
816
+
{ 0x5, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 },
817
+
{ 0x5, 0x11, 0x0, 0x0, 0x0d240000, 0, 0x00000000 },
818
+
{ 0x5, 0x12, 0x0, 0x0, 0x0d250000, 0, 0x00000000 },
819
+
{ 0x5, 0x13, 0x0, 0x0, 0x0d260000, 0, 0x00000000 },
820
+
{ 0x5, 0x14, 0x0, 0x0, 0x0d270000, 0, 0x00000000 },
821
+
{ 0x5, 0x15, 0x0, 0x0, 0x0d2b0000, 0, 0x00000000 },
822
+
{ 0x5, 0x16, 0x0, 0x0, 0x0d280000, 0, 0x00000000 },
823
+
{ 0x5, 0x17, 0x0, 0x0, 0x0d0f0000, 0, 0x00000000 },
824
+
{ 0x5, 0x17, 0x1, 0x0, 0x0d100000, 1, 0x00010000 },
825
+
{ 0x5, 0x17, 0x2, 0x0, 0x0d110000, 2, 0x00020000 },
826
+
{ 0x5, 0x17, 0x3, 0x0, 0x0d120000, 3, 0x00030000 },
827
+
{ 0x5, 0x17, 0x4, 0x0, 0x0d130000, 4, 0x00040000 },
828
+
{ 0x5, 0x17, 0x5, 0x0, 0x0d140000, 5, 0x00050000 },
829
+
{ 0x5, 0x18, 0x0, 0x0, 0x0d020000, 0, 0x00000000 },
830
+
{ 0x5, 0x19, 0x0, 0x0, 0x0d030000, 0, 0x00000000 },
831
+
{ 0x5, 0x1f, 0x0, 0x0, 0x0d600000, 0, 0x00000000 },
832
+
{ 0x5, 0x1f, 0x1, 0x0, 0x00000000, 0, 0x00000000 }
833
+
};
834
+
835
+
/*
836
+
* AON NOC aperture lookup table as per file "AON_NOC_Structure.info".
837
+
*/
838
+
static const char * const tegra194_aonnoc_routeid_initflow[] = {
839
+
[0x0] = "cbb_i/I/0",
840
+
[0x1] = "cpu_p_i/I/0",
841
+
[0x2] = "dma_m_i/I/0",
842
+
[0x3] = "dma_p_i/I/0"
843
+
};
844
+
845
+
static const char * const tegra194_aonnoc_routeid_targflow[] = {
846
+
[0x00] = "multiport1_t/T/aon_misc",
847
+
[0x01] = "multiport1_t/T/avic0",
848
+
[0x02] = "multiport1_t/T/avic1",
849
+
[0x03] = "multiport1_t/T/can1",
850
+
[0x04] = "multiport1_t/T/can2",
851
+
[0x05] = "multiport1_t/T/dma",
852
+
[0x06] = "multiport1_t/T/dmic",
853
+
[0x07] = "multiport1_t/T/err_collator",
854
+
[0x08] = "multiport1_t/T/fpga_misc",
855
+
[0x09] = "multiport1_t/T/gte",
856
+
[0x0a] = "multiport1_t/T/hsp",
857
+
[0x0b] = "multiport1_t/T/i2c2",
858
+
[0x0c] = "multiport1_t/T/i2c8",
859
+
[0x0d] = "multiport1_t/T/pwm",
860
+
[0x0e] = "multiport1_t/T/spi2",
861
+
[0x0f] = "multiport1_t/T/tke",
862
+
[0x10] = "multiport1_t/T/uartg",
863
+
[0x11] = "RESERVED",
864
+
[0x12] = "RESERVED",
865
+
[0x13] = "RESERVED",
866
+
[0x14] = "RESERVED",
867
+
[0x15] = "RESERVED",
868
+
[0x16] = "RESERVED",
869
+
[0x17] = "RESERVED",
870
+
[0x18] = "RESERVED",
871
+
[0x19] = "RESERVED",
872
+
[0x1a] = "RESERVED",
873
+
[0x1b] = "RESERVED",
874
+
[0x1c] = "RESERVED",
875
+
[0x1d] = "RESERVED",
876
+
[0x1e] = "RESERVED",
877
+
[0x1f] = "RESERVED",
878
+
[0x20] = "multiport0_t/T/aovc",
879
+
[0x21] = "multiport0_t/T/atcm",
880
+
[0x22] = "multiport0_t/T/cast",
881
+
[0x23] = "multiport0_t/T/dast",
882
+
[0x24] = "multiport0_t/T/err_collator_car",
883
+
[0x25] = "multiport0_t/T/gpio",
884
+
[0x26] = "multiport0_t/T/i2c10",
885
+
[0x27] = "multiport0_t/T/mss",
886
+
[0x28] = "multiport0_t/T/padctl_a12",
887
+
[0x29] = "multiport0_t/T/padctl_a14",
888
+
[0x2a] = "multiport0_t/T/padctl_a15",
889
+
[0x2b] = "multiport0_t/T/rtc",
890
+
[0x2c] = "multiport0_t/T/tsc",
891
+
[0x2d] = "RESERVED",
892
+
[0x2e] = "RESERVED",
893
+
[0x2f] = "RESERVED",
894
+
[0x30] = "multiport2_t/T/aon_vref_ro",
895
+
[0x31] = "multiport2_t/T/aopm",
896
+
[0x32] = "multiport2_t/T/car",
897
+
[0x33] = "multiport2_t/T/pmc",
898
+
[0x34] = "ast1_t/T/0",
899
+
[0x35] = "cbb_t/T/0",
900
+
[0x36] = "cpu_t/T/0",
901
+
[0x37] = "firewall_t/T/0",
902
+
[0x38] = "svc_t/T/0",
903
+
[0x39] = "uartc/T/uartc",
904
+
[0x3a] = "RESERVED",
905
+
[0x3b] = "RESERVED",
906
+
[0x3c] = "RESERVED",
907
+
[0x3d] = "RESERVED",
908
+
[0x3e] = "RESERVED",
909
+
[0x3f] = "RESERVED"
910
+
};
911
+
912
+
/*
913
+
* Fields of AON NOC lookup table:
914
+
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
915
+
* Targ mapping, Targ localAddress
916
+
* ----------------------------------------------------------------------------
917
+
*/
918
+
static const struct tegra194_cbb_aperture tegra194_aonnoc_aperture_lookup[] = {
919
+
{ 0x0, 0x37, 0x00, 0, 0x0c640000, 0, 0x00000000 },
920
+
{ 0x0, 0x20, 0x00, 0, 0x0c3b0000, 0, 0x00000000 },
921
+
{ 0x0, 0x21, 0x00, 0, 0x0c000000, 0, 0x00000000 },
922
+
{ 0x0, 0x22, 0x00, 0, 0x0c040000, 0, 0x00000000 },
923
+
{ 0x0, 0x23, 0x00, 0, 0x0c050000, 0, 0x00000000 },
924
+
{ 0x0, 0x24, 0x00, 0, 0x20cf0000, 0, 0x00000000 },
925
+
{ 0x0, 0x25, 0x00, 0, 0x0c2f0000, 0, 0x00000000 },
926
+
{ 0x0, 0x26, 0x00, 0, 0x0c230000, 0, 0x00000000 },
927
+
{ 0x0, 0x27, 0x00, 0, 0x0c350000, 0, 0x00000000 },
928
+
{ 0x0, 0x28, 0x00, 0, 0x0c301000, 0, 0x00000000 },
929
+
{ 0x0, 0x29, 0x00, 0, 0x0c302000, 0, 0x00000000 },
930
+
{ 0x0, 0x2a, 0x00, 0, 0x0c303000, 0, 0x00000000 },
931
+
{ 0x0, 0x2b, 0x00, 0, 0x0c2a0000, 0, 0x00000000 },
932
+
{ 0x0, 0x2c, 0x00, 0, 0x0c2b0000, 0, 0x00000000 },
933
+
{ 0x0, 0x2c, 0x01, 0, 0x0c2c0000, 1, 0x00010000 },
934
+
{ 0x0, 0x2c, 0x02, 0, 0x0c2d0000, 2, 0x00020000 },
935
+
{ 0x0, 0x2c, 0x03, 0, 0x0c2e0000, 3, 0x00030000 },
936
+
{ 0x0, 0x00, 0x00, 0, 0x0c660000, 0, 0x00000000 },
937
+
{ 0x0, 0x01, 0x00, 0, 0x0c020000, 0, 0x00000000 },
938
+
{ 0x0, 0x02, 0x00, 0, 0x0c030000, 0, 0x00000000 },
939
+
{ 0x0, 0x03, 0x00, 0, 0x0c310000, 0, 0x00000000 },
940
+
{ 0x0, 0x04, 0x00, 0, 0x0c320000, 0, 0x00000000 },
941
+
{ 0x0, 0x05, 0x00, 0, 0x0c0a0000, 2, 0x00040000 },
942
+
{ 0x0, 0x05, 0x01, 0, 0x0c0b0000, 3, 0x00050000 },
943
+
{ 0x0, 0x05, 0x02, 0, 0x0c0e0000, 5, 0x00080000 },
944
+
{ 0x0, 0x05, 0x03, 0, 0x0c060000, 0, 0x00000000 },
945
+
{ 0x0, 0x05, 0x04, 0, 0x0c080000, 1, 0x00020000 },
946
+
{ 0x0, 0x05, 0x05, 0, 0x0c0c0000, 4, 0x00060000 },
947
+
{ 0x0, 0x06, 0x00, 0, 0x0c330000, 0, 0x00000000 },
948
+
{ 0x0, 0x07, 0x00, 0, 0x0c650000, 0, 0x00000000 },
949
+
{ 0x0, 0x08, 0x00, 0, 0x0c3e0000, 0, 0x00000000 },
950
+
{ 0x0, 0x09, 0x00, 0, 0x0c1e0000, 0, 0x00000000 },
951
+
{ 0x0, 0x0a, 0x00, 0, 0x0c150000, 0, 0x00000000 },
952
+
{ 0x0, 0x0a, 0x01, 0, 0x0c160000, 1, 0x00010000 },
953
+
{ 0x0, 0x0a, 0x02, 0, 0x0c170000, 2, 0x00020000 },
954
+
{ 0x0, 0x0a, 0x03, 0, 0x0c180000, 3, 0x00030000 },
955
+
{ 0x0, 0x0a, 0x04, 0, 0x0c190000, 4, 0x00040000 },
956
+
{ 0x0, 0x0a, 0x05, 0, 0x0c1a0000, 5, 0x00050000 },
957
+
{ 0x0, 0x0a, 0x06, 0, 0x0c1b0000, 6, 0x00060000 },
958
+
{ 0x0, 0x0a, 0x07, 0, 0x0c1c0000, 7, 0x00070000 },
959
+
{ 0x0, 0x0a, 0x08, 0, 0x0c1d0000, 8, 0x00080000 },
960
+
{ 0x0, 0x0b, 0x00, 0, 0x0c240000, 0, 0x00000000 },
961
+
{ 0x0, 0x0c, 0x00, 0, 0x0c250000, 0, 0x00000000 },
962
+
{ 0x0, 0x0d, 0x00, 0, 0x0c340000, 0, 0x00000000 },
963
+
{ 0x0, 0x0e, 0x00, 0, 0x0c260000, 0, 0x00000000 },
964
+
{ 0x0, 0x0f, 0x00, 0, 0x0c0f0000, 0, 0x00000000 },
965
+
{ 0x0, 0x0f, 0x01, 0, 0x0c100000, 1, 0x00010000 },
966
+
{ 0x0, 0x0f, 0x02, 0, 0x0c110000, 2, 0x00020000 },
967
+
{ 0x0, 0x0f, 0x03, 0, 0x0c120000, 3, 0x00030000 },
968
+
{ 0x0, 0x0f, 0x04, 0, 0x0c130000, 4, 0x00040000 },
969
+
{ 0x0, 0x0f, 0x05, 0, 0x0c140000, 5, 0x00050000 },
970
+
{ 0x0, 0x10, 0x00, 0, 0x0c290000, 0, 0x00000000 },
971
+
{ 0x0, 0x30, 0x00, 0, 0x20ce0000, 0, 0x00000000 },
972
+
{ 0x0, 0x31, 0x00, 0, 0x0c1f0000, 0, 0x00000000 },
973
+
{ 0x0, 0x31, 0x01, 0, 0x0c200000, 1, 0x00010000 },
974
+
{ 0x0, 0x31, 0x02, 0, 0x0c210000, 2, 0x00020000 },
975
+
{ 0x0, 0x31, 0x03, 0, 0x0c220000, 3, 0x00030000 },
976
+
{ 0x0, 0x32, 0x00, 0, 0x20cc0000, 3, 0x001c0000 },
977
+
{ 0x0, 0x32, 0x01, 0, 0x20c80000, 2, 0x00180000 },
978
+
{ 0x0, 0x32, 0x02, 0, 0x20c00000, 1, 0x00100000 },
979
+
{ 0x0, 0x32, 0x03, 0, 0x20b00000, 0, 0x00000000 },
980
+
{ 0x0, 0x33, 0x00, 0, 0x0c360000, 0, 0x00000000 },
981
+
{ 0x0, 0x33, 0x01, 0, 0x0c370000, 1, 0x00010000 },
982
+
{ 0x0, 0x33, 0x02, 0, 0x0c3a0000, 3, 0x00040000 },
983
+
{ 0x0, 0x33, 0x03, 0, 0x0c380000, 2, 0x00020000 },
984
+
{ 0x0, 0x38, 0x00, 0, 0x0c600000, 0, 0x00000000 },
985
+
{ 0x0, 0x38, 0x01, 0, 0x00000000, 0, 0x00000000 },
986
+
{ 0x0, 0x39, 0x00, 0, 0x0c280000, 0, 0x00000000 },
987
+
{ 0x1, 0x35, 0x00, 0, 0x00000000, 0, 0x00000000 },
988
+
{ 0x1, 0x35, 0x01, 0, 0x00100000, 1, 0x00100000 },
989
+
{ 0x1, 0x35, 0x02, 0, 0x05a00000, 11, 0x05a00000 },
990
+
{ 0x1, 0x35, 0x03, 0, 0x05b00000, 32, 0x05b00000 },
991
+
{ 0x1, 0x35, 0x04, 0, 0x05c00000, 33, 0x05c00000 },
992
+
{ 0x1, 0x35, 0x05, 0, 0x05d00000, 12, 0x05d00000 },
993
+
{ 0x1, 0x35, 0x06, 0, 0x20000000, 19, 0x20000000 },
994
+
{ 0x1, 0x35, 0x07, 0, 0x20100000, 20, 0x20100000 },
995
+
{ 0x1, 0x35, 0x08, 0, 0x20a00000, 24, 0x20a00000 },
996
+
{ 0x1, 0x35, 0x09, 0, 0x20d00000, 25, 0x20d00000 },
997
+
{ 0x1, 0x35, 0x0a, 0, 0x00200000, 2, 0x00200000 },
998
+
{ 0x1, 0x35, 0x0b, 0, 0x05800000, 10, 0x05800000 },
999
+
{ 0x1, 0x35, 0x0c, 0, 0x05e00000, 13, 0x05e00000 },
1000
+
{ 0x1, 0x35, 0x0d, 0, 0x20200000, 21, 0x20200000 },
1001
+
{ 0x1, 0x35, 0x0e, 0, 0x20800000, 23, 0x20800000 },
1002
+
{ 0x1, 0x35, 0x0f, 0, 0x20e00000, 26, 0x20e00000 },
1003
+
{ 0x1, 0x35, 0x10, 0, 0x00400000, 3, 0x00400000 },
1004
+
{ 0x1, 0x35, 0x11, 0, 0x20400000, 22, 0x20400000 },
1005
+
{ 0x1, 0x35, 0x12, 0, 0x00800000, 4, 0x00800000 },
1006
+
{ 0x1, 0x35, 0x13, 0, 0x05000000, 9, 0x05000000 },
1007
+
{ 0x1, 0x35, 0x14, 0, 0x0c800000, 34, 0x0c800000 },
1008
+
{ 0x1, 0x35, 0x15, 0, 0x01000000, 5, 0x01000000 },
1009
+
{ 0x1, 0x35, 0x16, 0, 0x03000000, 7, 0x03000000 },
1010
+
{ 0x1, 0x35, 0x17, 0, 0x04000000, 8, 0x04000000 },
1011
+
{ 0x1, 0x35, 0x18, 0, 0x0d000000, 16, 0x0d000000 },
1012
+
{ 0x1, 0x35, 0x19, 0, 0x21000000, 27, 0x21000000 },
1013
+
{ 0x1, 0x35, 0x1a, 0, 0x02000000, 6, 0x02000000 },
1014
+
{ 0x1, 0x35, 0x1b, 0, 0x06000000, 14, 0x06000000 },
1015
+
{ 0x1, 0x35, 0x1c, 0, 0x0e000000, 17, 0x0e000000 },
1016
+
{ 0x1, 0x35, 0x1d, 0, 0x22000000, 28, 0x22000000 },
1017
+
{ 0x1, 0x35, 0x1e, 0, 0x08000000, 15, 0x08000000 },
1018
+
{ 0x1, 0x35, 0x1f, 0, 0x24000000, 29, 0x24000000 },
1019
+
{ 0x1, 0x35, 0x20, 0, 0x28000000, 30, 0x28000000 },
1020
+
{ 0x1, 0x35, 0x21, 0, 0x10000000, 18, 0x10000000 },
1021
+
{ 0x1, 0x35, 0x22, 0, 0x30000000, 31, 0x30000000 },
1022
+
{ 0x1, 0x37, 0x00, 0, 0x0c640000, 0, 0x00000000 },
1023
+
{ 0x1, 0x20, 0x00, 0, 0x0c3b0000, 0, 0x00000000 },
1024
+
{ 0x1, 0x21, 0x00, 0, 0x0c000000, 0, 0x00000000 },
1025
+
{ 0x1, 0x22, 0x00, 0, 0x0c040000, 0, 0x00000000 },
1026
+
{ 0x1, 0x23, 0x00, 0, 0x0c050000, 0, 0x00000000 },
1027
+
{ 0x1, 0x24, 0x00, 0, 0x20cf0000, 0, 0x00000000 },
1028
+
{ 0x1, 0x25, 0x00, 0, 0x0c2f0000, 0, 0x00000000 },
1029
+
{ 0x1, 0x26, 0x00, 0, 0x0c230000, 0, 0x00000000 },
1030
+
{ 0x1, 0x27, 0x00, 0, 0x0c350000, 0, 0x00000000 },
1031
+
{ 0x1, 0x28, 0x00, 0, 0x0c301000, 0, 0x00000000 },
1032
+
{ 0x1, 0x29, 0x00, 0, 0x0c302000, 0, 0x00000000 },
1033
+
{ 0x1, 0x2a, 0x00, 0, 0x0c303000, 0, 0x00000000 },
1034
+
{ 0x1, 0x2b, 0x00, 0, 0x0c2a0000, 0, 0x00000000 },
1035
+
{ 0x1, 0x2c, 0x00, 0, 0x0c2b0000, 0, 0x00000000 },
1036
+
{ 0x1, 0x2c, 0x01, 0, 0x0c2c0000, 1, 0x00010000 },
1037
+
{ 0x1, 0x2c, 0x02, 0, 0x0c2d0000, 2, 0x00020000 },
1038
+
{ 0x1, 0x2c, 0x03, 0, 0x0c2e0000, 3, 0x00030000 },
1039
+
{ 0x1, 0x00, 0x00, 0, 0x0c660000, 0, 0x00000000 },
1040
+
{ 0x1, 0x01, 0x00, 0, 0x0c020000, 0, 0x00000000 },
1041
+
{ 0x1, 0x02, 0x00, 0, 0x0c030000, 0, 0x00000000 },
1042
+
{ 0x1, 0x03, 0x00, 0, 0x0c310000, 0, 0x00000000 },
1043
+
{ 0x1, 0x04, 0x00, 0, 0x0c320000, 0, 0x00000000 },
1044
+
{ 0x1, 0x05, 0x00, 0, 0x0c0a0000, 2, 0x00040000 },
1045
+
{ 0x1, 0x05, 0x01, 0, 0x0c0b0000, 3, 0x00050000 },
1046
+
{ 0x1, 0x05, 0x02, 0, 0x0c0e0000, 5, 0x00080000 },
1047
+
{ 0x1, 0x05, 0x03, 0, 0x0c060000, 0, 0x00000000 },
1048
+
{ 0x1, 0x05, 0x04, 0, 0x0c080000, 1, 0x00020000 },
1049
+
{ 0x1, 0x05, 0x05, 0, 0x0c0c0000, 4, 0x00060000 },
1050
+
{ 0x1, 0x06, 0x00, 0, 0x0c330000, 0, 0x00000000 },
1051
+
{ 0x1, 0x07, 0x00, 0, 0x0c650000, 0, 0x00000000 },
1052
+
{ 0x1, 0x08, 0x00, 0, 0x0c3e0000, 0, 0x00000000 },
1053
+
{ 0x1, 0x09, 0x00, 0, 0x0c1e0000, 0, 0x00000000 },
1054
+
{ 0x1, 0x0a, 0x00, 0, 0x0c150000, 0, 0x00000000 },
1055
+
{ 0x1, 0x0a, 0x01, 0, 0x0c160000, 1, 0x00010000 },
1056
+
{ 0x1, 0x0a, 0x02, 0, 0x0c170000, 2, 0x00020000 },
1057
+
{ 0x1, 0x0a, 0x03, 0, 0x0c180000, 3, 0x00030000 },
1058
+
{ 0x1, 0x0a, 0x04, 0, 0x0c190000, 4, 0x00040000 },
1059
+
{ 0x1, 0x0a, 0x05, 0, 0x0c1a0000, 5, 0x00050000 },
1060
+
{ 0x1, 0x0a, 0x06, 0, 0x0c1b0000, 6, 0x00060000 },
1061
+
{ 0x1, 0x0a, 0x07, 0, 0x0c1c0000, 7, 0x00070000 },
1062
+
{ 0x1, 0x0a, 0x08, 0, 0x0c1d0000, 8, 0x00080000 },
1063
+
{ 0x1, 0x0b, 0x00, 0, 0x0c240000, 0, 0x00000000 },
1064
+
{ 0x1, 0x0c, 0x00, 0, 0x0c250000, 0, 0x00000000 },
1065
+
{ 0x1, 0x0d, 0x00, 0, 0x0c340000, 0, 0x00000000 },
1066
+
{ 0x1, 0x0e, 0x00, 0, 0x0c260000, 0, 0x00000000 },
1067
+
{ 0x1, 0x0f, 0x00, 0, 0x0c0f0000, 0, 0x00000000 },
1068
+
{ 0x1, 0x0f, 0x01, 0, 0x0c100000, 1, 0x00010000 },
1069
+
{ 0x1, 0x0f, 0x02, 0, 0x0c110000, 2, 0x00020000 },
1070
+
{ 0x1, 0x0f, 0x03, 0, 0x0c120000, 3, 0x00030000 },
1071
+
{ 0x1, 0x0f, 0x04, 0, 0x0c130000, 4, 0x00040000 },
1072
+
{ 0x1, 0x0f, 0x05, 0, 0x0c140000, 5, 0x00050000 },
1073
+
{ 0x1, 0x10, 0x00, 0, 0x0c290000, 0, 0x00000000 },
1074
+
{ 0x1, 0x30, 0x00, 0, 0x20ce0000, 0, 0x00000000 },
1075
+
{ 0x1, 0x31, 0x00, 0, 0x0c1f0000, 0, 0x00000000 },
1076
+
{ 0x1, 0x31, 0x01, 0, 0x0c200000, 1, 0x00010000 },
1077
+
{ 0x1, 0x31, 0x02, 0, 0x0c210000, 2, 0x00020000 },
1078
+
{ 0x1, 0x31, 0x03, 0, 0x0c220000, 3, 0x00030000 },
1079
+
{ 0x1, 0x32, 0x00, 0, 0x20cc0000, 3, 0x001c0000 },
1080
+
{ 0x1, 0x32, 0x01, 0, 0x20c80000, 2, 0x00180000 },
1081
+
{ 0x1, 0x32, 0x02, 0, 0x20c00000, 1, 0x00100000 },
1082
+
{ 0x1, 0x32, 0x03, 0, 0x20b00000, 0, 0x00000000 },
1083
+
{ 0x1, 0x33, 0x00, 0, 0x0c360000, 0, 0x00000000 },
1084
+
{ 0x1, 0x33, 0x01, 0, 0x0c370000, 1, 0x00010000 },
1085
+
{ 0x1, 0x33, 0x02, 0, 0x0c3a0000, 3, 0x00040000 },
1086
+
{ 0x1, 0x33, 0x03, 0, 0x0c380000, 2, 0x00020000 },
1087
+
{ 0x1, 0x38, 0x00, 0, 0x0c600000, 0, 0x00000000 },
1088
+
{ 0x1, 0x38, 0x01, 0, 0x00000000, 0, 0x00000000 },
1089
+
{ 0x1, 0x39, 0x00, 0, 0x0c280000, 0, 0x00000000 },
1090
+
{ 0x2, 0x34, 0x00, 0, 0x40000000, 0, 0x40000000 },
1091
+
{ 0x2, 0x34, 0x01, 0, 0x80000000, 1, 0x80000000 },
1092
+
{ 0x2, 0x36, 0x00, 0, 0x0c400000, 0, 0x0c400000 },
1093
+
{ 0x2, 0x36, 0x01, 0, 0x00000000, 0, 0x00000000 },
1094
+
{ 0x3, 0x35, 0x00, 0, 0x00000000, 0, 0x00000000 },
1095
+
{ 0x3, 0x35, 0x01, 0, 0x00100000, 1, 0x00100000 },
1096
+
{ 0x3, 0x35, 0x02, 0, 0x05a00000, 11, 0x05a00000 },
1097
+
{ 0x3, 0x35, 0x03, 0, 0x05b00000, 32, 0x05b00000 },
1098
+
{ 0x3, 0x35, 0x04, 0, 0x05c00000, 33, 0x05c00000 },
1099
+
{ 0x3, 0x35, 0x05, 0, 0x05d00000, 12, 0x05d00000 },
1100
+
{ 0x3, 0x35, 0x06, 0, 0x20000000, 19, 0x20000000 },
1101
+
{ 0x3, 0x35, 0x07, 0, 0x20100000, 20, 0x20100000 },
1102
+
{ 0x3, 0x35, 0x08, 0, 0x20a00000, 24, 0x20a00000 },
1103
+
{ 0x3, 0x35, 0x09, 0, 0x20d00000, 25, 0x20d00000 },
1104
+
{ 0x3, 0x35, 0x0a, 0, 0x00200000, 2, 0x00200000 },
1105
+
{ 0x3, 0x35, 0x0b, 0, 0x05800000, 10, 0x05800000 },
1106
+
{ 0x3, 0x35, 0x0c, 0, 0x05e00000, 13, 0x05e00000 },
1107
+
{ 0x3, 0x35, 0x0d, 0, 0x20200000, 21, 0x20200000 },
1108
+
{ 0x3, 0x35, 0x0e, 0, 0x20800000, 23, 0x20800000 },
1109
+
{ 0x3, 0x35, 0x0f, 0, 0x20e00000, 26, 0x20e00000 },
1110
+
{ 0x3, 0x35, 0x10, 0, 0x00400000, 3, 0x00400000 },
1111
+
{ 0x3, 0x35, 0x11, 0, 0x20400000, 22, 0x20400000 },
1112
+
{ 0x3, 0x35, 0x12, 0, 0x00800000, 4, 0x00800000 },
1113
+
{ 0x3, 0x35, 0x13, 0, 0x50000000, 9, 0x05000000 },
1114
+
{ 0x3, 0x35, 0x14, 0, 0xc0800000, 34, 0x0c800000 },
1115
+
{ 0x3, 0x35, 0x15, 0, 0x10000000, 5, 0x01000000 },
1116
+
{ 0x3, 0x35, 0x16, 0, 0x30000000, 7, 0x03000000 },
1117
+
{ 0x3, 0x35, 0x17, 0, 0x04000000, 8, 0x04000000 },
1118
+
{ 0x3, 0x35, 0x18, 0, 0x0d000000, 16, 0x0d000000 },
1119
+
{ 0x3, 0x35, 0x19, 0, 0x21000000, 27, 0x21000000 },
1120
+
{ 0x3, 0x35, 0x1a, 0, 0x02000000, 6, 0x02000000 },
1121
+
{ 0x3, 0x35, 0x1b, 0, 0x06000000, 14, 0x06000000 },
1122
+
{ 0x3, 0x35, 0x1c, 0, 0x0e000000, 17, 0x0e000000 },
1123
+
{ 0x3, 0x35, 0x1d, 0, 0x22000000, 28, 0x22000000 },
1124
+
{ 0x3, 0x35, 0x1e, 0, 0x08000000, 15, 0x08000000 },
1125
+
{ 0x3, 0x35, 0x1f, 0, 0x24000000, 29, 0x24000000 },
1126
+
{ 0x3, 0x35, 0x20, 0, 0x28000000, 30, 0x28000000 },
1127
+
{ 0x3, 0x35, 0x21, 0, 0x10000000, 18, 0x10000000 },
1128
+
{ 0x3, 0x35, 0x22, 0, 0x30000000, 31, 0x30000000 },
1129
+
{ 0x3, 0x37, 0x00, 0, 0x0c640000, 0, 0x00000000 },
1130
+
{ 0x3, 0x20, 0x00, 0, 0x0c3b0000, 0, 0x00000000 },
1131
+
{ 0x3, 0x21, 0x00, 0, 0x0c000000, 0, 0x00000000 },
1132
+
{ 0x3, 0x22, 0x00, 0, 0x0c040000, 0, 0x00000000 },
1133
+
{ 0x3, 0x23, 0x00, 0, 0x0c050000, 0, 0x00000000 },
1134
+
{ 0x3, 0x24, 0x00, 0, 0x20cf0000, 0, 0x00000000 },
1135
+
{ 0x3, 0x25, 0x00, 0, 0x0c2f0000, 0, 0x00000000 },
1136
+
{ 0x3, 0x26, 0x00, 0, 0x0c230000, 0, 0x00000000 },
1137
+
{ 0x3, 0x27, 0x00, 0, 0x0c350000, 0, 0x00000000 },
1138
+
{ 0x3, 0x28, 0x00, 0, 0x0c301000, 0, 0x00000000 },
1139
+
{ 0x3, 0x29, 0x00, 0, 0x0c302000, 0, 0x00000000 },
1140
+
{ 0x3, 0x2a, 0x00, 0, 0x0c303000, 0, 0x00000000 },
1141
+
{ 0x3, 0x2b, 0x00, 0, 0x0c2a0000, 0, 0x00000000 },
1142
+
{ 0x3, 0x2c, 0x00, 0, 0x0c2b0000, 0, 0x00000000 },
1143
+
{ 0x3, 0x2c, 0x01, 0, 0x0c2c0000, 1, 0x00010000 },
1144
+
{ 0x3, 0x2c, 0x02, 0, 0x0c2d0000, 2, 0x00020000 },
1145
+
{ 0x3, 0x2c, 0x03, 0, 0x0c2e0000, 3, 0x00030000 },
1146
+
{ 0x3, 0x00, 0x00, 0, 0x0c660000, 0, 0x00000000 },
1147
+
{ 0x3, 0x01, 0x00, 0, 0x0c020000, 0, 0x00000000 },
1148
+
{ 0x3, 0x02, 0x00, 0, 0x0c030000, 0, 0x00000000 },
1149
+
{ 0x3, 0x03, 0x00, 0, 0x0c310000, 0, 0x00000000 },
1150
+
{ 0x3, 0x04, 0x00, 0, 0x0c320000, 0, 0x00000000 },
1151
+
{ 0x3, 0x05, 0x00, 0, 0x0c0a0000, 2, 0x00040000 },
1152
+
{ 0x3, 0x05, 0x01, 0, 0x0c0b0000, 3, 0x00050000 },
1153
+
{ 0x3, 0x05, 0x02, 0, 0x0c0e0000, 5, 0x00080000 },
1154
+
{ 0x3, 0x05, 0x03, 0, 0x0c060000, 0, 0x00000000 },
1155
+
{ 0x3, 0x05, 0x04, 0, 0x0c080000, 1, 0x00020000 },
1156
+
{ 0x3, 0x05, 0x05, 0, 0x0c0c0000, 4, 0x00060000 },
1157
+
{ 0x3, 0x06, 0x00, 0, 0x0c330000, 0, 0x00000000 },
1158
+
{ 0x3, 0x07, 0x00, 0, 0x0c650000, 0, 0x00000000 },
1159
+
{ 0x3, 0x08, 0x00, 0, 0x0c3e0000, 0, 0x00000000 },
1160
+
{ 0x3, 0x09, 0x00, 0, 0x0c1e0000, 0, 0x00000000 },
1161
+
{ 0x3, 0x0a, 0x00, 0, 0x0c150000, 0, 0x00000000 },
1162
+
{ 0x3, 0x0a, 0x01, 0, 0x0c160000, 1, 0x00010000 },
1163
+
{ 0x3, 0x0a, 0x02, 0, 0x0c170000, 2, 0x00020000 },
1164
+
{ 0x3, 0x0a, 0x03, 0, 0x0c180000, 3, 0x00030000 },
1165
+
{ 0x3, 0x0a, 0x04, 0, 0x0c190000, 4, 0x00040000 },
1166
+
{ 0x3, 0x0a, 0x05, 0, 0x0c1a0000, 5, 0x00050000 },
1167
+
{ 0x3, 0x0a, 0x06, 0, 0x0c1b0000, 6, 0x00060000 },
1168
+
{ 0x3, 0x0a, 0x07, 0, 0x0c1c0000, 7, 0x00070000 },
1169
+
{ 0x3, 0x0a, 0x08, 0, 0x0c1d0000, 8, 0x00080000 },
1170
+
{ 0x3, 0x0b, 0x00, 0, 0x0c240000, 0, 0x00000000 },
1171
+
{ 0x3, 0x0c, 0x00, 0, 0x0c250000, 0, 0x00000000 },
1172
+
{ 0x3, 0x0d, 0x00, 0, 0x0c340000, 0, 0x00000000 },
1173
+
{ 0x3, 0x0e, 0x00, 0, 0x0c260000, 0, 0x00000000 },
1174
+
{ 0x3, 0x0f, 0x00, 0, 0x0c0f0000, 0, 0x00000000 },
1175
+
{ 0x3, 0x0f, 0x01, 0, 0x0c100000, 1, 0x00010000 },
1176
+
{ 0x3, 0x0f, 0x02, 0, 0x0c110000, 2, 0x00020000 },
1177
+
{ 0x3, 0x0f, 0x03, 0, 0x0c120000, 3, 0x00030000 },
1178
+
{ 0x3, 0x0f, 0x04, 0, 0x0c130000, 4, 0x00040000 },
1179
+
{ 0x3, 0x0f, 0x05, 0, 0x0c140000, 5, 0x00050000 },
1180
+
{ 0x3, 0x10, 0x00, 0, 0x0c290000, 0, 0x00000000 },
1181
+
{ 0x3, 0x30, 0x00, 0, 0x20ce0000, 0, 0x00000000 },
1182
+
{ 0x3, 0x31, 0x00, 0, 0x0c1f0000, 0, 0x00000000 },
1183
+
{ 0x3, 0x31, 0x01, 0, 0x0c200000, 1, 0x00010000 },
1184
+
{ 0x3, 0x31, 0x02, 0, 0x0c210000, 2, 0x00020000 },
1185
+
{ 0x3, 0x31, 0x03, 0, 0x0c220000, 3, 0x00030000 },
1186
+
{ 0x3, 0x32, 0x00, 0, 0x20cc0000, 3, 0x001c0000 },
1187
+
{ 0x3, 0x32, 0x01, 0, 0x20c80000, 2, 0x00180000 },
1188
+
{ 0x3, 0x32, 0x02, 0, 0x20c00000, 1, 0x00100000 },
1189
+
{ 0x3, 0x32, 0x03, 0, 0x20b00000, 0, 0x00000000 },
1190
+
{ 0x3, 0x33, 0x00, 0, 0x0c360000, 0, 0x00000000 },
1191
+
{ 0x3, 0x33, 0x01, 0, 0x0c370000, 1, 0x00010000 },
1192
+
{ 0x3, 0x33, 0x02, 0, 0x0c3a0000, 3, 0x00040000 },
1193
+
{ 0x3, 0x33, 0x03, 0, 0x0c380000, 2, 0x00020000 },
1194
+
{ 0x3, 0x38, 0x00, 0, 0x0c600000, 0, 0x00000000 },
1195
+
{ 0x3, 0x38, 0x01, 0, 0x00000000, 0, 0x00000000 },
1196
+
{ 0x3, 0x39, 0x00, 0, 0x0c280000, 0, 0x00000000 }
1197
+
};
1198
+
1199
+
/*
1200
+
* SCE/RCE NOC aperture lookup table as per file "AON_NOC_Structure.info".
1201
+
*/
1202
+
static const char * const tegra194_scenoc_routeid_initflow[] = {
1203
+
[0x0] = "cbb_i/I/0",
1204
+
[0x1] = "cpu_m_i/I/0",
1205
+
[0x2] = "cpu_p_i/I/0",
1206
+
[0x3] = "dma_m_i/I/0",
1207
+
[0x4] = "dma_p_i/I/0",
1208
+
[0x5] = "RESERVED",
1209
+
[0x6] = "RESERVED",
1210
+
[0x7] = "RESERVED"
1211
+
};
1212
+
1213
+
static const char * const tegra194_scenoc_routeid_targflow[] = {
1214
+
[0x00] = "multiport0_t/T/atcm_cfg",
1215
+
[0x01] = "multiport0_t/T/car",
1216
+
[0x02] = "multiport0_t/T/cast",
1217
+
[0x03] = "multiport0_t/T/cfg",
1218
+
[0x04] = "multiport0_t/T/dast",
1219
+
[0x05] = "multiport0_t/T/dma",
1220
+
[0x06] = "multiport0_t/T/err_collator",
1221
+
[0x07] = "multiport0_t/T/err_collator_car",
1222
+
[0x08] = "multiport0_t/T/fpga_misc",
1223
+
[0x09] = "multiport0_t/T/fpga_uart",
1224
+
[0x0a] = "multiport0_t/T/gte",
1225
+
[0x0b] = "multiport0_t/T/hsp",
1226
+
[0x0c] = "multiport0_t/T/misc",
1227
+
[0x0d] = "multiport0_t/T/pm",
1228
+
[0x0e] = "multiport0_t/T/tke",
1229
+
[0x0f] = "RESERVED",
1230
+
[0x10] = "multiport1_t/T/hsm",
1231
+
[0x11] = "multiport1_t/T/vic0",
1232
+
[0x12] = "multiport1_t/T/vic1",
1233
+
[0x13] = "ast0_t/T/0",
1234
+
[0x14] = "ast1_t/T/0",
1235
+
[0x15] = "cbb_t/T/0",
1236
+
[0x16] = "cpu_t/T/0",
1237
+
[0x17] = "sce_noc_firewall/T/0",
1238
+
[0x18] = "svc_t/T/0",
1239
+
[0x19] = "RESERVED",
1240
+
[0x1a] = "RESERVED",
1241
+
[0x1b] = "RESERVED",
1242
+
[0x1c] = "RESERVED",
1243
+
[0x1d] = "RESERVED",
1244
+
[0x1e] = "RESERVED",
1245
+
[0x1f] = "RESERVED"
1246
+
};
1247
+
1248
+
/*
1249
+
* Fields of SCE/RCE NOC lookup table:
1250
+
* Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress,
1251
+
* Targ mapping, Targ localAddress
1252
+
* ----------------------------------------------------------------------------
1253
+
*/
1254
+
static const struct tegra194_cbb_aperture tegra194_scenoc_apert_lookup[] = {
1255
+
{ 0x0, 0x16, 0x0, 0, 0x0b400000, 0, 0x0b400000 },
1256
+
{ 0x0, 0x16, 0x1, 0, 0x0bc00000, 1, 0x0bc00000 },
1257
+
{ 0x0, 0x0, 0x0, 0, 0x0b000000, 0, 0x00000000 },
1258
+
{ 0x0, 0x0, 0x1, 0, 0x0b800000, 1, 0x00000000 },
1259
+
{ 0x0, 0x1, 0x0, 0, 0x20de0000, 3, 0x000e0000 },
1260
+
{ 0x0, 0x1, 0x1, 0, 0x210e0000, 7, 0x000e0000 },
1261
+
{ 0x0, 0x1, 0x2, 0, 0x20dc0000, 2, 0x000c0000 },
1262
+
{ 0x0, 0x1, 0x3, 0, 0x210c0000, 6, 0x000c0000 },
1263
+
{ 0x0, 0x1, 0x4, 0, 0x20d80000, 1, 0x00080000 },
1264
+
{ 0x0, 0x1, 0x5, 0, 0x21080000, 5, 0x00080000 },
1265
+
{ 0x0, 0x1, 0x6, 0, 0x20d00000, 0, 0x00000000 },
1266
+
{ 0x0, 0x1, 0x7, 0, 0x21000000, 4, 0x00000000 },
1267
+
{ 0x0, 0x2, 0x0, 0, 0x0b040000, 0, 0x00000000 },
1268
+
{ 0x0, 0x2, 0x1, 0, 0x0b840000, 1, 0x00000000 },
1269
+
{ 0x0, 0x3, 0x0, 0, 0x0b230000, 0, 0x00000000 },
1270
+
{ 0x0, 0x3, 0x1, 0, 0x0ba30000, 1, 0x00000000 },
1271
+
{ 0x0, 0x4, 0x0, 0, 0x0b050000, 0, 0x00000000 },
1272
+
{ 0x0, 0x4, 0x1, 0, 0x0b850000, 1, 0x00000000 },
1273
+
{ 0x0, 0x5, 0x0, 0, 0x0b060000, 0, 0x00000000 },
1274
+
{ 0x0, 0x5, 0x1, 0, 0x0b070000, 1, 0x00010000 },
1275
+
{ 0x0, 0x5, 0x2, 0, 0x0b080000, 2, 0x00020000 },
1276
+
{ 0x0, 0x5, 0x3, 0, 0x0b090000, 3, 0x00030000 },
1277
+
{ 0x0, 0x5, 0x4, 0, 0x0b0a0000, 4, 0x00040000 },
1278
+
{ 0x0, 0x5, 0x5, 0, 0x0b0b0000, 5, 0x00050000 },
1279
+
{ 0x0, 0x5, 0x6, 0, 0x0b0c0000, 6, 0x00060000 },
1280
+
{ 0x0, 0x5, 0x7, 0, 0x0b0d0000, 7, 0x00070000 },
1281
+
{ 0x0, 0x5, 0x8, 0, 0x0b0e0000, 8, 0x00080000 },
1282
+
{ 0x0, 0x5, 0x9, 0, 0x0b860000, 9, 0x00000000 },
1283
+
{ 0x0, 0x5, 0xa, 0, 0x0b870000, 10, 0x00010000 },
1284
+
{ 0x0, 0x5, 0xb, 0, 0x0b880000, 11, 0x00020000 },
1285
+
{ 0x0, 0x5, 0xc, 0, 0x0b890000, 12, 0x00030000 },
1286
+
{ 0x0, 0x5, 0xd, 0, 0x0b8a0000, 13, 0x00040000 },
1287
+
{ 0x0, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
1288
+
{ 0x0, 0x5, 0xf, 0, 0x0b8c0000, 15, 0x00060000 },
1289
+
{ 0x0, 0x5, 0x10, 0, 0x0b8d0000, 16, 0x00070000 },
1290
+
{ 0x0, 0x5, 0x11, 0, 0x0b8e0000, 17, 0x00080000 },
1291
+
{ 0x0, 0x6, 0x0, 0, 0x0b650000, 0, 0x00000000 },
1292
+
{ 0x0, 0x6, 0x1, 0, 0x0be50000, 1, 0x00000000 },
1293
+
{ 0x0, 0x7, 0x0, 0, 0x20df0000, 0, 0x00000000 },
1294
+
{ 0x0, 0x7, 0x1, 0, 0x210f0000, 1, 0x00000000 },
1295
+
{ 0x0, 0x8, 0x0, 0, 0x0b3e0000, 0, 0x00000000 },
1296
+
{ 0x0, 0x8, 0x1, 0, 0x0bbe0000, 1, 0x00000000 },
1297
+
{ 0x0, 0x9, 0x0, 0, 0x0b3d0000, 0, 0x00000000 },
1298
+
{ 0x0, 0x9, 0x1, 0, 0x0bbd0000, 1, 0x00000000 },
1299
+
{ 0x0, 0xa, 0x0, 0, 0x0b1e0000, 0, 0x00000000 },
1300
+
{ 0x0, 0xa, 0x1, 0, 0x0b9e0000, 1, 0x00000000 },
1301
+
{ 0x0, 0xb, 0x0, 0, 0x0b150000, 0, 0x00000000 },
1302
+
{ 0x0, 0xb, 0x1, 0, 0x0b160000, 1, 0x00010000 },
1303
+
{ 0x0, 0xb, 0x2, 0, 0x0b170000, 2, 0x00020000 },
1304
+
{ 0x0, 0xb, 0x3, 0, 0x0b180000, 3, 0x00030000 },
1305
+
{ 0x0, 0xb, 0x4, 0, 0x0b190000, 4, 0x00040000 },
1306
+
{ 0x0, 0xb, 0x5, 0, 0x0b1a0000, 5, 0x00050000 },
1307
+
{ 0x0, 0xb, 0x6, 0, 0x0b1b0000, 6, 0x00060000 },
1308
+
{ 0x0, 0xb, 0x7, 0, 0x0b1c0000, 7, 0x00070000 },
1309
+
{ 0x0, 0xb, 0x8, 0, 0x0b1d0000, 8, 0x00080000 },
1310
+
{ 0x0, 0xb, 0x9, 0, 0x0b950000, 9, 0x00000000 },
1311
+
{ 0x0, 0xb, 0xa, 0, 0x0b960000, 10, 0x00010000 },
1312
+
{ 0x0, 0xb, 0xb, 0, 0x0b970000, 11, 0x00020000 },
1313
+
{ 0x0, 0xb, 0xc, 0, 0x0b980000, 12, 0x00030000 },
1314
+
{ 0x0, 0xb, 0xd, 0, 0x0b990000, 13, 0x00040000 },
1315
+
{ 0x0, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
1316
+
{ 0x0, 0xb, 0xf, 0, 0x0b9b0000, 15, 0x00060000 },
1317
+
{ 0x0, 0xb, 0x10, 0, 0x0b9c0000, 16, 0x00070000 },
1318
+
{ 0x0, 0xb, 0x11, 0, 0x0b9d0000, 17, 0x00080000 },
1319
+
{ 0x0, 0xc, 0x0, 0, 0x0b660000, 0, 0x00000000 },
1320
+
{ 0x0, 0xc, 0x1, 0, 0x0be60000, 1, 0x00000000 },
1321
+
{ 0x0, 0xd, 0x0, 0, 0x0b1f0000, 0, 0x00000000 },
1322
+
{ 0x0, 0xd, 0x1, 0, 0x0b200000, 1, 0x00010000 },
1323
+
{ 0x0, 0xd, 0x2, 0, 0x0b210000, 2, 0x00020000 },
1324
+
{ 0x0, 0xd, 0x3, 0, 0x0b220000, 3, 0x00030000 },
1325
+
{ 0x0, 0xd, 0x4, 0, 0x0b9f0000, 4, 0x00000000 },
1326
+
{ 0x0, 0xd, 0x5, 0, 0x0ba00000, 5, 0x00010000 },
1327
+
{ 0x0, 0xd, 0x6, 0, 0x0ba10000, 6, 0x00020000 },
1328
+
{ 0x0, 0xd, 0x7, 0, 0x0ba20000, 7, 0x00030000 },
1329
+
{ 0x0, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
1330
+
{ 0x0, 0xe, 0x1, 0, 0x0b100000, 1, 0x00010000 },
1331
+
{ 0x0, 0xe, 0x2, 0, 0x0b110000, 2, 0x00020000 },
1332
+
{ 0x0, 0xe, 0x3, 0, 0x0b120000, 3, 0x00030000 },
1333
+
{ 0x0, 0xe, 0x4, 0, 0x0b130000, 4, 0x00040000 },
1334
+
{ 0x0, 0xe, 0x5, 0, 0x0b140000, 5, 0x00050000 },
1335
+
{ 0x0, 0xe, 0x6, 0, 0x0b8f0000, 6, 0x00000000 },
1336
+
{ 0x0, 0xe, 0x7, 0, 0x0b900000, 7, 0x00010000 },
1337
+
{ 0x0, 0xe, 0x8, 0, 0x0b910000, 8, 0x00020000 },
1338
+
{ 0x0, 0xe, 0x9, 0, 0x0b920000, 9, 0x00030000 },
1339
+
{ 0x0, 0xe, 0xa, 0, 0x0b930000, 10, 0x00040000 },
1340
+
{ 0x0, 0xe, 0xb, 0, 0x0b940000, 11, 0x00050000 },
1341
+
{ 0x0, 0x10, 0x0, 0, 0x0b240000, 0, 0x00000000 },
1342
+
{ 0x0, 0x10, 0x1, 0, 0x0ba40000, 1, 0x00000000 },
1343
+
{ 0x0, 0x11, 0x0, 0, 0x0b020000, 0, 0x00000000 },
1344
+
{ 0x0, 0x11, 0x1, 0, 0x0b820000, 1, 0x00000000 },
1345
+
{ 0x0, 0x12, 0x0, 0, 0x0b030000, 0, 0x00000000 },
1346
+
{ 0x0, 0x12, 0x1, 0, 0x0b830000, 1, 0x00000000 },
1347
+
{ 0x0, 0x17, 0x0, 0, 0x0b640000, 0, 0x00000000 },
1348
+
{ 0x0, 0x17, 0x1, 0, 0x0be40000, 1, 0x00000000 },
1349
+
{ 0x0, 0x18, 0x0, 0, 0x0b600000, 0, 0x00000000 },
1350
+
{ 0x0, 0x18, 0x1, 0, 0x0be00000, 1, 0x00000000 },
1351
+
{ 0x0, 0x18, 0x2, 0, 0x00000000, 0, 0x00000000 },
1352
+
{ 0x0, 0x18, 0x3, 0, 0x00000000, 0, 0x00000000 },
1353
+
{ 0x1, 0x13, 0x0, 0, 0x40000000, 0, 0x40000000 },
1354
+
{ 0x1, 0x13, 0x1, 1, 0x80000000, 1, 0x80000000 },
1355
+
{ 0x1, 0x13, 0x2, 0, 0x00000000, 0, 0x00000000 },
1356
+
{ 0x2, 0x15, 0x0, 0, 0x20c00000, 8, 0x20c00000 },
1357
+
{ 0x2, 0x15, 0x1, 0, 0x21100000, 22, 0x21100000 },
1358
+
{ 0x2, 0x15, 0x2, 0, 0x20e00000, 9, 0x20e00000 },
1359
+
{ 0x2, 0x15, 0x3, 0, 0x21200000, 23, 0x21200000 },
1360
+
{ 0x2, 0x15, 0x4, 0, 0x20800000, 7, 0x20800000 },
1361
+
{ 0x2, 0x15, 0x5, 0, 0x21400000, 24, 0x21400000 },
1362
+
{ 0x2, 0x15, 0x6, 0, 0x0b000000, 18, 0x0b000000 },
1363
+
{ 0x2, 0x15, 0x7, 0, 0x0b800000, 3, 0x0b800000 },
1364
+
{ 0x2, 0x15, 0x8, 0, 0x20000000, 6, 0x20000000 },
1365
+
{ 0x2, 0x15, 0x9, 0, 0x21800000, 25, 0x21800000 },
1366
+
{ 0x2, 0x15, 0xa, 0, 0x0a000000, 2, 0x0a000000 },
1367
+
{ 0x2, 0x15, 0xb, 0, 0x0a000000, 17, 0x0a000000 },
1368
+
{ 0x2, 0x15, 0xc, 0, 0x20000000, 21, 0x20000000 },
1369
+
{ 0x2, 0x15, 0xd, 0, 0x21000000, 10, 0x21000000 },
1370
+
{ 0x2, 0x15, 0xe, 0, 0x08000000, 1, 0x08000000 },
1371
+
{ 0x2, 0x15, 0xf, 0, 0x08000000, 16, 0x08000000 },
1372
+
{ 0x2, 0x15, 0x10, 0, 0x22000000, 11, 0x22000000 },
1373
+
{ 0x2, 0x15, 0x11, 0, 0x22000000, 26, 0x22000000 },
1374
+
{ 0x2, 0x15, 0x12, 0, 0x0c000000, 4, 0x0c000000 },
1375
+
{ 0x2, 0x15, 0x13, 0, 0x0c000000, 19, 0x0c000000 },
1376
+
{ 0x2, 0x15, 0x14, 0, 0x24000000, 12, 0x24000000 },
1377
+
{ 0x2, 0x15, 0x15, 0, 0x24000000, 27, 0x24000000 },
1378
+
{ 0x2, 0x15, 0x16, 0, 0x00000000, 0, 0x00000000 },
1379
+
{ 0x2, 0x15, 0x17, 0, 0x00000000, 15, 0x00000000 },
1380
+
{ 0x2, 0x15, 0x18, 0, 0x28000000, 13, 0x28000000 },
1381
+
{ 0x2, 0x15, 0x19, 0, 0x28000000, 28, 0x28000000 },
1382
+
{ 0x2, 0x15, 0x1a, 0, 0x10000000, 5, 0x10000000 },
1383
+
{ 0x2, 0x15, 0x1b, 0, 0x10000000, 20, 0x10000000 },
1384
+
{ 0x2, 0x15, 0x1c, 0, 0x30000000, 14, 0x30000000 },
1385
+
{ 0x2, 0x15, 0x1d, 0, 0x30000000, 29, 0x30000000 },
1386
+
{ 0x2, 0x0, 0x0, 0, 0x0b000000, 0, 0x00000000 },
1387
+
{ 0x2, 0x0, 0x1, 0, 0x0b800000, 1, 0x00000000 },
1388
+
{ 0x2, 0x1, 0x0, 0, 0x20de0000, 3, 0x000e0000 },
1389
+
{ 0x2, 0x1, 0x1, 0, 0x210e0000, 7, 0x000e0000 },
1390
+
{ 0x2, 0x1, 0x2, 0, 0x20dc0000, 2, 0x000c0000 },
1391
+
{ 0x2, 0x1, 0x3, 0, 0x210c0000, 6, 0x000c0000 },
1392
+
{ 0x2, 0x1, 0x4, 0, 0x20d80000, 1, 0x00080000 },
1393
+
{ 0x2, 0x1, 0x5, 0, 0x21080000, 5, 0x00080000 },
1394
+
{ 0x2, 0x1, 0x6, 0, 0x20d00000, 0, 0x00000000 },
1395
+
{ 0x2, 0x1, 0x7, 0, 0x21000000, 4, 0x00000000 },
1396
+
{ 0x2, 0x2, 0x0, 0, 0x0b040000, 0, 0x00000000 },
1397
+
{ 0x2, 0x2, 0x1, 0, 0x0b840000, 1, 0x00000000 },
1398
+
{ 0x2, 0x3, 0x0, 0, 0x0b230000, 0, 0x00000000 },
1399
+
{ 0x2, 0x3, 0x1, 0, 0x0ba30000, 1, 0x00000000 },
1400
+
{ 0x2, 0x4, 0x0, 0, 0x0b050000, 0, 0x00000000 },
1401
+
{ 0x2, 0x4, 0x1, 0, 0x0b850000, 1, 0x00000000 },
1402
+
{ 0x2, 0x5, 0x0, 0, 0x0b060000, 0, 0x00000000 },
1403
+
{ 0x2, 0x5, 0x1, 0, 0x0b070000, 1, 0x00010000 },
1404
+
{ 0x2, 0x5, 0x2, 0, 0x0b080000, 2, 0x00020000 },
1405
+
{ 0x2, 0x5, 0x3, 0, 0x0b090000, 3, 0x00030000 },
1406
+
{ 0x2, 0x5, 0x4, 0, 0x0b0a0000, 4, 0x00040000 },
1407
+
{ 0x2, 0x5, 0x5, 0, 0x0b0b0000, 5, 0x00050000 },
1408
+
{ 0x2, 0x5, 0x6, 0, 0x0b0c0000, 6, 0x00060000 },
1409
+
{ 0x2, 0x5, 0x7, 0, 0x0b0d0000, 7, 0x00070000 },
1410
+
{ 0x2, 0x5, 0x8, 0, 0x0b0e0000, 8, 0x00080000 },
1411
+
{ 0x2, 0x5, 0x9, 0, 0x0b860000, 9, 0x00000000 },
1412
+
{ 0x2, 0x5, 0xa, 0, 0x0b870000, 10, 0x00010000 },
1413
+
{ 0x2, 0x5, 0xb, 0, 0x0b880000, 11, 0x00020000 },
1414
+
{ 0x2, 0x5, 0xc, 0, 0x0b890000, 12, 0x00030000 },
1415
+
{ 0x2, 0x5, 0xd, 0, 0x0b8a0000, 13, 0x00040000 },
1416
+
{ 0x2, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
1417
+
{ 0x2, 0x5, 0xf, 0, 0x0b8c0000, 15, 0x00060000 },
1418
+
{ 0x2, 0x5, 0x10, 0, 0x0b8d0000, 16, 0x00070000 },
1419
+
{ 0x2, 0x5, 0x11, 0, 0x0b8e0000, 17, 0x00080000 },
1420
+
{ 0x2, 0x6, 0x0, 0, 0x0b650000, 0, 0x00000000 },
1421
+
{ 0x2, 0x6, 0x1, 0, 0x0be50000, 1, 0x00000000 },
1422
+
{ 0x2, 0x7, 0x0, 0, 0x20df0000, 0, 0x00000000 },
1423
+
{ 0x2, 0x7, 0x1, 0, 0x210f0000, 1, 0x00000000 },
1424
+
{ 0x2, 0x8, 0x0, 0, 0x0b3e0000, 0, 0x00000000 },
1425
+
{ 0x2, 0x8, 0x1, 0, 0x0bbe0000, 1, 0x00000000 },
1426
+
{ 0x2, 0x9, 0x0, 0, 0x0b3d0000, 0, 0x00000000 },
1427
+
{ 0x2, 0x9, 0x1, 0, 0x0bbd0000, 1, 0x00000000 },
1428
+
{ 0x2, 0xa, 0x0, 0, 0x0b1e0000, 0, 0x00000000 },
1429
+
{ 0x2, 0xa, 0x1, 0, 0x0b9e0000, 1, 0x00000000 },
1430
+
{ 0x2, 0xb, 0x0, 0, 0x0b150000, 0, 0x00000000 },
1431
+
{ 0x2, 0xb, 0x1, 0, 0x0b160000, 1, 0x00010000 },
1432
+
{ 0x2, 0xb, 0x2, 0, 0x0b170000, 2, 0x00020000 },
1433
+
{ 0x2, 0xb, 0x3, 0, 0x0b180000, 3, 0x00030000 },
1434
+
{ 0x2, 0xb, 0x4, 0, 0x0b190000, 4, 0x00040000 },
1435
+
{ 0x2, 0xb, 0x5, 0, 0x0b1a0000, 5, 0x00050000 },
1436
+
{ 0x2, 0xb, 0x6, 0, 0x0b1b0000, 6, 0x00060000 },
1437
+
{ 0x2, 0xb, 0x7, 0, 0x0b1c0000, 7, 0x00070000 },
1438
+
{ 0x2, 0xb, 0x8, 0, 0x0b1d0000, 8, 0x00080000 },
1439
+
{ 0x2, 0xb, 0x9, 0, 0x0b950000, 9, 0x00000000 },
1440
+
{ 0x2, 0xb, 0xa, 0, 0x0b960000, 10, 0x00010000 },
1441
+
{ 0x2, 0xb, 0xb, 0, 0x0b970000, 11, 0x00020000 },
1442
+
{ 0x2, 0xb, 0xc, 0, 0x0b980000, 12, 0x00030000 },
1443
+
{ 0x2, 0xb, 0xd, 0, 0x0b990000, 13, 0x00040000 },
1444
+
{ 0x2, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
1445
+
{ 0x2, 0xb, 0xf, 0, 0x0b9b0000, 15, 0x00060000 },
1446
+
{ 0x2, 0xb, 0x10, 0, 0x0b9c0000, 16, 0x00070000 },
1447
+
{ 0x2, 0xb, 0x11, 0, 0x0b9d0000, 17, 0x00080000 },
1448
+
{ 0x2, 0xc, 0x0, 0, 0x0b660000, 0, 0x00000000 },
1449
+
{ 0x2, 0xc, 0x1, 0, 0x0be60000, 1, 0x00000000 },
1450
+
{ 0x2, 0xd, 0x0, 0, 0x0b1f0000, 0, 0x00000000 },
1451
+
{ 0x2, 0xd, 0x1, 0, 0x0b200000, 1, 0x00010000 },
1452
+
{ 0x2, 0xd, 0x2, 0, 0x0b210000, 2, 0x00020000 },
1453
+
{ 0x2, 0xd, 0x3, 0, 0x0b220000, 3, 0x00030000 },
1454
+
{ 0x2, 0xd, 0x4, 0, 0x0b9f0000, 4, 0x00000000 },
1455
+
{ 0x2, 0xd, 0x5, 0, 0x0ba00000, 5, 0x00010000 },
1456
+
{ 0x2, 0xd, 0x6, 0, 0x0ba10000, 6, 0x00020000 },
1457
+
{ 0x2, 0xd, 0x7, 0, 0x0ba20000, 7, 0x00030000 },
1458
+
{ 0x2, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
1459
+
{ 0x2, 0xe, 0x1, 0, 0x0b100000, 1, 0x00010000 },
1460
+
{ 0x2, 0xe, 0x2, 0, 0x0b110000, 2, 0x00020000 },
1461
+
{ 0x2, 0xe, 0x3, 0, 0x0b120000, 3, 0x00030000 },
1462
+
{ 0x2, 0xe, 0x4, 0, 0x0b130000, 4, 0x00040000 },
1463
+
{ 0x2, 0xe, 0x5, 0, 0x0b140000, 5, 0x00050000 },
1464
+
{ 0x2, 0xe, 0x6, 0, 0x0b8f0000, 6, 0x00000000 },
1465
+
{ 0x2, 0xe, 0x7, 0, 0x0b900000, 7, 0x00010000 },
1466
+
{ 0x2, 0xe, 0x8, 0, 0x0b910000, 8, 0x00020000 },
1467
+
{ 0x2, 0xe, 0x9, 0, 0x0b920000, 9, 0x00030000 },
1468
+
{ 0x2, 0xe, 0xa, 0, 0x0b930000, 10, 0x00040000 },
1469
+
{ 0x2, 0xe, 0xb, 0, 0x0b940000, 11, 0x00050000 },
1470
+
{ 0x2, 0x10, 0x0, 0, 0x0b240000, 0, 0x00000000 },
1471
+
{ 0x2, 0x10, 0x1, 0, 0x0ba40000, 1, 0x00000000 },
1472
+
{ 0x2, 0x11, 0x0, 0, 0x0b020000, 0, 0x00000000 },
1473
+
{ 0x2, 0x11, 0x1, 0, 0x0b820000, 1, 0x00000000 },
1474
+
{ 0x2, 0x12, 0x0, 0, 0x0b030000, 0, 0x00000000 },
1475
+
{ 0x2, 0x12, 0x1, 0, 0x0b830000, 1, 0x00000000 },
1476
+
{ 0x2, 0x17, 0x0, 0, 0x0b640000, 0, 0x00000000 },
1477
+
{ 0x2, 0x17, 0x1, 0, 0x0be40000, 1, 0x00000000 },
1478
+
{ 0x2, 0x18, 0x0, 0, 0x0b600000, 0, 0x00000000 },
1479
+
{ 0x2, 0x18, 0x1, 0, 0x0be00000, 1, 0x00000000 },
1480
+
{ 0x2, 0x18, 0x2, 0, 0x00000000, 0, 0x00000000 },
1481
+
{ 0x2, 0x18, 0x3, 0, 0x00000000, 0, 0x00000000 },
1482
+
{ 0x3, 0x14, 0x0, 0, 0x40000000, 0, 0x40000000 },
1483
+
{ 0x3, 0x14, 0x1, 1, 0x80000000, 1, 0x80000000 },
1484
+
{ 0x3, 0x16, 0x0, 2, 0x0b400000, 0, 0x0b400000 },
1485
+
{ 0x3, 0x16, 0x1, 2, 0x0bc00000, 1, 0x0bc00000 },
1486
+
{ 0x3, 0x16, 0x2, 0, 0x00000000, 0, 0x00000000 },
1487
+
{ 0x3, 0x16, 0x3, 0, 0x00000000, 0, 0x00000000 },
1488
+
{ 0x4, 0x15, 0x0, 0, 0x20c00000, 8, 0x20c00000 },
1489
+
{ 0x4, 0x15, 0x1, 0, 0x21100000, 22, 0x21100000 },
1490
+
{ 0x4, 0x15, 0x2, 0, 0x20e00000, 9, 0x20e00000 },
1491
+
{ 0x4, 0x15, 0x3, 0, 0x21200000, 23, 0x21200000 },
1492
+
{ 0x4, 0x15, 0x4, 0, 0x20800000, 7, 0x20800000 },
1493
+
{ 0x4, 0x15, 0x5, 0, 0x21400000, 24, 0x21400000 },
1494
+
{ 0x4, 0x15, 0x6, 0, 0x0b000000, 18, 0x0b000000 },
1495
+
{ 0x4, 0x15, 0x7, 0, 0x0b800000, 3, 0x0b800000 },
1496
+
{ 0x4, 0x15, 0x8, 0, 0x20000000, 6, 0x20000000 },
1497
+
{ 0x4, 0x15, 0x9, 0, 0x21800000, 25, 0x21800000 },
1498
+
{ 0x4, 0x15, 0xa, 0, 0x0a000000, 2, 0x0a000000 },
1499
+
{ 0x4, 0x15, 0xb, 0, 0x0a000000, 17, 0x0a000000 },
1500
+
{ 0x4, 0x15, 0xc, 0, 0x20000000, 21, 0x20000000 },
1501
+
{ 0x4, 0x15, 0xd, 0, 0x21000000, 10, 0x21000000 },
1502
+
{ 0x4, 0x15, 0xe, 0, 0x08000000, 1, 0x08000000 },
1503
+
{ 0x4, 0x15, 0xf, 0, 0x08000000, 16, 0x08000000 },
1504
+
{ 0x4, 0x15, 0x10, 0, 0x22000000, 11, 0x22000000 },
1505
+
{ 0x4, 0x15, 0x11, 0, 0x22000000, 26, 0x22000000 },
1506
+
{ 0x4, 0x15, 0x12, 0, 0x0c000000, 4, 0x0c000000 },
1507
+
{ 0x4, 0x15, 0x13, 0, 0x0c000000, 19, 0x0c000000 },
1508
+
{ 0x4, 0x15, 0x14, 0, 0x24000000, 12, 0x24000000 },
1509
+
{ 0x4, 0x15, 0x15, 0, 0x24000000, 27, 0x24000000 },
1510
+
{ 0x4, 0x15, 0x16, 0, 0x00000000, 0, 0x00000000 },
1511
+
{ 0x4, 0x15, 0x17, 0, 0x00000000, 15, 0x00000000 },
1512
+
{ 0x4, 0x15, 0x18, 0, 0x28000000, 13, 0x28000000 },
1513
+
{ 0x4, 0x15, 0x19, 0, 0x28000000, 28, 0x28000000 },
1514
+
{ 0x4, 0x15, 0x1a, 0, 0x10000000, 5, 0x10000000 },
1515
+
{ 0x4, 0x15, 0x1b, 0, 0x10000000, 20, 0x10000000 },
1516
+
{ 0x4, 0x15, 0x1c, 0, 0x30000000, 14, 0x30000000 },
1517
+
{ 0x4, 0x15, 0x1d, 0, 0x30000000, 29, 0x30000000 },
1518
+
{ 0x4, 0x0, 0x0, 0, 0x0b000000, 0, 0x00000000 },
1519
+
{ 0x4, 0x0, 0x1, 0, 0x0b800000, 1, 0x00000000 },
1520
+
{ 0x4, 0x1, 0x0, 0, 0x20de0000, 3, 0x000e0000 },
1521
+
{ 0x4, 0x1, 0x1, 0, 0x210e0000, 7, 0x000e0000 },
1522
+
{ 0x4, 0x1, 0x2, 0, 0x20dc0000, 2, 0x000c0000 },
1523
+
{ 0x4, 0x1, 0x3, 0, 0x210c0000, 6, 0x000c0000 },
1524
+
{ 0x4, 0x1, 0x4, 0, 0x20d80000, 1, 0x00080000 },
1525
+
{ 0x4, 0x1, 0x5, 0, 0x21080000, 5, 0x00080000 },
1526
+
{ 0x4, 0x1, 0x6, 0, 0x20d00000, 0, 0x00000000 },
1527
+
{ 0x4, 0x1, 0x7, 0, 0x21000000, 4, 0x00000000 },
1528
+
{ 0x4, 0x2, 0x0, 0, 0x0b040000, 0, 0x00000000 },
1529
+
{ 0x4, 0x2, 0x1, 0, 0x0b840000, 1, 0x00000000 },
1530
+
{ 0x4, 0x3, 0x0, 0, 0x0b230000, 0, 0x00000000 },
1531
+
{ 0x4, 0x3, 0x1, 0, 0x0ba30000, 1, 0x00000000 },
1532
+
{ 0x4, 0x4, 0x0, 0, 0x0b050000, 0, 0x00000000 },
1533
+
{ 0x4, 0x4, 0x1, 0, 0x0b850000, 1, 0x00000000 },
1534
+
{ 0x4, 0x5, 0x0, 0, 0x0b060000, 0, 0x00000000 },
1535
+
{ 0x4, 0x5, 0x1, 0, 0x0b070000, 1, 0x00010000 },
1536
+
{ 0x4, 0x5, 0x2, 0, 0x0b080000, 2, 0x00020000 },
1537
+
{ 0x4, 0x5, 0x3, 0, 0x0b090000, 3, 0x00030000 },
1538
+
{ 0x4, 0x5, 0x4, 0, 0x0b0a0000, 4, 0x00040000 },
1539
+
{ 0x4, 0x5, 0x5, 0, 0x0b0b0000, 5, 0x00050000 },
1540
+
{ 0x4, 0x5, 0x6, 0, 0x0b0c0000, 6, 0x00060000 },
1541
+
{ 0x4, 0x5, 0x7, 0, 0x0b0d0000, 7, 0x00070000 },
1542
+
{ 0x4, 0x5, 0x8, 0, 0x0b0e0000, 8, 0x00080000 },
1543
+
{ 0x4, 0x5, 0x9, 0, 0x0b860000, 9, 0x00000000 },
1544
+
{ 0x4, 0x5, 0xa, 0, 0x0b870000, 10, 0x00010000 },
1545
+
{ 0x4, 0x5, 0xb, 0, 0x0b880000, 11, 0x00020000 },
1546
+
{ 0x4, 0x5, 0xc, 0, 0x0b890000, 12, 0x00030000 },
1547
+
{ 0x4, 0x5, 0xd, 0, 0x0b8a0000, 13, 0x00040000 },
1548
+
{ 0x4, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
1549
+
{ 0x4, 0x5, 0xf, 0, 0x0b8c0000, 15, 0x00060000 },
1550
+
{ 0x4, 0x5, 0x10, 0, 0x0b8d0000, 16, 0x00070000 },
1551
+
{ 0x4, 0x5, 0x11, 0, 0x0b8e0000, 17, 0x00080000 },
1552
+
{ 0x4, 0x6, 0x0, 0, 0x0b650000, 0, 0x00000000 },
1553
+
{ 0x4, 0x6, 0x1, 0, 0x0be50000, 1, 0x00000000 },
1554
+
{ 0x4, 0x7, 0x0, 0, 0x20df0000, 0, 0x00000000 },
1555
+
{ 0x4, 0x7, 0x1, 0, 0x210f0000, 1, 0x00000000 },
1556
+
{ 0x4, 0x8, 0x0, 0, 0x0b3e0000, 0, 0x00000000 },
1557
+
{ 0x4, 0x8, 0x1, 0, 0x0bbe0000, 1, 0x00000000 },
1558
+
{ 0x4, 0x9, 0x0, 0, 0x0b3d0000, 0, 0x00000000 },
1559
+
{ 0x4, 0x9, 0x1, 0, 0x0bbd0000, 1, 0x00000000 },
1560
+
{ 0x4, 0xa, 0x0, 0, 0x0b1e0000, 0, 0x00000000 },
1561
+
{ 0x4, 0xa, 0x1, 0, 0x0b9e0000, 1, 0x00000000 },
1562
+
{ 0x4, 0xb, 0x0, 0, 0x0b150000, 0, 0x00000000 },
1563
+
{ 0x4, 0xb, 0x1, 0, 0x0b160000, 1, 0x00010000 },
1564
+
{ 0x4, 0xb, 0x2, 0, 0x0b170000, 2, 0x00020000 },
1565
+
{ 0x4, 0xb, 0x3, 0, 0x0b180000, 3, 0x00030000 },
1566
+
{ 0x4, 0xb, 0x4, 0, 0x0b190000, 4, 0x00040000 },
1567
+
{ 0x4, 0xb, 0x5, 0, 0x0b1a0000, 5, 0x00050000 },
1568
+
{ 0x4, 0xb, 0x6, 0, 0x0b1b0000, 6, 0x00060000 },
1569
+
{ 0x4, 0xb, 0x7, 0, 0x0b1c0000, 7, 0x00070000 },
1570
+
{ 0x4, 0xb, 0x8, 0, 0x0b1d0000, 8, 0x00080000 },
1571
+
{ 0x4, 0xb, 0x9, 0, 0x0b950000, 9, 0x00000000 },
1572
+
{ 0x4, 0xb, 0xa, 0, 0x0b960000, 10, 0x00010000 },
1573
+
{ 0x4, 0xb, 0xb, 0, 0x0b970000, 11, 0x00020000 },
1574
+
{ 0x4, 0xb, 0xc, 0, 0x0b980000, 12, 0x00030000 },
1575
+
{ 0x4, 0xb, 0xd, 0, 0x0b990000, 13, 0x00040000 },
1576
+
{ 0x4, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
1577
+
{ 0x4, 0xb, 0xf, 0, 0x0b9b0000, 15, 0x00060000 },
1578
+
{ 0x4, 0xb, 0x10, 0, 0x0b9c0000, 16, 0x00070000 },
1579
+
{ 0x4, 0xb, 0x11, 0, 0x0b9d0000, 17, 0x00080000 },
1580
+
{ 0x4, 0xc, 0x0, 0, 0x0b660000, 0, 0x00000000 },
1581
+
{ 0x4, 0xc, 0x1, 0, 0x0be60000, 1, 0x00000000 },
1582
+
{ 0x4, 0xd, 0x0, 0, 0x0b1f0000, 0, 0x00000000 },
1583
+
{ 0x4, 0xd, 0x1, 0, 0x0b200000, 1, 0x00010000 },
1584
+
{ 0x4, 0xd, 0x2, 0, 0x0b210000, 2, 0x00020000 },
1585
+
{ 0x4, 0xd, 0x3, 0, 0x0b220000, 3, 0x00030000 },
1586
+
{ 0x4, 0xd, 0x4, 0, 0x0b9f0000, 4, 0x00000000 },
1587
+
{ 0x4, 0xd, 0x5, 0, 0x0ba00000, 5, 0x00010000 },
1588
+
{ 0x4, 0xd, 0x6, 0, 0x0ba10000, 6, 0x00020000 },
1589
+
{ 0x4, 0xd, 0x7, 0, 0x0ba20000, 7, 0x00030000 },
1590
+
{ 0x4, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
1591
+
{ 0x4, 0xe, 0x1, 0, 0x0b100000, 1, 0x00010000 },
1592
+
{ 0x4, 0xe, 0x2, 0, 0x0b110000, 2, 0x00020000 },
1593
+
{ 0x4, 0xe, 0x3, 0, 0x0b120000, 3, 0x00030000 },
1594
+
{ 0x4, 0xe, 0x4, 0, 0x0b130000, 4, 0x00040000 },
1595
+
{ 0x4, 0xe, 0x5, 0, 0x0b140000, 5, 0x00050000 },
1596
+
{ 0x4, 0xe, 0x6, 0, 0x0b8f0000, 6, 0x00000000 },
1597
+
{ 0x4, 0xe, 0x7, 0, 0x0b900000, 7, 0x00010000 },
1598
+
{ 0x4, 0xe, 0x8, 0, 0x0b910000, 8, 0x00020000 },
1599
+
{ 0x4, 0xe, 0x9, 0, 0x0b920000, 9, 0x00030000 },
1600
+
{ 0x4, 0xe, 0xa, 0, 0x0b930000, 10, 0x00040000 },
1601
+
{ 0x4, 0xe, 0xb, 0, 0x0b940000, 11, 0x00050000 },
1602
+
{ 0x4, 0x10, 0x0, 0, 0x0b240000, 0, 0x00000000 },
1603
+
{ 0x4, 0x10, 0x1, 0, 0x0ba40000, 1, 0x00000000 },
1604
+
{ 0x4, 0x11, 0x0, 0, 0x0b020000, 0, 0x00000000 },
1605
+
{ 0x4, 0x11, 0x1, 0, 0x0b820000, 1, 0x00000000 },
1606
+
{ 0x4, 0x12, 0x0, 0, 0x0b030000, 0, 0x00000000 },
1607
+
{ 0x4, 0x12, 0x1, 0, 0x0b830000, 1, 0x00000000 },
1608
+
{ 0x4, 0x17, 0x0, 0, 0x0b640000, 0, 0x00000000 },
1609
+
{ 0x4, 0x17, 0x1, 0, 0x0be40000, 1, 0x00000000 },
1610
+
{ 0x4, 0x18, 0x0, 0, 0x0b600000, 0, 0x00000000 },
1611
+
{ 0x4, 0x18, 0x1, 0, 0x0be00000, 1, 0x00000000 },
1612
+
{ 0x4, 0x18, 0x2, 0, 0x00000000, 0, 0x00000000 },
1613
+
{ 0x4, 0x18, 0x3, 0, 0x00000000, 0, 0x00000000 }
1614
+
};
1615
+
1616
+
static void cbbcentralnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
1617
+
{
1618
+
info->initflow = FIELD_GET(CBB_NOC_INITFLOW, routeid);
1619
+
info->targflow = FIELD_GET(CBB_NOC_TARGFLOW, routeid);
1620
+
info->targ_subrange = FIELD_GET(CBB_NOC_TARG_SUBRANGE, routeid);
1621
+
info->seqid = FIELD_GET(CBB_NOC_SEQID, routeid);
1622
+
}
1623
+
1624
+
static void bpmpnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
1625
+
{
1626
+
info->initflow = FIELD_GET(BPMP_NOC_INITFLOW, routeid);
1627
+
info->targflow = FIELD_GET(BPMP_NOC_TARGFLOW, routeid);
1628
+
info->targ_subrange = FIELD_GET(BPMP_NOC_TARG_SUBRANGE, routeid);
1629
+
info->seqid = FIELD_GET(BPMP_NOC_SEQID, routeid);
1630
+
}
1631
+
1632
+
static void aonnoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
1633
+
{
1634
+
info->initflow = FIELD_GET(AON_NOC_INITFLOW, routeid);
1635
+
info->targflow = FIELD_GET(AON_NOC_TARGFLOW, routeid);
1636
+
info->targ_subrange = FIELD_GET(AON_NOC_TARG_SUBRANGE, routeid);
1637
+
info->seqid = FIELD_GET(AON_NOC_SEQID, routeid);
1638
+
}
1639
+
1640
+
static void scenoc_parse_routeid(struct tegra194_cbb_aperture *info, u64 routeid)
1641
+
{
1642
+
info->initflow = FIELD_GET(SCE_NOC_INITFLOW, routeid);
1643
+
info->targflow = FIELD_GET(SCE_NOC_TARGFLOW, routeid);
1644
+
info->targ_subrange = FIELD_GET(SCE_NOC_TARG_SUBRANGE, routeid);
1645
+
info->seqid = FIELD_GET(SCE_NOC_SEQID, routeid);
1646
+
}
1647
+
1648
+
static void cbbcentralnoc_parse_userbits(struct tegra194_cbb_userbits *usrbits, u32 elog_5)
1649
+
{
1650
+
usrbits->axcache = FIELD_GET(CBB_NOC_AXCACHE, elog_5);
1651
+
usrbits->non_mod = FIELD_GET(CBB_NOC_NON_MOD, elog_5);
1652
+
usrbits->axprot = FIELD_GET(CBB_NOC_AXPROT, elog_5);
1653
+
usrbits->falconsec = FIELD_GET(CBB_NOC_FALCONSEC, elog_5);
1654
+
usrbits->grpsec = FIELD_GET(CBB_NOC_GRPSEC, elog_5);
1655
+
usrbits->vqc = FIELD_GET(CBB_NOC_VQC, elog_5);
1656
+
usrbits->mstr_id = FIELD_GET(CBB_NOC_MSTR_ID, elog_5) - 1;
1657
+
usrbits->axi_id = FIELD_GET(CBB_NOC_AXI_ID, elog_5);
1658
+
}
1659
+
1660
+
static void clusternoc_parse_userbits(struct tegra194_cbb_userbits *usrbits, u32 elog_5)
1661
+
{
1662
+
usrbits->axcache = FIELD_GET(CLUSTER_NOC_AXCACHE, elog_5);
1663
+
usrbits->axprot = FIELD_GET(CLUSTER_NOC_AXCACHE, elog_5);
1664
+
usrbits->falconsec = FIELD_GET(CLUSTER_NOC_FALCONSEC, elog_5);
1665
+
usrbits->grpsec = FIELD_GET(CLUSTER_NOC_GRPSEC, elog_5);
1666
+
usrbits->vqc = FIELD_GET(CLUSTER_NOC_VQC, elog_5);
1667
+
usrbits->mstr_id = FIELD_GET(CLUSTER_NOC_MSTR_ID, elog_5) - 1;
1668
+
}
1669
+
1670
+
static void tegra194_cbb_fault_enable(struct tegra_cbb *cbb)
1671
+
{
1672
+
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
1673
+
1674
+
writel(1, priv->regs + ERRLOGGER_0_FAULTEN_0);
1675
+
writel(1, priv->regs + ERRLOGGER_1_FAULTEN_0);
1676
+
writel(1, priv->regs + ERRLOGGER_2_FAULTEN_0);
1677
+
}
1678
+
1679
+
static void tegra194_cbb_stall_enable(struct tegra_cbb *cbb)
1680
+
{
1681
+
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
1682
+
1683
+
writel(1, priv->regs + ERRLOGGER_0_STALLEN_0);
1684
+
writel(1, priv->regs + ERRLOGGER_1_STALLEN_0);
1685
+
writel(1, priv->regs + ERRLOGGER_2_STALLEN_0);
1686
+
}
1687
+
1688
+
static void tegra194_cbb_error_clear(struct tegra_cbb *cbb)
1689
+
{
1690
+
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
1691
+
1692
+
writel(1, priv->regs + ERRLOGGER_0_ERRCLR_0);
1693
+
writel(1, priv->regs + ERRLOGGER_1_ERRCLR_0);
1694
+
writel(1, priv->regs + ERRLOGGER_2_ERRCLR_0);
1695
+
dsb(sy);
1696
+
}
1697
+
1698
+
static u32 tegra194_cbb_get_status(struct tegra_cbb *cbb)
1699
+
{
1700
+
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
1701
+
u32 value;
1702
+
1703
+
value = readl(priv->regs + ERRLOGGER_0_ERRVLD_0);
1704
+
value |= (readl(priv->regs + ERRLOGGER_1_ERRVLD_0) << 1);
1705
+
value |= (readl(priv->regs + ERRLOGGER_2_ERRVLD_0) << 2);
1706
+
1707
+
dsb(sy);
1708
+
return value;
1709
+
}
1710
+
1711
+
static u32 tegra194_axi2apb_status(void __iomem *addr)
1712
+
{
1713
+
u32 value;
1714
+
1715
+
value = readl(addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
1716
+
writel(0xffffffff, addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
1717
+
1718
+
return value;
1719
+
}
1720
+
1721
+
static bool tegra194_axi2apb_fatal(struct seq_file *file, unsigned int bridge, u32 status)
1722
+
{
1723
+
bool is_fatal = true;
1724
+
size_t i;
1725
+
1726
+
for (i = 0; i < ARRAY_SIZE(tegra194_axi2apb_error); i++) {
1727
+
if (status & BIT(i)) {
1728
+
tegra_cbb_print_err(file, "\t AXI2APB_%d bridge error: %s\n",
1729
+
bridge + 1, tegra194_axi2apb_error[i]);
1730
+
if (strstr(tegra194_axi2apb_error[i], "Firewall"))
1731
+
is_fatal = false;
1732
+
}
1733
+
}
1734
+
1735
+
return is_fatal;
1736
+
}
1737
+
1738
+
/*
1739
+
* Fetch InitlocalAddress from NOC Aperture lookup table
1740
+
* using Targflow, Targsubrange
1741
+
*/
1742
+
static u32 get_init_localaddress(const struct tegra194_cbb_aperture *info,
1743
+
const struct tegra194_cbb_aperture *aper, unsigned int max)
1744
+
{
1745
+
unsigned int t_f = 0, t_sr = 0;
1746
+
u32 addr = 0;
1747
+
1748
+
for (t_f = 0; t_f < max; t_f++) {
1749
+
if (aper[t_f].targflow == info->targflow) {
1750
+
t_sr = t_f;
1751
+
1752
+
do {
1753
+
if (aper[t_sr].targ_subrange == info->targ_subrange) {
1754
+
addr = aper[t_sr].init_localaddress;
1755
+
return addr;
1756
+
}
1757
+
1758
+
if (t_sr >= max)
1759
+
return 0;
1760
+
1761
+
t_sr++;
1762
+
} while (aper[t_sr].targflow == aper[t_sr - 1].targflow);
1763
+
1764
+
t_f = t_sr;
1765
+
}
1766
+
}
1767
+
1768
+
return addr;
1769
+
}
1770
+
1771
+
static void print_errlog5(struct seq_file *file, struct tegra194_cbb *cbb)
1772
+
{
1773
+
struct tegra194_cbb_userbits userbits;
1774
+
1775
+
cbb->noc->parse_userbits(&userbits, cbb->errlog5);
1776
+
1777
+
if (!strcmp(cbb->noc->name, "cbb-noc")) {
1778
+
tegra_cbb_print_err(file, "\t Non-Modify\t\t: %#x\n", userbits.non_mod);
1779
+
tegra_cbb_print_err(file, "\t AXI ID\t\t: %#x\n", userbits.axi_id);
1780
+
}
1781
+
1782
+
tegra_cbb_print_err(file, "\t Master ID\t\t: %s\n",
1783
+
cbb->noc->master_id[userbits.mstr_id]);
1784
+
tegra_cbb_print_err(file, "\t Security Group(GRPSEC): %#x\n", userbits.grpsec);
1785
+
tegra_cbb_print_cache(file, userbits.axcache);
1786
+
tegra_cbb_print_prot(file, userbits.axprot);
1787
+
tegra_cbb_print_err(file, "\t FALCONSEC\t\t: %#x\n", userbits.falconsec);
1788
+
tegra_cbb_print_err(file, "\t Virtual Queuing Channel(VQC): %#x\n", userbits.vqc);
1789
+
}
1790
+
1791
+
/*
1792
+
* Fetch Base Address/InitlocalAddress from NOC aperture lookup table using TargFlow &
1793
+
* Targ_subRange extracted from RouteId. Perform address reconstruction as below:
1794
+
*
1795
+
* Address = Base Address + (ErrLog3 + ErrLog4)
1796
+
*/
1797
+
static void
1798
+
print_errlog3_4(struct seq_file *file, u32 errlog3, u32 errlog4,
1799
+
const struct tegra194_cbb_aperture *info,
1800
+
const struct tegra194_cbb_aperture *aperture, unsigned int max)
1801
+
{
1802
+
u64 addr = (u64)errlog4 << 32 | errlog3;
1803
+
1804
+
/*
1805
+
* If errlog4[7] = "1", then it's a joker entry. Joker entries are a rare phenomenon and
1806
+
* such addresses are not reliable. Debugging should be done using only the RouteId
1807
+
* information.
1808
+
*/
1809
+
if (errlog4 & 0x80)
1810
+
tegra_cbb_print_err(file, "\t debug using RouteId alone as below address is a "
1811
+
"joker entry and not reliable");
1812
+
1813
+
addr += get_init_localaddress(info, aperture, max);
1814
+
1815
+
tegra_cbb_print_err(file, "\t Address accessed\t: %#llx\n", addr);
1816
+
}
1817
+
1818
+
/*
1819
+
* Get RouteId from ErrLog1+ErrLog2 registers and fetch values of
1820
+
* InitFlow, TargFlow, Targ_subRange and SeqId values from RouteId
1821
+
*/
1822
+
static void
1823
+
print_errlog1_2(struct seq_file *file, struct tegra194_cbb *cbb,
1824
+
struct tegra194_cbb_aperture *info)
1825
+
{
1826
+
u64 routeid = (u64)cbb->errlog2 << 32 | cbb->errlog1;
1827
+
u32 seqid = 0;
1828
+
1829
+
tegra_cbb_print_err(file, "\t RouteId\t\t: %#llx\n", routeid);
1830
+
1831
+
cbb->noc->parse_routeid(info, routeid);
1832
+
1833
+
tegra_cbb_print_err(file, "\t InitFlow\t\t: %s\n",
1834
+
cbb->noc->routeid_initflow[info->initflow]);
1835
+
1836
+
tegra_cbb_print_err(file, "\t Targflow\t\t: %s\n",
1837
+
cbb->noc->routeid_targflow[info->targflow]);
1838
+
1839
+
tegra_cbb_print_err(file, "\t TargSubRange\t\t: %d\n", info->targ_subrange);
1840
+
tegra_cbb_print_err(file, "\t SeqId\t\t\t: %d\n", seqid);
1841
+
}
1842
+
1843
+
/*
1844
+
* Print transcation type, error code and description from ErrLog0 for all
1845
+
* errors. For NOC slave errors, all relevant error info is printed using
1846
+
* ErrLog0 only. But additional information is printed for errors from
1847
+
* APB slaves because for them:
1848
+
* - All errors are logged as SLV(slave) errors due to APB having only single
1849
+
* bit pslverr to report all errors.
1850
+
* - Exact cause is printed by reading DMAAPB_X_RAW_INTERRUPT_STATUS register.
1851
+
* - The driver prints information showing AXI2APB bridge and exact error
1852
+
* only if there is error in any AXI2APB slave.
1853
+
* - There is still no way to disambiguate a DEC error from SLV error type.
1854
+
*/
1855
+
static bool print_errlog0(struct seq_file *file, struct tegra194_cbb *cbb)
1856
+
{
1857
+
struct tegra194_cbb_packet_header hdr;
1858
+
bool is_fatal = true;
1859
+
1860
+
hdr.lock = cbb->errlog0 & 0x1;
1861
+
hdr.opc = FIELD_GET(CBB_ERR_OPC, cbb->errlog0);
1862
+
hdr.errcode = FIELD_GET(CBB_ERR_ERRCODE, cbb->errlog0);
1863
+
hdr.len1 = FIELD_GET(CBB_ERR_LEN1, cbb->errlog0);
1864
+
hdr.format = (cbb->errlog0 >> 31);
1865
+
1866
+
tegra_cbb_print_err(file, "\t Transaction Type\t: %s\n",
1867
+
tegra194_cbb_trantype[hdr.opc]);
1868
+
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
1869
+
tegra194_cbb_errors[hdr.errcode].code);
1870
+
tegra_cbb_print_err(file, "\t Error Source\t\t: %s\n",
1871
+
tegra194_cbb_errors[hdr.errcode].source);
1872
+
tegra_cbb_print_err(file, "\t Error Description\t: %s\n",
1873
+
tegra194_cbb_errors[hdr.errcode].desc);
1874
+
1875
+
/*
1876
+
* Do not crash system for errors which are only notifications to indicate a transaction
1877
+
* was not allowed to be attempted.
1878
+
*/
1879
+
if (!strcmp(tegra194_cbb_errors[hdr.errcode].code, "SEC") ||
1880
+
!strcmp(tegra194_cbb_errors[hdr.errcode].code, "DEC") ||
1881
+
!strcmp(tegra194_cbb_errors[hdr.errcode].code, "UNS") ||
1882
+
!strcmp(tegra194_cbb_errors[hdr.errcode].code, "DISC")) {
1883
+
is_fatal = false;
1884
+
} else if (!strcmp(tegra194_cbb_errors[hdr.errcode].code, "SLV") &&
1885
+
cbb->num_bridges > 0) {
1886
+
unsigned int i;
1887
+
u32 status;
1888
+
1889
+
/* For all SLV errors, read DMAAPB_X_RAW_INTERRUPT_STATUS
1890
+
* register to get error status for all AXI2APB bridges.
1891
+
* Print bridge details if a bit is set in a bridge's
1892
+
* status register due to error in a APB slave connected
1893
+
* to that bridge. For other NOC slaves, none of the status
1894
+
* register will be set.
1895
+
*/
1896
+
1897
+
for (i = 0; i < cbb->num_bridges; i++) {
1898
+
status = tegra194_axi2apb_status(cbb->bridges[i].base);
1899
+
1900
+
if (status)
1901
+
is_fatal = tegra194_axi2apb_fatal(file, i, status);
1902
+
}
1903
+
}
1904
+
1905
+
tegra_cbb_print_err(file, "\t Packet header Lock\t: %d\n", hdr.lock);
1906
+
tegra_cbb_print_err(file, "\t Packet header Len1\t: %d\n", hdr.len1);
1907
+
1908
+
if (hdr.format)
1909
+
tegra_cbb_print_err(file, "\t NOC protocol version\t: %s\n",
1910
+
"version >= 2.7");
1911
+
else
1912
+
tegra_cbb_print_err(file, "\t NOC protocol version\t: %s\n",
1913
+
"version < 2.7");
1914
+
1915
+
return is_fatal;
1916
+
}
1917
+
1918
+
/*
1919
+
* Print debug information about failed transaction using
1920
+
* ErrLog registers of error loggger having ErrVld set
1921
+
*/
1922
+
static bool print_errloggerX_info(struct seq_file *file, struct tegra194_cbb *cbb,
1923
+
int errloggerX)
1924
+
{
1925
+
struct tegra194_cbb_aperture info = { 0, };
1926
+
bool is_fatal = true;
1927
+
1928
+
tegra_cbb_print_err(file, "\tError Logger\t\t: %d\n", errloggerX);
1929
+
1930
+
if (errloggerX == 0) {
1931
+
cbb->errlog0 = readl(cbb->regs + ERRLOGGER_0_ERRLOG0_0);
1932
+
cbb->errlog1 = readl(cbb->regs + ERRLOGGER_0_ERRLOG1_0);
1933
+
cbb->errlog2 = readl(cbb->regs + ERRLOGGER_0_RSVD_00_0);
1934
+
cbb->errlog3 = readl(cbb->regs + ERRLOGGER_0_ERRLOG3_0);
1935
+
cbb->errlog4 = readl(cbb->regs + ERRLOGGER_0_ERRLOG4_0);
1936
+
cbb->errlog5 = readl(cbb->regs + ERRLOGGER_0_ERRLOG5_0);
1937
+
} else if (errloggerX == 1) {
1938
+
cbb->errlog0 = readl(cbb->regs + ERRLOGGER_1_ERRLOG0_0);
1939
+
cbb->errlog1 = readl(cbb->regs + ERRLOGGER_1_ERRLOG1_0);
1940
+
cbb->errlog2 = readl(cbb->regs + ERRLOGGER_1_RSVD_00_0);
1941
+
cbb->errlog3 = readl(cbb->regs + ERRLOGGER_1_ERRLOG3_0);
1942
+
cbb->errlog4 = readl(cbb->regs + ERRLOGGER_1_ERRLOG4_0);
1943
+
cbb->errlog5 = readl(cbb->regs + ERRLOGGER_1_ERRLOG5_0);
1944
+
} else if (errloggerX == 2) {
1945
+
cbb->errlog0 = readl(cbb->regs + ERRLOGGER_2_ERRLOG0_0);
1946
+
cbb->errlog1 = readl(cbb->regs + ERRLOGGER_2_ERRLOG1_0);
1947
+
cbb->errlog2 = readl(cbb->regs + ERRLOGGER_2_RSVD_00_0);
1948
+
cbb->errlog3 = readl(cbb->regs + ERRLOGGER_2_ERRLOG3_0);
1949
+
cbb->errlog4 = readl(cbb->regs + ERRLOGGER_2_ERRLOG4_0);
1950
+
cbb->errlog5 = readl(cbb->regs + ERRLOGGER_2_ERRLOG5_0);
1951
+
}
1952
+
1953
+
tegra_cbb_print_err(file, "\tErrLog0\t\t\t: %#x\n", cbb->errlog0);
1954
+
is_fatal = print_errlog0(file, cbb);
1955
+
1956
+
tegra_cbb_print_err(file, "\tErrLog1\t\t\t: %#x\n", cbb->errlog1);
1957
+
tegra_cbb_print_err(file, "\tErrLog2\t\t\t: %#x\n", cbb->errlog2);
1958
+
print_errlog1_2(file, cbb, &info);
1959
+
1960
+
tegra_cbb_print_err(file, "\tErrLog3\t\t\t: %#x\n", cbb->errlog3);
1961
+
tegra_cbb_print_err(file, "\tErrLog4\t\t\t: %#x\n", cbb->errlog4);
1962
+
print_errlog3_4(file, cbb->errlog3, cbb->errlog4, &info, cbb->noc->noc_aperture,
1963
+
cbb->noc->max_aperture);
1964
+
1965
+
tegra_cbb_print_err(file, "\tErrLog5\t\t\t: %#x\n", cbb->errlog5);
1966
+
1967
+
if (cbb->errlog5)
1968
+
print_errlog5(file, cbb);
1969
+
1970
+
return is_fatal;
1971
+
}
1972
+
1973
+
static bool print_errlog(struct seq_file *file, struct tegra194_cbb *cbb, u32 errvld)
1974
+
{
1975
+
bool is_fatal = true;
1976
+
1977
+
pr_crit("**************************************\n");
1978
+
pr_crit("CPU:%d, Error:%s\n", smp_processor_id(), cbb->noc->name);
1979
+
1980
+
if (errvld & 0x1)
1981
+
is_fatal = print_errloggerX_info(file, cbb, 0);
1982
+
else if (errvld & 0x2)
1983
+
is_fatal = print_errloggerX_info(file, cbb, 1);
1984
+
else if (errvld & 0x4)
1985
+
is_fatal = print_errloggerX_info(file, cbb, 2);
1986
+
1987
+
tegra_cbb_error_clear(&cbb->base);
1988
+
tegra_cbb_print_err(file, "\t**************************************\n");
1989
+
return is_fatal;
1990
+
}
1991
+
1992
+
#ifdef CONFIG_DEBUG_FS
1993
+
static DEFINE_MUTEX(cbb_err_mutex);
1994
+
1995
+
static int tegra194_cbb_debugfs_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
1996
+
{
1997
+
struct tegra_cbb *noc;
1998
+
1999
+
mutex_lock(&cbb_err_mutex);
2000
+
2001
+
list_for_each_entry(noc, &cbb_list, node) {
2002
+
struct tegra194_cbb *priv = to_tegra194_cbb(noc);
2003
+
u32 status;
2004
+
2005
+
status = tegra_cbb_get_status(noc);
2006
+
if (status)
2007
+
print_errlog(file, priv, status);
2008
+
}
2009
+
2010
+
mutex_unlock(&cbb_err_mutex);
2011
+
2012
+
return 0;
2013
+
}
2014
+
#endif
2015
+
2016
+
/*
2017
+
* Handler for CBB errors from different initiators
2018
+
*/
2019
+
static irqreturn_t tegra194_cbb_err_isr(int irq, void *data)
2020
+
{
2021
+
bool is_inband_err = false, is_fatal = false;
2022
+
//struct tegra194_cbb *cbb = data;
2023
+
struct tegra_cbb *noc;
2024
+
unsigned long flags;
2025
+
u8 mstr_id = 0;
2026
+
2027
+
spin_lock_irqsave(&cbb_lock, flags);
2028
+
2029
+
/* XXX only process interrupts for "cbb" instead of iterating over all NOCs? */
2030
+
list_for_each_entry(noc, &cbb_list, node) {
2031
+
struct tegra194_cbb *priv = to_tegra194_cbb(noc);
2032
+
u32 status = 0;
2033
+
2034
+
status = tegra_cbb_get_status(noc);
2035
+
2036
+
if (status && ((irq == priv->sec_irq) || (irq == priv->nonsec_irq))) {
2037
+
tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@%llx, irq=%d\n",
2038
+
smp_processor_id(), priv->noc->name, priv->res->start,
2039
+
irq);
2040
+
2041
+
mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->errlog5) - 1;
2042
+
is_fatal = print_errlog(NULL, priv, status);
2043
+
2044
+
/*
2045
+
* If illegal request is from CCPLEX(0x1)
2046
+
* initiator then call BUG() to crash system.
2047
+
*/
2048
+
if ((mstr_id == 0x1) && priv->noc->erd_mask_inband_err)
2049
+
is_inband_err = 1;
2050
+
}
2051
+
}
2052
+
2053
+
spin_unlock_irqrestore(&cbb_lock, flags);
2054
+
2055
+
if (is_inband_err) {
2056
+
if (is_fatal)
2057
+
BUG();
2058
+
else
2059
+
WARN(true, "Warning due to CBB Error\n");
2060
+
}
2061
+
2062
+
return IRQ_HANDLED;
2063
+
}
2064
+
2065
+
/*
2066
+
* Register handler for CBB_NONSECURE & CBB_SECURE interrupts
2067
+
* for reporting CBB errors
2068
+
*/
2069
+
static int tegra194_cbb_interrupt_enable(struct tegra_cbb *cbb)
2070
+
{
2071
+
struct tegra194_cbb *priv = to_tegra194_cbb(cbb);
2072
+
struct device *dev = cbb->dev;
2073
+
int err;
2074
+
2075
+
if (priv->sec_irq) {
2076
+
err = devm_request_irq(dev, priv->sec_irq, tegra194_cbb_err_isr, 0, dev_name(dev),
2077
+
priv);
2078
+
if (err) {
2079
+
dev_err(dev, "failed to register interrupt %u: %d\n", priv->sec_irq, err);
2080
+
return err;
2081
+
}
2082
+
}
2083
+
2084
+
if (priv->nonsec_irq) {
2085
+
err = devm_request_irq(dev, priv->nonsec_irq, tegra194_cbb_err_isr, 0,
2086
+
dev_name(dev), priv);
2087
+
if (err) {
2088
+
dev_err(dev, "failed to register interrupt %u: %d\n", priv->nonsec_irq,
2089
+
err);
2090
+
return err;
2091
+
}
2092
+
}
2093
+
2094
+
return 0;
2095
+
}
2096
+
2097
+
static void tegra194_cbb_error_enable(struct tegra_cbb *cbb)
2098
+
{
2099
+
/*
2100
+
* Set “StallEn=1” to enable queuing of error packets till
2101
+
* first is served & cleared
2102
+
*/
2103
+
tegra_cbb_stall_enable(cbb);
2104
+
2105
+
/* set “FaultEn=1” to enable error reporting signal “Fault” */
2106
+
tegra_cbb_fault_enable(cbb);
2107
+
}
2108
+
2109
+
static const struct tegra_cbb_ops tegra194_cbb_ops = {
2110
+
.get_status = tegra194_cbb_get_status,
2111
+
.error_clear = tegra194_cbb_error_clear,
2112
+
.fault_enable = tegra194_cbb_fault_enable,
2113
+
.stall_enable = tegra194_cbb_stall_enable,
2114
+
.error_enable = tegra194_cbb_error_enable,
2115
+
.interrupt_enable = tegra194_cbb_interrupt_enable,
2116
+
#ifdef CONFIG_DEBUG_FS
2117
+
.debugfs_show = tegra194_cbb_debugfs_show,
2118
+
#endif
2119
+
};
2120
+
2121
+
static struct tegra194_cbb_noc_data tegra194_cbb_central_noc_data = {
2122
+
.name = "cbb-noc",
2123
+
.erd_mask_inband_err = true,
2124
+
.master_id = tegra194_master_id,
2125
+
.noc_aperture = tegra194_cbbcentralnoc_apert_lookup,
2126
+
.max_aperture = ARRAY_SIZE(tegra194_cbbcentralnoc_apert_lookup),
2127
+
.routeid_initflow = tegra194_cbbcentralnoc_routeid_initflow,
2128
+
.routeid_targflow = tegra194_cbbcentralnoc_routeid_targflow,
2129
+
.parse_routeid = cbbcentralnoc_parse_routeid,
2130
+
.parse_userbits = cbbcentralnoc_parse_userbits
2131
+
};
2132
+
2133
+
static struct tegra194_cbb_noc_data tegra194_aon_noc_data = {
2134
+
.name = "aon-noc",
2135
+
.erd_mask_inband_err = false,
2136
+
.master_id = tegra194_master_id,
2137
+
.noc_aperture = tegra194_aonnoc_aperture_lookup,
2138
+
.max_aperture = ARRAY_SIZE(tegra194_aonnoc_aperture_lookup),
2139
+
.routeid_initflow = tegra194_aonnoc_routeid_initflow,
2140
+
.routeid_targflow = tegra194_aonnoc_routeid_targflow,
2141
+
.parse_routeid = aonnoc_parse_routeid,
2142
+
.parse_userbits = clusternoc_parse_userbits
2143
+
};
2144
+
2145
+
static struct tegra194_cbb_noc_data tegra194_bpmp_noc_data = {
2146
+
.name = "bpmp-noc",
2147
+
.erd_mask_inband_err = false,
2148
+
.master_id = tegra194_master_id,
2149
+
.noc_aperture = tegra194_bpmpnoc_apert_lookup,
2150
+
.max_aperture = ARRAY_SIZE(tegra194_bpmpnoc_apert_lookup),
2151
+
.routeid_initflow = tegra194_bpmpnoc_routeid_initflow,
2152
+
.routeid_targflow = tegra194_bpmpnoc_routeid_targflow,
2153
+
.parse_routeid = bpmpnoc_parse_routeid,
2154
+
.parse_userbits = clusternoc_parse_userbits
2155
+
};
2156
+
2157
+
static struct tegra194_cbb_noc_data tegra194_rce_noc_data = {
2158
+
.name = "rce-noc",
2159
+
.erd_mask_inband_err = false,
2160
+
.master_id = tegra194_master_id,
2161
+
.noc_aperture = tegra194_scenoc_apert_lookup,
2162
+
.max_aperture = ARRAY_SIZE(tegra194_scenoc_apert_lookup),
2163
+
.routeid_initflow = tegra194_scenoc_routeid_initflow,
2164
+
.routeid_targflow = tegra194_scenoc_routeid_targflow,
2165
+
.parse_routeid = scenoc_parse_routeid,
2166
+
.parse_userbits = clusternoc_parse_userbits
2167
+
};
2168
+
2169
+
static struct tegra194_cbb_noc_data tegra194_sce_noc_data = {
2170
+
.name = "sce-noc",
2171
+
.erd_mask_inband_err = false,
2172
+
.master_id = tegra194_master_id,
2173
+
.noc_aperture = tegra194_scenoc_apert_lookup,
2174
+
.max_aperture = ARRAY_SIZE(tegra194_scenoc_apert_lookup),
2175
+
.routeid_initflow = tegra194_scenoc_routeid_initflow,
2176
+
.routeid_targflow = tegra194_scenoc_routeid_targflow,
2177
+
.parse_routeid = scenoc_parse_routeid,
2178
+
.parse_userbits = clusternoc_parse_userbits
2179
+
};
2180
+
2181
+
static const struct of_device_id tegra194_cbb_match[] = {
2182
+
{ .compatible = "nvidia,tegra194-cbb-noc", .data = &tegra194_cbb_central_noc_data },
2183
+
{ .compatible = "nvidia,tegra194-aon-noc", .data = &tegra194_aon_noc_data },
2184
+
{ .compatible = "nvidia,tegra194-bpmp-noc", .data = &tegra194_bpmp_noc_data },
2185
+
{ .compatible = "nvidia,tegra194-rce-noc", .data = &tegra194_rce_noc_data },
2186
+
{ .compatible = "nvidia,tegra194-sce-noc", .data = &tegra194_sce_noc_data },
2187
+
{ /* sentinel */ }
2188
+
};
2189
+
MODULE_DEVICE_TABLE(of, tegra194_cbb_match);
2190
+
2191
+
static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node *np)
2192
+
{
2193
+
struct tegra_cbb *entry;
2194
+
struct resource res;
2195
+
unsigned long flags;
2196
+
unsigned int i;
2197
+
int err;
2198
+
2199
+
spin_lock_irqsave(&cbb_lock, flags);
2200
+
2201
+
list_for_each_entry(entry, &cbb_list, node) {
2202
+
struct tegra194_cbb *priv = to_tegra194_cbb(entry);
2203
+
2204
+
if (priv->bridges) {
2205
+
cbb->num_bridges = priv->num_bridges;
2206
+
cbb->bridges = priv->bridges;
2207
+
break;
2208
+
}
2209
+
}
2210
+
2211
+
spin_unlock_irqrestore(&cbb_lock, flags);
2212
+
2213
+
if (!cbb->bridges) {
2214
+
while (of_address_to_resource(np, cbb->num_bridges, &res) == 0)
2215
+
cbb->num_bridges++;
2216
+
2217
+
cbb->bridges = devm_kcalloc(cbb->base.dev, cbb->num_bridges,
2218
+
sizeof(*cbb->bridges), GFP_KERNEL);
2219
+
if (!cbb->bridges)
2220
+
return -ENOMEM;
2221
+
2222
+
for (i = 0; i < cbb->num_bridges; i++) {
2223
+
err = of_address_to_resource(np, i, &cbb->bridges[i].res);
2224
+
if (err < 0)
2225
+
return err;
2226
+
2227
+
cbb->bridges[i].base = devm_ioremap_resource(cbb->base.dev,
2228
+
&cbb->bridges[i].res);
2229
+
if (IS_ERR(cbb->bridges[i].base)) {
2230
+
dev_err(cbb->base.dev, "failed to map AXI2APB range\n");
2231
+
return PTR_ERR(cbb->bridges[i].base);
2232
+
}
2233
+
}
2234
+
}
2235
+
2236
+
if (cbb->num_bridges > 0) {
2237
+
dev_dbg(cbb->base.dev, "AXI2APB bridge info present:\n");
2238
+
2239
+
for (i = 0; i < cbb->num_bridges; i++)
2240
+
dev_dbg(cbb->base.dev, " %u: %pR\n", i, &cbb->bridges[i].res);
2241
+
}
2242
+
2243
+
return 0;
2244
+
}
2245
+
2246
+
static int tegra194_cbb_probe(struct platform_device *pdev)
2247
+
{
2248
+
const struct tegra194_cbb_noc_data *noc;
2249
+
struct tegra194_cbb *cbb;
2250
+
struct device_node *np;
2251
+
unsigned long flags;
2252
+
int err;
2253
+
2254
+
noc = of_device_get_match_data(&pdev->dev);
2255
+
2256
+
if (noc->erd_mask_inband_err) {
2257
+
/*
2258
+
* Set Error Response Disable(ERD) bit to mask SError/inband
2259
+
* error and only trigger interrupts for illegal access from
2260
+
* CCPLEX initiator.
2261
+
*/
2262
+
err = tegra194_miscreg_mask_serror();
2263
+
if (err) {
2264
+
dev_err(&pdev->dev, "couldn't mask inband errors\n");
2265
+
return err;
2266
+
}
2267
+
}
2268
+
2269
+
cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
2270
+
if (!cbb)
2271
+
return -ENOMEM;
2272
+
2273
+
INIT_LIST_HEAD(&cbb->base.node);
2274
+
cbb->base.ops = &tegra194_cbb_ops;
2275
+
cbb->base.dev = &pdev->dev;
2276
+
cbb->noc = noc;
2277
+
2278
+
cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);
2279
+
if (IS_ERR(cbb->regs))
2280
+
return PTR_ERR(cbb->regs);
2281
+
2282
+
err = tegra_cbb_get_irq(pdev, &cbb->nonsec_irq, &cbb->sec_irq);
2283
+
if (err)
2284
+
return err;
2285
+
2286
+
np = of_parse_phandle(pdev->dev.of_node, "nvidia,axi2apb", 0);
2287
+
if (np) {
2288
+
err = tegra194_cbb_get_bridges(cbb, np);
2289
+
of_node_put(np);
2290
+
if (err < 0)
2291
+
return err;
2292
+
}
2293
+
2294
+
platform_set_drvdata(pdev, cbb);
2295
+
2296
+
spin_lock_irqsave(&cbb_lock, flags);
2297
+
list_add(&cbb->base.node, &cbb_list);
2298
+
spin_unlock_irqrestore(&cbb_lock, flags);
2299
+
2300
+
return tegra_cbb_register(&cbb->base);
2301
+
}
2302
+
2303
+
static int tegra194_cbb_remove(struct platform_device *pdev)
2304
+
{
2305
+
struct tegra194_cbb *cbb = platform_get_drvdata(pdev);
2306
+
struct tegra_cbb *noc, *tmp;
2307
+
unsigned long flags;
2308
+
2309
+
spin_lock_irqsave(&cbb_lock, flags);
2310
+
2311
+
list_for_each_entry_safe(noc, tmp, &cbb_list, node) {
2312
+
struct tegra194_cbb *priv = to_tegra194_cbb(noc);
2313
+
2314
+
if (cbb->res->start == priv->res->start) {
2315
+
list_del(&noc->node);
2316
+
break;
2317
+
}
2318
+
}
2319
+
2320
+
spin_unlock_irqrestore(&cbb_lock, flags);
2321
+
2322
+
return 0;
2323
+
}
2324
+
2325
+
static int __maybe_unused tegra194_cbb_resume_noirq(struct device *dev)
2326
+
{
2327
+
struct tegra194_cbb *cbb = dev_get_drvdata(dev);
2328
+
2329
+
tegra194_cbb_error_enable(&cbb->base);
2330
+
dsb(sy);
2331
+
2332
+
dev_dbg(dev, "%s resumed\n", cbb->noc->name);
2333
+
return 0;
2334
+
}
2335
+
2336
+
static const struct dev_pm_ops tegra194_cbb_pm = {
2337
+
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra194_cbb_resume_noirq)
2338
+
};
2339
+
2340
+
static struct platform_driver tegra194_cbb_driver = {
2341
+
.probe = tegra194_cbb_probe,
2342
+
.remove = tegra194_cbb_remove,
2343
+
.driver = {
2344
+
.name = "tegra194-cbb",
2345
+
.of_match_table = of_match_ptr(tegra194_cbb_match),
2346
+
.pm = &tegra194_cbb_pm,
2347
+
},
2348
+
};
2349
+
2350
+
static int __init tegra194_cbb_init(void)
2351
+
{
2352
+
return platform_driver_register(&tegra194_cbb_driver);
2353
+
}
2354
+
pure_initcall(tegra194_cbb_init);
2355
+
2356
+
static void __exit tegra194_cbb_exit(void)
2357
+
{
2358
+
platform_driver_unregister(&tegra194_cbb_driver);
2359
+
}
2360
+
module_exit(tegra194_cbb_exit);
2361
+
2362
+
MODULE_AUTHOR("Sumit Gupta <sumitg@nvidia.com>");
2363
+
MODULE_DESCRIPTION("Control Backbone error handling driver for Tegra194");
2364
+
MODULE_LICENSE("GPL");
+1113
drivers/soc/tegra/cbb/tegra234-cbb.c
+1113
drivers/soc/tegra/cbb/tegra234-cbb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
4
+
*
5
+
* The driver handles Error's from Control Backbone(CBB) version 2.0.
6
+
* generated due to illegal accesses. The driver prints debug information
7
+
* about failed transaction on receiving interrupt from Error Notifier.
8
+
* Error types supported by CBB2.0 are:
9
+
* UNSUPPORTED_ERR, PWRDOWN_ERR, TIMEOUT_ERR, FIREWALL_ERR, DECODE_ERR,
10
+
* SLAVE_ERR
11
+
*/
12
+
13
+
#include <linux/acpi.h>
14
+
#include <linux/clk.h>
15
+
#include <linux/cpufeature.h>
16
+
#include <linux/debugfs.h>
17
+
#include <linux/module.h>
18
+
#include <linux/of.h>
19
+
#include <linux/of_device.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/device.h>
22
+
#include <linux/io.h>
23
+
#include <linux/of_irq.h>
24
+
#include <linux/of_address.h>
25
+
#include <linux/interrupt.h>
26
+
#include <linux/ioport.h>
27
+
#include <linux/version.h>
28
+
#include <soc/tegra/fuse.h>
29
+
#include <soc/tegra/tegra-cbb.h>
30
+
31
+
#define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
32
+
#define FABRIC_EN_CFG_STATUS_0_0 0x40
33
+
#define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
34
+
#define FABRIC_EN_CFG_ADDR_LOW_0 0x80
35
+
#define FABRIC_EN_CFG_ADDR_HI_0 0x84
36
+
37
+
#define FABRIC_MN_MASTER_ERR_EN_0 0x200
38
+
#define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
39
+
#define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
40
+
#define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
41
+
42
+
#define FABRIC_MN_MASTER_LOG_ERR_STATUS_0 0x300
43
+
#define FABRIC_MN_MASTER_LOG_ADDR_LOW_0 0x304
44
+
#define FABRIC_MN_MASTER_LOG_ADDR_HIGH_0 0x308
45
+
#define FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0 0x30c
46
+
#define FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0 0x310
47
+
#define FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0 0x314
48
+
#define FABRIC_MN_MASTER_LOG_USER_BITS0_0 0x318
49
+
50
+
#define AXI_SLV_TIMEOUT_STATUS_0_0 0x8
51
+
#define APB_BLOCK_TMO_STATUS_0 0xc00
52
+
#define APB_BLOCK_NUM_TMO_OFFSET 0x20
53
+
54
+
#define FAB_EM_EL_MSTRID GENMASK(29, 24)
55
+
#define FAB_EM_EL_VQC GENMASK(17, 16)
56
+
#define FAB_EM_EL_GRPSEC GENMASK(14, 8)
57
+
#define FAB_EM_EL_FALCONSEC GENMASK(1, 0)
58
+
59
+
#define FAB_EM_EL_FABID GENMASK(20, 16)
60
+
#define FAB_EM_EL_SLAVEID GENMASK(7, 0)
61
+
62
+
#define FAB_EM_EL_ACCESSID GENMASK(7, 0)
63
+
64
+
#define FAB_EM_EL_AXCACHE GENMASK(27, 24)
65
+
#define FAB_EM_EL_AXPROT GENMASK(22, 20)
66
+
#define FAB_EM_EL_BURSTLENGTH GENMASK(19, 12)
67
+
#define FAB_EM_EL_BURSTTYPE GENMASK(9, 8)
68
+
#define FAB_EM_EL_BEATSIZE GENMASK(6, 4)
69
+
#define FAB_EM_EL_ACCESSTYPE GENMASK(0, 0)
70
+
71
+
#define USRBITS_MSTR_ID GENMASK(29, 24)
72
+
73
+
#define REQ_SOCKET_ID GENMASK(27, 24)
74
+
75
+
enum tegra234_cbb_fabric_ids {
76
+
CBB_FAB_ID,
77
+
SCE_FAB_ID,
78
+
RCE_FAB_ID,
79
+
DCE_FAB_ID,
80
+
AON_FAB_ID,
81
+
PSC_FAB_ID,
82
+
BPMP_FAB_ID,
83
+
FSI_FAB_ID,
84
+
MAX_FAB_ID,
85
+
};
86
+
87
+
struct tegra234_slave_lookup {
88
+
const char *name;
89
+
unsigned int offset;
90
+
};
91
+
92
+
struct tegra234_cbb_fabric {
93
+
const char *name;
94
+
phys_addr_t off_mask_erd;
95
+
bool erd_mask_inband_err;
96
+
const char * const *master_id;
97
+
unsigned int notifier_offset;
98
+
const struct tegra_cbb_error *errors;
99
+
const struct tegra234_slave_lookup *slave_map;
100
+
};
101
+
102
+
struct tegra234_cbb {
103
+
struct tegra_cbb base;
104
+
105
+
const struct tegra234_cbb_fabric *fabric;
106
+
struct resource *res;
107
+
void __iomem *regs;
108
+
109
+
int num_intr;
110
+
int sec_irq;
111
+
112
+
/* record */
113
+
void __iomem *mon;
114
+
unsigned int type;
115
+
u32 mask;
116
+
u64 access;
117
+
u32 mn_attr0;
118
+
u32 mn_attr1;
119
+
u32 mn_attr2;
120
+
u32 mn_user_bits;
121
+
};
122
+
123
+
static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb)
124
+
{
125
+
return container_of(cbb, struct tegra234_cbb, base);
126
+
}
127
+
128
+
static LIST_HEAD(cbb_list);
129
+
static DEFINE_SPINLOCK(cbb_lock);
130
+
131
+
static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb)
132
+
{
133
+
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
134
+
void __iomem *addr;
135
+
136
+
addr = priv->regs + priv->fabric->notifier_offset;
137
+
writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
138
+
dsb(sy);
139
+
}
140
+
141
+
static void tegra234_cbb_error_clear(struct tegra_cbb *cbb)
142
+
{
143
+
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
144
+
145
+
writel(0x3f, priv->mon + FABRIC_MN_MASTER_ERR_STATUS_0);
146
+
dsb(sy);
147
+
}
148
+
149
+
static u32 tegra234_cbb_get_status(struct tegra_cbb *cbb)
150
+
{
151
+
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
152
+
void __iomem *addr;
153
+
u32 value;
154
+
155
+
addr = priv->regs + priv->fabric->notifier_offset;
156
+
value = readl(addr + FABRIC_EN_CFG_STATUS_0_0);
157
+
dsb(sy);
158
+
159
+
return value;
160
+
}
161
+
162
+
static void tegra234_cbb_mask_serror(struct tegra234_cbb *cbb)
163
+
{
164
+
writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);
165
+
dsb(sy);
166
+
}
167
+
168
+
static u32 tegra234_cbb_get_tmo_slv(void __iomem *addr)
169
+
{
170
+
u32 timeout;
171
+
172
+
timeout = readl(addr);
173
+
return timeout;
174
+
}
175
+
176
+
static void tegra234_cbb_tmo_slv(struct seq_file *file, const char *slave, void __iomem *addr,
177
+
u32 status)
178
+
{
179
+
tegra_cbb_print_err(file, "\t %s : %#x\n", slave, status);
180
+
}
181
+
182
+
static void tegra234_cbb_lookup_apbslv(struct seq_file *file, const char *slave,
183
+
void __iomem *base)
184
+
{
185
+
unsigned int block = 0;
186
+
void __iomem *addr;
187
+
char name[64];
188
+
u32 status;
189
+
190
+
status = tegra234_cbb_get_tmo_slv(base);
191
+
if (status)
192
+
tegra_cbb_print_err(file, "\t %s_BLOCK_TMO_STATUS : %#x\n", slave, status);
193
+
194
+
while (status) {
195
+
if (status & BIT(0)) {
196
+
u32 timeout, clients, client = 0;
197
+
198
+
addr = base + APB_BLOCK_NUM_TMO_OFFSET + (block * 4);
199
+
timeout = tegra234_cbb_get_tmo_slv(addr);
200
+
clients = timeout;
201
+
202
+
while (timeout) {
203
+
if (timeout & BIT(0)) {
204
+
if (clients != 0xffffffff)
205
+
clients &= BIT(client);
206
+
207
+
sprintf(name, "%s_BLOCK%d_TMO", slave, block);
208
+
209
+
tegra234_cbb_tmo_slv(file, name, addr, clients);
210
+
}
211
+
212
+
timeout >>= 1;
213
+
client++;
214
+
}
215
+
}
216
+
217
+
status >>= 1;
218
+
block++;
219
+
}
220
+
}
221
+
222
+
static void tegra234_lookup_slave_timeout(struct seq_file *file, struct tegra234_cbb *cbb,
223
+
u8 slave_id, u8 fab_id)
224
+
{
225
+
const struct tegra234_slave_lookup *map = cbb->fabric->slave_map;
226
+
void __iomem *addr;
227
+
228
+
/*
229
+
* 1) Get slave node name and address mapping using slave_id.
230
+
* 2) Check if the timed out slave node is APB or AXI.
231
+
* 3) If AXI, then print timeout register and reset axi slave
232
+
* using <FABRIC>_SN_<>_SLV_TIMEOUT_STATUS_0_0 register.
233
+
* 4) If APB, then perform an additional lookup to find the client
234
+
* which timed out.
235
+
* a) Get block number from the index of set bit in
236
+
* <FABRIC>_SN_AXI2APB_<>_BLOCK_TMO_STATUS_0 register.
237
+
* b) Get address of register repective to block number i.e.
238
+
* <FABRIC>_SN_AXI2APB_<>_BLOCK<index-set-bit>_TMO_0.
239
+
* c) Read the register in above step to get client_id which
240
+
* timed out as per the set bits.
241
+
* d) Reset the timedout client and print details.
242
+
* e) Goto step-a till all bits are set.
243
+
*/
244
+
245
+
addr = cbb->regs + map[slave_id].offset;
246
+
247
+
if (strstr(map[slave_id].name, "AXI2APB")) {
248
+
addr += APB_BLOCK_TMO_STATUS_0;
249
+
250
+
tegra234_cbb_lookup_apbslv(file, map[slave_id].name, addr);
251
+
} else {
252
+
char name[64];
253
+
u32 status;
254
+
255
+
addr += AXI_SLV_TIMEOUT_STATUS_0_0;
256
+
257
+
status = tegra234_cbb_get_tmo_slv(addr);
258
+
if (status) {
259
+
sprintf(name, "%s_SLV_TIMEOUT_STATUS", map[slave_id].name);
260
+
tegra234_cbb_tmo_slv(file, name, addr, status);
261
+
}
262
+
}
263
+
}
264
+
265
+
static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb *cbb, u32 status,
266
+
u32 overflow)
267
+
{
268
+
unsigned int type = 0;
269
+
270
+
if (status & (status - 1))
271
+
tegra_cbb_print_err(file, "\t Multiple type of errors reported\n");
272
+
273
+
while (status) {
274
+
if (status & 0x1)
275
+
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
276
+
cbb->fabric->errors[type].code);
277
+
278
+
status >>= 1;
279
+
type++;
280
+
}
281
+
282
+
type = 0;
283
+
284
+
while (overflow) {
285
+
if (overflow & 0x1)
286
+
tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n",
287
+
cbb->fabric->errors[type].code);
288
+
289
+
overflow >>= 1;
290
+
type++;
291
+
}
292
+
}
293
+
294
+
static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
295
+
{
296
+
u8 cache_type, prot_type, burst_length, mstr_id, grpsec, vqc, falconsec, beat_size;
297
+
u8 access_type, access_id, requester_socket_id, local_socket_id, slave_id, fab_id;
298
+
char fabric_name[20];
299
+
bool is_numa = false;
300
+
u8 burst_type;
301
+
302
+
if (num_possible_nodes() > 1)
303
+
is_numa = true;
304
+
305
+
mstr_id = FIELD_GET(FAB_EM_EL_MSTRID, cbb->mn_user_bits);
306
+
vqc = FIELD_GET(FAB_EM_EL_VQC, cbb->mn_user_bits);
307
+
grpsec = FIELD_GET(FAB_EM_EL_GRPSEC, cbb->mn_user_bits);
308
+
falconsec = FIELD_GET(FAB_EM_EL_FALCONSEC, cbb->mn_user_bits);
309
+
310
+
/*
311
+
* For SOC with multiple NUMA nodes, print cross socket access
312
+
* errors only if initiator/master_id is CCPLEX, CPMU or GPU.
313
+
*/
314
+
if (is_numa) {
315
+
local_socket_id = numa_node_id();
316
+
requester_socket_id = FIELD_GET(REQ_SOCKET_ID, cbb->mn_attr2);
317
+
318
+
if (requester_socket_id != local_socket_id) {
319
+
if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))
320
+
return;
321
+
}
322
+
}
323
+
324
+
fab_id = FIELD_GET(FAB_EM_EL_FABID, cbb->mn_attr2);
325
+
slave_id = FIELD_GET(FAB_EM_EL_SLAVEID, cbb->mn_attr2);
326
+
327
+
access_id = FIELD_GET(FAB_EM_EL_ACCESSID, cbb->mn_attr1);
328
+
329
+
cache_type = FIELD_GET(FAB_EM_EL_AXCACHE, cbb->mn_attr0);
330
+
prot_type = FIELD_GET(FAB_EM_EL_AXPROT, cbb->mn_attr0);
331
+
burst_length = FIELD_GET(FAB_EM_EL_BURSTLENGTH, cbb->mn_attr0);
332
+
burst_type = FIELD_GET(FAB_EM_EL_BURSTTYPE, cbb->mn_attr0);
333
+
beat_size = FIELD_GET(FAB_EM_EL_BEATSIZE, cbb->mn_attr0);
334
+
access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, cbb->mn_attr0);
335
+
336
+
tegra_cbb_print_err(file, "\n");
337
+
tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
338
+
cbb->fabric->errors[cbb->type].code);
339
+
340
+
tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", cbb->fabric->master_id[mstr_id]);
341
+
tegra_cbb_print_err(file, "\t Address\t\t: %#llx\n", cbb->access);
342
+
343
+
tegra_cbb_print_cache(file, cache_type);
344
+
tegra_cbb_print_prot(file, prot_type);
345
+
346
+
tegra_cbb_print_err(file, "\t Access_Type\t\t: %s", (access_type) ? "Write\n" : "Read\n");
347
+
tegra_cbb_print_err(file, "\t Access_ID\t\t: %#x", access_id);
348
+
349
+
if (fab_id == PSC_FAB_ID)
350
+
strcpy(fabric_name, "psc-fabric");
351
+
else if (fab_id == FSI_FAB_ID)
352
+
strcpy(fabric_name, "fsi-fabric");
353
+
else
354
+
strcpy(fabric_name, cbb->fabric->name);
355
+
356
+
if (is_numa) {
357
+
tegra_cbb_print_err(file, "\t Requester_Socket_Id\t: %#x\n",
358
+
requester_socket_id);
359
+
tegra_cbb_print_err(file, "\t Local_Socket_Id\t: %#x\n",
360
+
local_socket_id);
361
+
tegra_cbb_print_err(file, "\t No. of NUMA_NODES\t: %#x\n",
362
+
num_possible_nodes());
363
+
}
364
+
365
+
tegra_cbb_print_err(file, "\t Fabric\t\t: %s\n", fabric_name);
366
+
tegra_cbb_print_err(file, "\t Slave_Id\t\t: %#x\n", slave_id);
367
+
tegra_cbb_print_err(file, "\t Burst_length\t\t: %#x\n", burst_length);
368
+
tegra_cbb_print_err(file, "\t Burst_type\t\t: %#x\n", burst_type);
369
+
tegra_cbb_print_err(file, "\t Beat_size\t\t: %#x\n", beat_size);
370
+
tegra_cbb_print_err(file, "\t VQC\t\t\t: %#x\n", vqc);
371
+
tegra_cbb_print_err(file, "\t GRPSEC\t\t: %#x\n", grpsec);
372
+
tegra_cbb_print_err(file, "\t FALCONSEC\t\t: %#x\n", falconsec);
373
+
374
+
if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID))
375
+
return;
376
+
377
+
if (!strcmp(cbb->fabric->errors[cbb->type].code, "TIMEOUT_ERR")) {
378
+
tegra234_lookup_slave_timeout(file, cbb, slave_id, fab_id);
379
+
return;
380
+
}
381
+
382
+
tegra_cbb_print_err(file, "\t Slave\t\t\t: %s\n", cbb->fabric->slave_map[slave_id].name);
383
+
}
384
+
385
+
static int print_errmonX_info(struct seq_file *file, struct tegra234_cbb *cbb)
386
+
{
387
+
u32 overflow, status, error;
388
+
389
+
status = readl(cbb->mon + FABRIC_MN_MASTER_ERR_STATUS_0);
390
+
if (!status) {
391
+
pr_err("Error Notifier received a spurious notification\n");
392
+
return -ENODATA;
393
+
}
394
+
395
+
if (status == 0xffffffff) {
396
+
pr_err("CBB registers returning all 1's which is invalid\n");
397
+
return -EINVAL;
398
+
}
399
+
400
+
overflow = readl(cbb->mon + FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0);
401
+
402
+
tegra234_cbb_print_error(file, cbb, status, overflow);
403
+
404
+
error = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ERR_STATUS_0);
405
+
if (!error) {
406
+
pr_info("Error Monitor doesn't have Error Logger\n");
407
+
return -EINVAL;
408
+
}
409
+
410
+
cbb->type = 0;
411
+
412
+
while (error) {
413
+
if (error & BIT(0)) {
414
+
u32 hi, lo;
415
+
416
+
hi = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ADDR_HIGH_0);
417
+
lo = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ADDR_LOW_0);
418
+
419
+
cbb->access = (u64)hi << 32 | lo;
420
+
421
+
cbb->mn_attr0 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0);
422
+
cbb->mn_attr1 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0);
423
+
cbb->mn_attr2 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0);
424
+
cbb->mn_user_bits = readl(cbb->mon + FABRIC_MN_MASTER_LOG_USER_BITS0_0);
425
+
426
+
print_errlog_err(file, cbb);
427
+
}
428
+
429
+
cbb->type++;
430
+
error >>= 1;
431
+
}
432
+
433
+
return 0;
434
+
}
435
+
436
+
static int print_err_notifier(struct seq_file *file, struct tegra234_cbb *cbb, u32 status)
437
+
{
438
+
unsigned int index = 0;
439
+
int err;
440
+
441
+
pr_crit("**************************************\n");
442
+
pr_crit("CPU:%d, Error:%s, Errmon:%d\n", smp_processor_id(),
443
+
cbb->fabric->name, status);
444
+
445
+
while (status) {
446
+
if (status & BIT(0)) {
447
+
unsigned int notifier = cbb->fabric->notifier_offset;
448
+
u32 hi, lo, mask = BIT(index);
449
+
phys_addr_t addr;
450
+
u64 offset;
451
+
452
+
writel(mask, cbb->regs + notifier + FABRIC_EN_CFG_ADDR_INDEX_0_0);
453
+
hi = readl(cbb->regs + notifier + FABRIC_EN_CFG_ADDR_HI_0);
454
+
lo = readl(cbb->regs + notifier + FABRIC_EN_CFG_ADDR_LOW_0);
455
+
456
+
addr = (u64)hi << 32 | lo;
457
+
458
+
offset = addr - cbb->res->start;
459
+
cbb->mon = cbb->regs + offset;
460
+
cbb->mask = BIT(index);
461
+
462
+
err = print_errmonX_info(file, cbb);
463
+
tegra234_cbb_error_clear(&cbb->base);
464
+
if (err)
465
+
return err;
466
+
}
467
+
468
+
status >>= 1;
469
+
index++;
470
+
}
471
+
472
+
tegra_cbb_print_err(file, "\t**************************************\n");
473
+
return 0;
474
+
}
475
+
476
+
#ifdef CONFIG_DEBUG_FS
477
+
static DEFINE_MUTEX(cbb_debugfs_mutex);
478
+
479
+
static int tegra234_cbb_debugfs_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
480
+
{
481
+
int err = 0;
482
+
483
+
mutex_lock(&cbb_debugfs_mutex);
484
+
485
+
list_for_each_entry(cbb, &cbb_list, node) {
486
+
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
487
+
u32 status;
488
+
489
+
status = tegra_cbb_get_status(&priv->base);
490
+
if (status) {
491
+
err = print_err_notifier(file, priv, status);
492
+
if (err)
493
+
break;
494
+
}
495
+
}
496
+
497
+
mutex_unlock(&cbb_debugfs_mutex);
498
+
return err;
499
+
}
500
+
#endif
501
+
502
+
/*
503
+
* Handler for CBB errors
504
+
*/
505
+
static irqreturn_t tegra234_cbb_isr(int irq, void *data)
506
+
{
507
+
bool is_inband_err = false;
508
+
struct tegra_cbb *cbb;
509
+
unsigned long flags;
510
+
u8 mstr_id;
511
+
int err;
512
+
513
+
spin_lock_irqsave(&cbb_lock, flags);
514
+
515
+
list_for_each_entry(cbb, &cbb_list, node) {
516
+
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
517
+
u32 status = tegra_cbb_get_status(cbb);
518
+
519
+
if (status && (irq == priv->sec_irq)) {
520
+
tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@%llx, irq=%d\n",
521
+
smp_processor_id(), priv->fabric->name,
522
+
priv->res->start, irq);
523
+
524
+
err = print_err_notifier(NULL, priv, status);
525
+
if (err)
526
+
goto unlock;
527
+
528
+
mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits);
529
+
530
+
/*
531
+
* If illegal request is from CCPLEX(id:0x1) master then call BUG() to
532
+
* crash system.
533
+
*/
534
+
if ((mstr_id == 0x1) && priv->fabric->off_mask_erd)
535
+
is_inband_err = 1;
536
+
}
537
+
}
538
+
539
+
unlock:
540
+
spin_unlock_irqrestore(&cbb_lock, flags);
541
+
WARN_ON(is_inband_err);
542
+
return IRQ_HANDLED;
543
+
}
544
+
545
+
/*
546
+
* Register handler for CBB_SECURE interrupt for reporting errors
547
+
*/
548
+
static int tegra234_cbb_interrupt_enable(struct tegra_cbb *cbb)
549
+
{
550
+
struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
551
+
552
+
if (priv->sec_irq) {
553
+
int err = devm_request_irq(cbb->dev, priv->sec_irq, tegra234_cbb_isr, 0,
554
+
dev_name(cbb->dev), priv);
555
+
if (err) {
556
+
dev_err(cbb->dev, "failed to register interrupt %u: %d\n", priv->sec_irq,
557
+
err);
558
+
return err;
559
+
}
560
+
}
561
+
562
+
return 0;
563
+
}
564
+
565
+
static void tegra234_cbb_error_enable(struct tegra_cbb *cbb)
566
+
{
567
+
tegra_cbb_fault_enable(cbb);
568
+
}
569
+
570
+
static const struct tegra_cbb_ops tegra234_cbb_ops = {
571
+
.get_status = tegra234_cbb_get_status,
572
+
.error_clear = tegra234_cbb_error_clear,
573
+
.fault_enable = tegra234_cbb_fault_enable,
574
+
.error_enable = tegra234_cbb_error_enable,
575
+
.interrupt_enable = tegra234_cbb_interrupt_enable,
576
+
#ifdef CONFIG_DEBUG_FS
577
+
.debugfs_show = tegra234_cbb_debugfs_show,
578
+
#endif
579
+
};
580
+
581
+
static const char * const tegra234_master_id[] = {
582
+
[0x00] = "TZ",
583
+
[0x01] = "CCPLEX",
584
+
[0x02] = "CCPMU",
585
+
[0x03] = "BPMP_FW",
586
+
[0x04] = "AON",
587
+
[0x05] = "SCE",
588
+
[0x06] = "GPCDMA_P",
589
+
[0x07] = "TSECA_NONSECURE",
590
+
[0x08] = "TSECA_LIGHTSECURE",
591
+
[0x09] = "TSECA_HEAVYSECURE",
592
+
[0x0a] = "CORESIGHT",
593
+
[0x0b] = "APE",
594
+
[0x0c] = "PEATRANS",
595
+
[0x0d] = "JTAGM_DFT",
596
+
[0x0e] = "RCE",
597
+
[0x0f] = "DCE",
598
+
[0x10] = "PSC_FW_USER",
599
+
[0x11] = "PSC_FW_SUPERVISOR",
600
+
[0x12] = "PSC_FW_MACHINE",
601
+
[0x13] = "PSC_BOOT",
602
+
[0x14] = "BPMP_BOOT",
603
+
[0x15] = "NVDEC_NONSECURE",
604
+
[0x16] = "NVDEC_LIGHTSECURE",
605
+
[0x17] = "NVDEC_HEAVYSECURE",
606
+
[0x18] = "CBB_INTERNAL",
607
+
[0x19] = "RSVD"
608
+
};
609
+
610
+
static const struct tegra_cbb_error tegra234_cbb_errors[] = {
611
+
{
612
+
.code = "SLAVE_ERR",
613
+
.desc = "Slave being accessed responded with an error"
614
+
}, {
615
+
.code = "DECODE_ERR",
616
+
.desc = "Attempt to access an address hole"
617
+
}, {
618
+
.code = "FIREWALL_ERR",
619
+
.desc = "Attempt to access a region which is firewall protected"
620
+
}, {
621
+
.code = "TIMEOUT_ERR",
622
+
.desc = "No response returned by slave"
623
+
}, {
624
+
.code = "PWRDOWN_ERR",
625
+
.desc = "Attempt to access a portion of fabric that is powered down"
626
+
}, {
627
+
.code = "UNSUPPORTED_ERR",
628
+
.desc = "Attempt to access a slave through an unsupported access"
629
+
}
630
+
};
631
+
632
+
static const struct tegra234_slave_lookup tegra234_aon_slave_map[] = {
633
+
{ "AXI2APB", 0x00000 },
634
+
{ "AST", 0x14000 },
635
+
{ "CBB", 0x15000 },
636
+
{ "CPU", 0x16000 },
637
+
};
638
+
639
+
static const struct tegra234_cbb_fabric tegra234_aon_fabric = {
640
+
.name = "aon-fabric",
641
+
.master_id = tegra234_master_id,
642
+
.slave_map = tegra234_aon_slave_map,
643
+
.errors = tegra234_cbb_errors,
644
+
.notifier_offset = 0x17000,
645
+
};
646
+
647
+
static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = {
648
+
{ "AXI2APB", 0x00000 },
649
+
{ "AST0", 0x15000 },
650
+
{ "AST1", 0x16000 },
651
+
{ "CBB", 0x17000 },
652
+
{ "CPU", 0x18000 },
653
+
};
654
+
655
+
static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = {
656
+
.name = "bpmp-fabric",
657
+
.master_id = tegra234_master_id,
658
+
.slave_map = tegra234_bpmp_slave_map,
659
+
.errors = tegra234_cbb_errors,
660
+
.notifier_offset = 0x19000,
661
+
};
662
+
663
+
static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = {
664
+
{ "AON", 0x40000 },
665
+
{ "BPMP", 0x41000 },
666
+
{ "CBB", 0x42000 },
667
+
{ "HOST1X", 0x43000 },
668
+
{ "STM", 0x44000 },
669
+
{ "FSI", 0x45000 },
670
+
{ "PSC", 0x46000 },
671
+
{ "PCIE_C1", 0x47000 },
672
+
{ "PCIE_C2", 0x48000 },
673
+
{ "PCIE_C3", 0x49000 },
674
+
{ "PCIE_C0", 0x4a000 },
675
+
{ "PCIE_C4", 0x4b000 },
676
+
{ "GPU", 0x4c000 },
677
+
{ "SMMU0", 0x4d000 },
678
+
{ "SMMU1", 0x4e000 },
679
+
{ "SMMU2", 0x4f000 },
680
+
{ "SMMU3", 0x50000 },
681
+
{ "SMMU4", 0x51000 },
682
+
{ "PCIE_C10", 0x52000 },
683
+
{ "PCIE_C7", 0x53000 },
684
+
{ "PCIE_C8", 0x54000 },
685
+
{ "PCIE_C9", 0x55000 },
686
+
{ "PCIE_C5", 0x56000 },
687
+
{ "PCIE_C6", 0x57000 },
688
+
{ "DCE", 0x58000 },
689
+
{ "RCE", 0x59000 },
690
+
{ "SCE", 0x5a000 },
691
+
{ "AXI2APB_1", 0x70000 },
692
+
{ "AXI2APB_10", 0x71000 },
693
+
{ "AXI2APB_11", 0x72000 },
694
+
{ "AXI2APB_12", 0x73000 },
695
+
{ "AXI2APB_13", 0x74000 },
696
+
{ "AXI2APB_14", 0x75000 },
697
+
{ "AXI2APB_15", 0x76000 },
698
+
{ "AXI2APB_16", 0x77000 },
699
+
{ "AXI2APB_17", 0x78000 },
700
+
{ "AXI2APB_18", 0x79000 },
701
+
{ "AXI2APB_19", 0x7a000 },
702
+
{ "AXI2APB_2", 0x7b000 },
703
+
{ "AXI2APB_20", 0x7c000 },
704
+
{ "AXI2APB_21", 0x7d000 },
705
+
{ "AXI2APB_22", 0x7e000 },
706
+
{ "AXI2APB_23", 0x7f000 },
707
+
{ "AXI2APB_25", 0x80000 },
708
+
{ "AXI2APB_26", 0x81000 },
709
+
{ "AXI2APB_27", 0x82000 },
710
+
{ "AXI2APB_28", 0x83000 },
711
+
{ "AXI2APB_29", 0x84000 },
712
+
{ "AXI2APB_30", 0x85000 },
713
+
{ "AXI2APB_31", 0x86000 },
714
+
{ "AXI2APB_32", 0x87000 },
715
+
{ "AXI2APB_33", 0x88000 },
716
+
{ "AXI2APB_34", 0x89000 },
717
+
{ "AXI2APB_35", 0x92000 },
718
+
{ "AXI2APB_4", 0x8b000 },
719
+
{ "AXI2APB_5", 0x8c000 },
720
+
{ "AXI2APB_6", 0x8d000 },
721
+
{ "AXI2APB_7", 0x8e000 },
722
+
{ "AXI2APB_8", 0x8f000 },
723
+
{ "AXI2APB_9", 0x90000 },
724
+
{ "AXI2APB_3", 0x91000 },
725
+
};
726
+
727
+
static const struct tegra234_cbb_fabric tegra234_cbb_fabric = {
728
+
.name = "cbb-fabric",
729
+
.master_id = tegra234_master_id,
730
+
.slave_map = tegra234_cbb_slave_map,
731
+
.errors = tegra234_cbb_errors,
732
+
.notifier_offset = 0x60000,
733
+
.off_mask_erd = 0x3a004
734
+
};
735
+
736
+
static const struct tegra234_slave_lookup tegra234_dce_slave_map[] = {
737
+
{ "AXI2APB", 0x00000 },
738
+
{ "AST0", 0x15000 },
739
+
{ "AST1", 0x16000 },
740
+
{ "CPU", 0x18000 },
741
+
};
742
+
743
+
static const struct tegra234_cbb_fabric tegra234_dce_fabric = {
744
+
.name = "dce-fabric",
745
+
.master_id = tegra234_master_id,
746
+
.slave_map = tegra234_dce_slave_map,
747
+
.errors = tegra234_cbb_errors,
748
+
.notifier_offset = 0x19000,
749
+
};
750
+
751
+
static const struct tegra234_slave_lookup tegra234_rce_slave_map[] = {
752
+
{ "AXI2APB", 0x00000 },
753
+
{ "AST0", 0x15000 },
754
+
{ "AST1", 0x16000 },
755
+
{ "CPU", 0x18000 },
756
+
};
757
+
758
+
static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
759
+
.name = "rce-fabric",
760
+
.master_id = tegra234_master_id,
761
+
.slave_map = tegra234_rce_slave_map,
762
+
.errors = tegra234_cbb_errors,
763
+
.notifier_offset = 0x19000,
764
+
};
765
+
766
+
static const struct tegra234_slave_lookup tegra234_sce_slave_map[] = {
767
+
{ "AXI2APB", 0x00000 },
768
+
{ "AST0", 0x15000 },
769
+
{ "AST1", 0x16000 },
770
+
{ "CBB", 0x17000 },
771
+
{ "CPU", 0x18000 },
772
+
};
773
+
774
+
static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
775
+
.name = "sce-fabric",
776
+
.master_id = tegra234_master_id,
777
+
.slave_map = tegra234_sce_slave_map,
778
+
.errors = tegra234_cbb_errors,
779
+
.notifier_offset = 0x19000,
780
+
};
781
+
782
+
static const char * const tegra241_master_id[] = {
783
+
[0x0] = "TZ",
784
+
[0x1] = "CCPLEX",
785
+
[0x2] = "CCPMU",
786
+
[0x3] = "BPMP_FW",
787
+
[0x4] = "PSC_FW_USER",
788
+
[0x5] = "PSC_FW_SUPERVISOR",
789
+
[0x6] = "PSC_FW_MACHINE",
790
+
[0x7] = "PSC_BOOT",
791
+
[0x8] = "BPMP_BOOT",
792
+
[0x9] = "JTAGM_DFT",
793
+
[0xa] = "CORESIGHT",
794
+
[0xb] = "GPU",
795
+
[0xc] = "PEATRANS",
796
+
[0xd ... 0x3f] = "RSVD"
797
+
};
798
+
799
+
/*
800
+
* Possible causes for Slave and Timeout errors.
801
+
* SLAVE_ERR:
802
+
* Slave being accessed responded with an error. Slave could return
803
+
* an error for various cases :
804
+
* Unsupported access, clamp setting when power gated, register
805
+
* level firewall(SCR), address hole within the slave, etc
806
+
*
807
+
* TIMEOUT_ERR:
808
+
* No response returned by slave. Can be due to slave being clock
809
+
* gated, under reset, powered down or slave inability to respond
810
+
* for an internal slave issue
811
+
*/
812
+
static const struct tegra_cbb_error tegra241_cbb_errors[] = {
813
+
{
814
+
.code = "SLAVE_ERR",
815
+
.desc = "Slave being accessed responded with an error."
816
+
}, {
817
+
.code = "DECODE_ERR",
818
+
.desc = "Attempt to access an address hole or Reserved region of memory."
819
+
}, {
820
+
.code = "FIREWALL_ERR",
821
+
.desc = "Attempt to access a region which is firewalled."
822
+
}, {
823
+
.code = "TIMEOUT_ERR",
824
+
.desc = "No response returned by slave."
825
+
}, {
826
+
.code = "PWRDOWN_ERR",
827
+
.desc = "Attempt to access a portion of the fabric that is powered down."
828
+
}, {
829
+
.code = "UNSUPPORTED_ERR",
830
+
.desc = "Attempt to access a slave through an unsupported access."
831
+
}, {
832
+
.code = "POISON_ERR",
833
+
.desc = "Slave responds with poison error to indicate error in data."
834
+
}, {
835
+
.code = "RSVD"
836
+
}, {
837
+
.code = "RSVD"
838
+
}, {
839
+
.code = "RSVD"
840
+
}, {
841
+
.code = "RSVD"
842
+
}, {
843
+
.code = "RSVD"
844
+
}, {
845
+
.code = "RSVD"
846
+
}, {
847
+
.code = "RSVD"
848
+
}, {
849
+
.code = "RSVD"
850
+
}, {
851
+
.code = "RSVD"
852
+
}, {
853
+
.code = "NO_SUCH_ADDRESS_ERR",
854
+
.desc = "The address belongs to the pri_target range but there is no register "
855
+
"implemented at the address."
856
+
}, {
857
+
.code = "TASK_ERR",
858
+
.desc = "Attempt to update a PRI task when the current task has still not "
859
+
"completed."
860
+
}, {
861
+
.code = "EXTERNAL_ERR",
862
+
.desc = "Indicates that an external PRI register access met with an error due to "
863
+
"any issue in the unit."
864
+
}, {
865
+
.code = "INDEX_ERR",
866
+
.desc = "Applicable to PRI index aperture pair, when the programmed index is "
867
+
"outside the range defined in the manual."
868
+
}, {
869
+
.code = "RESET_ERR",
870
+
.desc = "Target in Reset Error: Attempt to access a SubPri or external PRI "
871
+
"register but they are in reset."
872
+
}, {
873
+
.code = "REGISTER_RST_ERR",
874
+
.desc = "Attempt to access a PRI register but the register is partial or "
875
+
"completely in reset."
876
+
}, {
877
+
.code = "POWER_GATED_ERR",
878
+
.desc = "Returned by external PRI client when the external access goes to a power "
879
+
"gated domain."
880
+
}, {
881
+
.code = "SUBPRI_FS_ERR",
882
+
.desc = "Subpri is floorswept: Attempt to access a subpri through the main pri "
883
+
"target but subPri logic is floorswept."
884
+
}, {
885
+
.code = "SUBPRI_CLK_OFF_ERR",
886
+
.desc = "Subpri clock is off: Attempt to access a subpri through the main pri "
887
+
"target but subPris clock is gated/off."
888
+
},
889
+
};
890
+
891
+
static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = {
892
+
{ "CCPLEX", 0x50000 },
893
+
{ "PCIE_C8", 0x51000 },
894
+
{ "PCIE_C9", 0x52000 },
895
+
{ "RSVD", 0x00000 },
896
+
{ "RSVD", 0x00000 },
897
+
{ "RSVD", 0x00000 },
898
+
{ "RSVD", 0x00000 },
899
+
{ "RSVD", 0x00000 },
900
+
{ "RSVD", 0x00000 },
901
+
{ "RSVD", 0x00000 },
902
+
{ "RSVD", 0x00000 },
903
+
{ "AON", 0x5b000 },
904
+
{ "BPMP", 0x5c000 },
905
+
{ "RSVD", 0x00000 },
906
+
{ "RSVD", 0x00000 },
907
+
{ "PSC", 0x5d000 },
908
+
{ "STM", 0x5e000 },
909
+
{ "AXI2APB_1", 0x70000 },
910
+
{ "AXI2APB_10", 0x71000 },
911
+
{ "AXI2APB_11", 0x72000 },
912
+
{ "AXI2APB_12", 0x73000 },
913
+
{ "AXI2APB_13", 0x74000 },
914
+
{ "AXI2APB_14", 0x75000 },
915
+
{ "AXI2APB_15", 0x76000 },
916
+
{ "AXI2APB_16", 0x77000 },
917
+
{ "AXI2APB_17", 0x78000 },
918
+
{ "AXI2APB_18", 0x79000 },
919
+
{ "AXI2APB_19", 0x7a000 },
920
+
{ "AXI2APB_2", 0x7b000 },
921
+
{ "AXI2APB_20", 0x7c000 },
922
+
{ "AXI2APB_4", 0x87000 },
923
+
{ "AXI2APB_5", 0x88000 },
924
+
{ "AXI2APB_6", 0x89000 },
925
+
{ "AXI2APB_7", 0x8a000 },
926
+
{ "AXI2APB_8", 0x8b000 },
927
+
{ "AXI2APB_9", 0x8c000 },
928
+
{ "AXI2APB_3", 0x8d000 },
929
+
{ "AXI2APB_21", 0x7d000 },
930
+
{ "AXI2APB_22", 0x7e000 },
931
+
{ "AXI2APB_23", 0x7f000 },
932
+
{ "AXI2APB_24", 0x80000 },
933
+
{ "AXI2APB_25", 0x81000 },
934
+
{ "AXI2APB_26", 0x82000 },
935
+
{ "AXI2APB_27", 0x83000 },
936
+
{ "AXI2APB_28", 0x84000 },
937
+
{ "PCIE_C4", 0x53000 },
938
+
{ "PCIE_C5", 0x54000 },
939
+
{ "PCIE_C6", 0x55000 },
940
+
{ "PCIE_C7", 0x56000 },
941
+
{ "PCIE_C2", 0x57000 },
942
+
{ "PCIE_C3", 0x58000 },
943
+
{ "PCIE_C0", 0x59000 },
944
+
{ "PCIE_C1", 0x5a000 },
945
+
{ "AXI2APB_29", 0x85000 },
946
+
{ "AXI2APB_30", 0x86000 },
947
+
};
948
+
949
+
static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
950
+
.name = "cbb-fabric",
951
+
.master_id = tegra241_master_id,
952
+
.slave_map = tegra241_cbb_slave_map,
953
+
.errors = tegra241_cbb_errors,
954
+
.notifier_offset = 0x60000,
955
+
.off_mask_erd = 0x40004,
956
+
};
957
+
958
+
static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = {
959
+
{ "RSVD", 0x00000 },
960
+
{ "RSVD", 0x00000 },
961
+
{ "CBB", 0x15000 },
962
+
{ "CPU", 0x16000 },
963
+
{ "AXI2APB", 0x00000 },
964
+
{ "DBB0", 0x17000 },
965
+
{ "DBB1", 0x18000 },
966
+
};
967
+
968
+
static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
969
+
.name = "bpmp-fabric",
970
+
.master_id = tegra241_master_id,
971
+
.slave_map = tegra241_bpmp_slave_map,
972
+
.errors = tegra241_cbb_errors,
973
+
.notifier_offset = 0x19000,
974
+
};
975
+
976
+
static const struct of_device_id tegra234_cbb_dt_ids[] = {
977
+
{ .compatible = "nvidia,tegra234-cbb-fabric", .data = &tegra234_cbb_fabric },
978
+
{ .compatible = "nvidia,tegra234-aon-fabric", .data = &tegra234_aon_fabric },
979
+
{ .compatible = "nvidia,tegra234-bpmp-fabric", .data = &tegra234_bpmp_fabric },
980
+
{ .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },
981
+
{ .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },
982
+
{ .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },
983
+
{ /* sentinel */ },
984
+
};
985
+
MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);
986
+
987
+
struct tegra234_cbb_acpi_uid {
988
+
const char *hid;
989
+
const char *uid;
990
+
const struct tegra234_cbb_fabric *fabric;
991
+
};
992
+
993
+
static const struct tegra234_cbb_acpi_uid tegra234_cbb_acpi_uids[] = {
994
+
{ "NVDA1070", "1", &tegra241_cbb_fabric },
995
+
{ "NVDA1070", "2", &tegra241_bpmp_fabric },
996
+
{ },
997
+
};
998
+
999
+
static const struct
1000
+
tegra234_cbb_fabric *tegra234_cbb_acpi_get_fabric(struct acpi_device *adev)
1001
+
{
1002
+
const struct tegra234_cbb_acpi_uid *entry;
1003
+
1004
+
for (entry = tegra234_cbb_acpi_uids; entry->hid; entry++) {
1005
+
if (acpi_dev_hid_uid_match(adev, entry->hid, entry->uid))
1006
+
return entry->fabric;
1007
+
}
1008
+
1009
+
return NULL;
1010
+
}
1011
+
1012
+
static const struct acpi_device_id tegra241_cbb_acpi_ids[] = {
1013
+
{ "NVDA1070" },
1014
+
{ },
1015
+
};
1016
+
MODULE_DEVICE_TABLE(acpi, tegra241_cbb_acpi_ids);
1017
+
1018
+
static int tegra234_cbb_probe(struct platform_device *pdev)
1019
+
{
1020
+
const struct tegra234_cbb_fabric *fabric;
1021
+
struct tegra234_cbb *cbb;
1022
+
unsigned long flags = 0;
1023
+
int err;
1024
+
1025
+
if (pdev->dev.of_node) {
1026
+
fabric = of_device_get_match_data(&pdev->dev);
1027
+
} else {
1028
+
struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
1029
+
if (!device)
1030
+
return -ENODEV;
1031
+
1032
+
fabric = tegra234_cbb_acpi_get_fabric(device);
1033
+
if (!fabric) {
1034
+
dev_err(&pdev->dev, "no device match found\n");
1035
+
return -ENODEV;
1036
+
}
1037
+
}
1038
+
1039
+
cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
1040
+
if (!cbb)
1041
+
return -ENOMEM;
1042
+
1043
+
INIT_LIST_HEAD(&cbb->base.node);
1044
+
cbb->base.ops = &tegra234_cbb_ops;
1045
+
cbb->base.dev = &pdev->dev;
1046
+
cbb->fabric = fabric;
1047
+
1048
+
cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);
1049
+
if (IS_ERR(cbb->regs))
1050
+
return PTR_ERR(cbb->regs);
1051
+
1052
+
err = tegra_cbb_get_irq(pdev, NULL, &cbb->sec_irq);
1053
+
if (err)
1054
+
return err;
1055
+
1056
+
platform_set_drvdata(pdev, cbb);
1057
+
1058
+
spin_lock_irqsave(&cbb_lock, flags);
1059
+
list_add(&cbb->base.node, &cbb_list);
1060
+
spin_unlock_irqrestore(&cbb_lock, flags);
1061
+
1062
+
/* set ERD bit to mask SError and generate interrupt to report error */
1063
+
if (cbb->fabric->off_mask_erd)
1064
+
tegra234_cbb_mask_serror(cbb);
1065
+
1066
+
return tegra_cbb_register(&cbb->base);
1067
+
}
1068
+
1069
+
static int tegra234_cbb_remove(struct platform_device *pdev)
1070
+
{
1071
+
return 0;
1072
+
}
1073
+
1074
+
static int __maybe_unused tegra234_cbb_resume_noirq(struct device *dev)
1075
+
{
1076
+
struct tegra234_cbb *cbb = dev_get_drvdata(dev);
1077
+
1078
+
tegra234_cbb_error_enable(&cbb->base);
1079
+
1080
+
dev_dbg(dev, "%s resumed\n", cbb->fabric->name);
1081
+
1082
+
return 0;
1083
+
}
1084
+
1085
+
static const struct dev_pm_ops tegra234_cbb_pm = {
1086
+
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra234_cbb_resume_noirq)
1087
+
};
1088
+
1089
+
static struct platform_driver tegra234_cbb_driver = {
1090
+
.probe = tegra234_cbb_probe,
1091
+
.remove = tegra234_cbb_remove,
1092
+
.driver = {
1093
+
.name = "tegra234-cbb",
1094
+
.of_match_table = tegra234_cbb_dt_ids,
1095
+
.acpi_match_table = tegra241_cbb_acpi_ids,
1096
+
.pm = &tegra234_cbb_pm,
1097
+
},
1098
+
};
1099
+
1100
+
static int __init tegra234_cbb_init(void)
1101
+
{
1102
+
return platform_driver_register(&tegra234_cbb_driver);
1103
+
}
1104
+
pure_initcall(tegra234_cbb_init);
1105
+
1106
+
static void __exit tegra234_cbb_exit(void)
1107
+
{
1108
+
platform_driver_unregister(&tegra234_cbb_driver);
1109
+
}
1110
+
module_exit(tegra234_cbb_exit);
1111
+
1112
+
MODULE_DESCRIPTION("Control Backbone 2.0 error handling driver for Tegra234");
1113
+
MODULE_LICENSE("GPL");
+27
-2
drivers/soc/tegra/fuse/tegra-apbmisc.c
+27
-2
drivers/soc/tegra/fuse/tegra-apbmisc.c
···
16
16
17
17
#define FUSE_SKU_INFO 0x10
18
18
19
+
#define ERD_ERR_CONFIG 0x120c
20
+
#define ERD_MASK_INBAND_ERR 0x1
21
+
19
22
#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
20
23
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
21
24
(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
22
25
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
23
26
(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
24
27
28
+
static void __iomem *apbmisc_base;
25
29
static bool long_ram_code;
26
30
static u32 strapping;
27
31
static u32 chipid;
···
97
93
}
98
94
EXPORT_SYMBOL_GPL(tegra_read_ram_code);
99
95
96
+
/*
97
+
* The function sets ERD(Error Response Disable) bit.
98
+
* This allows to mask inband errors and always send an
99
+
* OKAY response from CBB to the master which caused error.
100
+
*/
101
+
int tegra194_miscreg_mask_serror(void)
102
+
{
103
+
if (!apbmisc_base)
104
+
return -EPROBE_DEFER;
105
+
106
+
if (!of_machine_is_compatible("nvidia,tegra194")) {
107
+
WARN(1, "Only supported for Tegra194 devices!\n");
108
+
return -EOPNOTSUPP;
109
+
}
110
+
111
+
writel_relaxed(ERD_MASK_INBAND_ERR,
112
+
apbmisc_base + ERD_ERR_CONFIG);
113
+
114
+
return 0;
115
+
}
116
+
EXPORT_SYMBOL(tegra194_miscreg_mask_serror);
117
+
100
118
static const struct of_device_id apbmisc_match[] __initconst = {
101
119
{ .compatible = "nvidia,tegra20-apbmisc", },
102
120
{ .compatible = "nvidia,tegra186-misc", },
···
160
134
161
135
void __init tegra_init_apbmisc(void)
162
136
{
163
-
void __iomem *apbmisc_base, *strapping_base;
137
+
void __iomem *strapping_base;
164
138
struct resource apbmisc, straps;
165
139
struct device_node *np;
166
140
···
222
196
pr_err("failed to map APBMISC registers\n");
223
197
} else {
224
198
chipid = readl_relaxed(apbmisc_base + 4);
225
-
iounmap(apbmisc_base);
226
199
}
227
200
228
201
strapping_base = ioremap(straps.start, resource_size(&straps));
+6
include/soc/tegra/fuse.h
+6
include/soc/tegra/fuse.h
···
58
58
u8 tegra_get_chip_id(void);
59
59
u8 tegra_get_platform(void);
60
60
bool tegra_is_silicon(void);
61
+
int tegra194_miscreg_mask_serror(void);
61
62
#else
62
63
static struct tegra_sku_info tegra_sku_info __maybe_unused;
63
64
···
93
92
}
94
93
95
94
static inline bool tegra_is_silicon(void)
95
+
{
96
+
return false;
97
+
}
98
+
99
+
static inline int tegra194_miscreg_mask_serror(void)
96
100
{
97
101
return false;
98
102
}
+47
include/soc/tegra/tegra-cbb.h
+47
include/soc/tegra/tegra-cbb.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
4
+
*/
5
+
6
+
#ifndef TEGRA_CBB_H
7
+
#define TEGRA_CBB_H
8
+
9
+
#include <linux/list.h>
10
+
11
+
struct tegra_cbb_error {
12
+
const char *code;
13
+
const char *source;
14
+
const char *desc;
15
+
};
16
+
17
+
struct tegra_cbb {
18
+
struct device *dev;
19
+
const struct tegra_cbb_ops *ops;
20
+
struct list_head node;
21
+
};
22
+
23
+
struct tegra_cbb_ops {
24
+
int (*debugfs_show)(struct tegra_cbb *cbb, struct seq_file *s, void *v);
25
+
int (*interrupt_enable)(struct tegra_cbb *cbb);
26
+
void (*error_enable)(struct tegra_cbb *cbb);
27
+
void (*fault_enable)(struct tegra_cbb *cbb);
28
+
void (*stall_enable)(struct tegra_cbb *cbb);
29
+
void (*error_clear)(struct tegra_cbb *cbb);
30
+
u32 (*get_status)(struct tegra_cbb *cbb);
31
+
};
32
+
33
+
int tegra_cbb_get_irq(struct platform_device *pdev, unsigned int *nonsec_irq,
34
+
unsigned int *sec_irq);
35
+
__printf(2, 3)
36
+
void tegra_cbb_print_err(struct seq_file *file, const char *fmt, ...);
37
+
38
+
void tegra_cbb_print_cache(struct seq_file *file, u32 cache);
39
+
void tegra_cbb_print_prot(struct seq_file *file, u32 prot);
40
+
int tegra_cbb_register(struct tegra_cbb *cbb);
41
+
42
+
void tegra_cbb_fault_enable(struct tegra_cbb *cbb);
43
+
void tegra_cbb_stall_enable(struct tegra_cbb *cbb);
44
+
void tegra_cbb_error_clear(struct tegra_cbb *cbb);
45
+
u32 tegra_cbb_get_status(struct tegra_cbb *cbb);
46
+
47
+
#endif /* TEGRA_CBB_H */