tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v5.7-next-dts64.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
mt8183:
- add PMIC mt6358
- add MMC node
mt2712:
- enable APDMA for the uart node
- add ethernet gmac node
mmsys:
- change node name to syscon as mmsys no longer represents only clocks
but also the DRM subsystem
* tag 'v5.7-next-dts64.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm: dts: mt2712: add uart APDMA to device tree
arm64: dts: mt8183: add mmc node
arm64: dts: mt2712: add ethernet device node
arm64: dts: mt6358: add PMIC MT6358 related nodes
arm64: dts: mt6797: Fix mmsys node name
arm64: dts: mt8173: Fix mmsys node name
Link: https://lore.kernel.org/r/7c9f85c7-5b13-38e3-7a1f-a3cd6461b095@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+721
-2
+74
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+74
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
···
105
105
proc-supply = <&cpus_fixed_vproc1>;
106
106
};
107
107
108
+
ð {
109
+
phy-mode ="rgmii-rxid";
110
+
phy-handle = <ðernet_phy0>;
111
+
mediatek,tx-delay-ps = <1530>;
112
+
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
113
+
pinctrl-names = "default", "sleep";
114
+
pinctrl-0 = <ð_default>;
115
+
pinctrl-1 = <ð_sleep>;
116
+
status = "okay";
117
+
118
+
mdio {
119
+
compatible = "snps,dwmac-mdio";
120
+
#address-cells = <1>;
121
+
#size-cells = <0>;
122
+
ethernet_phy0: ethernet-phy@5 {
123
+
compatible = "ethernet-phy-id0243.0d90";
124
+
reg = <0x5>;
125
+
};
126
+
};
127
+
};
128
+
108
129
&pio {
130
+
eth_default: eth_default {
131
+
tx_pins {
132
+
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
133
+
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
134
+
<MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>,
135
+
<MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
136
+
<MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
137
+
<MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
138
+
drive-strength = <MTK_DRIVE_8mA>;
139
+
};
140
+
rx_pins {
141
+
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
142
+
<MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>,
143
+
<MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>,
144
+
<MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>,
145
+
<MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>,
146
+
<MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>;
147
+
input-enable;
148
+
};
149
+
mdio_pins {
150
+
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
151
+
<MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
152
+
drive-strength = <MTK_DRIVE_8mA>;
153
+
input-enable;
154
+
};
155
+
};
156
+
157
+
eth_sleep: eth_sleep {
158
+
tx_pins {
159
+
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
160
+
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
161
+
<MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>,
162
+
<MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>,
163
+
<MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>,
164
+
<MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>;
165
+
};
166
+
rx_pins {
167
+
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>,
168
+
<MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>,
169
+
<MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>,
170
+
<MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>,
171
+
<MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>,
172
+
<MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>;
173
+
input-disable;
174
+
};
175
+
mdio_pins {
176
+
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>,
177
+
<MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>;
178
+
input-disable;
179
+
bias-disable;
180
+
};
181
+
};
182
+
109
183
usb0_id_pins_float: usb0_iddig {
110
184
pins_iddig {
111
185
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
+116
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+116
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
···
300
300
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
301
301
clocks = <&baud_clk>, <&sys_clk>;
302
302
clock-names = "baud", "bus";
303
+
dmas = <&apdma 10
304
+
&apdma 11>;
305
+
dma-names = "tx", "rx";
303
306
status = "disabled";
304
307
};
305
308
···
378
375
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
379
376
};
380
377
378
+
apdma: dma-controller@11000400 {
379
+
compatible = "mediatek,mt2712-uart-dma",
380
+
"mediatek,mt6577-uart-dma";
381
+
reg = <0 0x11000400 0 0x80>,
382
+
<0 0x11000480 0 0x80>,
383
+
<0 0x11000500 0 0x80>,
384
+
<0 0x11000580 0 0x80>,
385
+
<0 0x11000600 0 0x80>,
386
+
<0 0x11000680 0 0x80>,
387
+
<0 0x11000700 0 0x80>,
388
+
<0 0x11000780 0 0x80>,
389
+
<0 0x11000800 0 0x80>,
390
+
<0 0x11000880 0 0x80>,
391
+
<0 0x11000900 0 0x80>,
392
+
<0 0x11000980 0 0x80>;
393
+
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
394
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
395
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
396
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
397
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
398
+
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
399
+
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
400
+
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
401
+
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
402
+
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
403
+
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
404
+
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
405
+
dma-requests = <12>;
406
+
clocks = <&pericfg CLK_PERI_AP_DMA>;
407
+
clock-names = "apdma";
408
+
#dma-cells = <1>;
409
+
};
410
+
381
411
auxadc: adc@11001000 {
382
412
compatible = "mediatek,mt2712-auxadc";
383
413
reg = <0 0x11001000 0 0x1000>;
···
427
391
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
428
392
clocks = <&baud_clk>, <&sys_clk>;
429
393
clock-names = "baud", "bus";
394
+
dmas = <&apdma 0
395
+
&apdma 1>;
396
+
dma-names = "tx", "rx";
430
397
status = "disabled";
431
398
};
432
399
···
440
401
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
441
402
clocks = <&baud_clk>, <&sys_clk>;
442
403
clock-names = "baud", "bus";
404
+
dmas = <&apdma 2
405
+
&apdma 3>;
406
+
dma-names = "tx", "rx";
443
407
status = "disabled";
444
408
};
445
409
···
453
411
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
454
412
clocks = <&baud_clk>, <&sys_clk>;
455
413
clock-names = "baud", "bus";
414
+
dmas = <&apdma 4
415
+
&apdma 5>;
416
+
dma-names = "tx", "rx";
456
417
status = "disabled";
457
418
};
458
419
···
466
421
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
467
422
clocks = <&baud_clk>, <&sys_clk>;
468
423
clock-names = "baud", "bus";
424
+
dmas = <&apdma 6
425
+
&apdma 7>;
426
+
dma-names = "tx", "rx";
469
427
status = "disabled";
470
428
};
471
429
···
683
635
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
684
636
clocks = <&baud_clk>, <&sys_clk>;
685
637
clock-names = "baud", "bus";
638
+
dmas = <&apdma 8
639
+
&apdma 9>;
640
+
dma-names = "tx", "rx";
641
+
status = "disabled";
642
+
};
643
+
644
+
stmmac_axi_setup: stmmac-axi-config {
645
+
snps,wr_osr_lmt = <0x7>;
646
+
snps,rd_osr_lmt = <0x7>;
647
+
snps,blen = <0 0 0 0 16 8 4>;
648
+
};
649
+
650
+
mtl_rx_setup: rx-queues-config {
651
+
snps,rx-queues-to-use = <1>;
652
+
snps,rx-sched-sp;
653
+
queue0 {
654
+
snps,dcb-algorithm;
655
+
snps,map-to-dma-channel = <0x0>;
656
+
snps,priority = <0x0>;
657
+
};
658
+
};
659
+
660
+
mtl_tx_setup: tx-queues-config {
661
+
snps,tx-queues-to-use = <3>;
662
+
snps,tx-sched-wrr;
663
+
queue0 {
664
+
snps,weight = <0x10>;
665
+
snps,dcb-algorithm;
666
+
snps,priority = <0x0>;
667
+
};
668
+
queue1 {
669
+
snps,weight = <0x11>;
670
+
snps,dcb-algorithm;
671
+
snps,priority = <0x1>;
672
+
};
673
+
queue2 {
674
+
snps,weight = <0x12>;
675
+
snps,dcb-algorithm;
676
+
snps,priority = <0x2>;
677
+
};
678
+
};
679
+
680
+
eth: ethernet@1101c000 {
681
+
compatible = "mediatek,mt2712-gmac";
682
+
reg = <0 0x1101c000 0 0x1300>;
683
+
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
684
+
interrupt-names = "macirq";
685
+
mac-address = [00 55 7b b5 7d f7];
686
+
clock-names = "axi",
687
+
"apb",
688
+
"mac_main",
689
+
"ptp_ref";
690
+
clocks = <&pericfg CLK_PERI_GMAC>,
691
+
<&pericfg CLK_PERI_GMAC_PCLK>,
692
+
<&topckgen CLK_TOP_ETHER_125M_SEL>,
693
+
<&topckgen CLK_TOP_ETHER_50M_SEL>;
694
+
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
695
+
<&topckgen CLK_TOP_ETHER_50M_SEL>;
696
+
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
697
+
<&topckgen CLK_TOP_APLL1_D3>;
698
+
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
699
+
mediatek,pericfg = <&pericfg>;
700
+
snps,axi-config = <&stmmac_axi_setup>;
701
+
snps,mtl-rx-config = <&mtl_rx_setup>;
702
+
snps,mtl-tx-config = <&mtl_tx_setup>;
703
+
snps,txpbl = <1>;
704
+
snps,rxpbl = <1>;
705
+
clk_csr = <0>;
686
706
status = "disabled";
687
707
};
688
708
+358
arch/arm64/boot/dts/mediatek/mt6358.dtsi
+358
arch/arm64/boot/dts/mediatek/mt6358.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/*
3
+
* Copyright (c) 2020 MediaTek Inc.
4
+
*/
5
+
6
+
&pwrap {
7
+
pmic: mt6358 {
8
+
compatible = "mediatek,mt6358";
9
+
interrupt-controller;
10
+
interrupt-parent = <&pio>;
11
+
interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
12
+
#interrupt-cells = <2>;
13
+
14
+
mt6358codec: mt6358codec {
15
+
compatible = "mediatek,mt6358-sound";
16
+
};
17
+
18
+
mt6358regulator: mt6358regulator {
19
+
mt6358_vdram1_reg: buck_vdram1 {
20
+
regulator-name = "vdram1";
21
+
regulator-min-microvolt = <500000>;
22
+
regulator-max-microvolt = <2087500>;
23
+
regulator-ramp-delay = <12500>;
24
+
regulator-enable-ramp-delay = <0>;
25
+
regulator-always-on;
26
+
regulator-allowed-modes = <0 1>;
27
+
};
28
+
29
+
mt6358_vcore_reg: buck_vcore {
30
+
regulator-name = "vcore";
31
+
regulator-min-microvolt = <500000>;
32
+
regulator-max-microvolt = <1293750>;
33
+
regulator-ramp-delay = <6250>;
34
+
regulator-enable-ramp-delay = <200>;
35
+
regulator-always-on;
36
+
regulator-allowed-modes = <0 1>;
37
+
};
38
+
39
+
mt6358_vpa_reg: buck_vpa {
40
+
regulator-name = "vpa";
41
+
regulator-min-microvolt = <500000>;
42
+
regulator-max-microvolt = <3650000>;
43
+
regulator-ramp-delay = <50000>;
44
+
regulator-enable-ramp-delay = <250>;
45
+
regulator-allowed-modes = <0 1>;
46
+
};
47
+
48
+
mt6358_vproc11_reg: buck_vproc11 {
49
+
regulator-name = "vproc11";
50
+
regulator-min-microvolt = <500000>;
51
+
regulator-max-microvolt = <1293750>;
52
+
regulator-ramp-delay = <6250>;
53
+
regulator-enable-ramp-delay = <200>;
54
+
regulator-always-on;
55
+
regulator-allowed-modes = <0 1>;
56
+
};
57
+
58
+
mt6358_vproc12_reg: buck_vproc12 {
59
+
regulator-name = "vproc12";
60
+
regulator-min-microvolt = <500000>;
61
+
regulator-max-microvolt = <1293750>;
62
+
regulator-ramp-delay = <6250>;
63
+
regulator-enable-ramp-delay = <200>;
64
+
regulator-always-on;
65
+
regulator-allowed-modes = <0 1>;
66
+
};
67
+
68
+
mt6358_vgpu_reg: buck_vgpu {
69
+
regulator-name = "vgpu";
70
+
regulator-min-microvolt = <500000>;
71
+
regulator-max-microvolt = <1293750>;
72
+
regulator-ramp-delay = <6250>;
73
+
regulator-enable-ramp-delay = <200>;
74
+
regulator-allowed-modes = <0 1>;
75
+
};
76
+
77
+
mt6358_vs2_reg: buck_vs2 {
78
+
regulator-name = "vs2";
79
+
regulator-min-microvolt = <500000>;
80
+
regulator-max-microvolt = <2087500>;
81
+
regulator-ramp-delay = <12500>;
82
+
regulator-enable-ramp-delay = <0>;
83
+
regulator-always-on;
84
+
};
85
+
86
+
mt6358_vmodem_reg: buck_vmodem {
87
+
regulator-name = "vmodem";
88
+
regulator-min-microvolt = <500000>;
89
+
regulator-max-microvolt = <1293750>;
90
+
regulator-ramp-delay = <6250>;
91
+
regulator-enable-ramp-delay = <900>;
92
+
regulator-always-on;
93
+
regulator-allowed-modes = <0 1>;
94
+
};
95
+
96
+
mt6358_vs1_reg: buck_vs1 {
97
+
regulator-name = "vs1";
98
+
regulator-min-microvolt = <1000000>;
99
+
regulator-max-microvolt = <2587500>;
100
+
regulator-ramp-delay = <12500>;
101
+
regulator-enable-ramp-delay = <0>;
102
+
regulator-always-on;
103
+
};
104
+
105
+
mt6358_vdram2_reg: ldo_vdram2 {
106
+
regulator-name = "vdram2";
107
+
regulator-min-microvolt = <600000>;
108
+
regulator-max-microvolt = <1800000>;
109
+
regulator-enable-ramp-delay = <3300>;
110
+
};
111
+
112
+
mt6358_vsim1_reg: ldo_vsim1 {
113
+
regulator-name = "vsim1";
114
+
regulator-min-microvolt = <1700000>;
115
+
regulator-max-microvolt = <3100000>;
116
+
regulator-enable-ramp-delay = <540>;
117
+
};
118
+
119
+
mt6358_vibr_reg: ldo_vibr {
120
+
regulator-name = "vibr";
121
+
regulator-min-microvolt = <1200000>;
122
+
regulator-max-microvolt = <3300000>;
123
+
regulator-enable-ramp-delay = <60>;
124
+
};
125
+
126
+
mt6358_vrf12_reg: ldo_vrf12 {
127
+
compatible = "regulator-fixed";
128
+
regulator-name = "vrf12";
129
+
regulator-min-microvolt = <1200000>;
130
+
regulator-max-microvolt = <1200000>;
131
+
regulator-enable-ramp-delay = <120>;
132
+
};
133
+
134
+
mt6358_vio18_reg: ldo_vio18 {
135
+
compatible = "regulator-fixed";
136
+
regulator-name = "vio18";
137
+
regulator-min-microvolt = <1800000>;
138
+
regulator-max-microvolt = <1800000>;
139
+
regulator-enable-ramp-delay = <2700>;
140
+
regulator-always-on;
141
+
};
142
+
143
+
mt6358_vusb_reg: ldo_vusb {
144
+
regulator-name = "vusb";
145
+
regulator-min-microvolt = <3000000>;
146
+
regulator-max-microvolt = <3100000>;
147
+
regulator-enable-ramp-delay = <270>;
148
+
regulator-always-on;
149
+
};
150
+
151
+
mt6358_vcamio_reg: ldo_vcamio {
152
+
compatible = "regulator-fixed";
153
+
regulator-name = "vcamio";
154
+
regulator-min-microvolt = <1800000>;
155
+
regulator-max-microvolt = <1800000>;
156
+
regulator-enable-ramp-delay = <325>;
157
+
};
158
+
159
+
mt6358_vcamd_reg: ldo_vcamd {
160
+
regulator-name = "vcamd";
161
+
regulator-min-microvolt = <900000>;
162
+
regulator-max-microvolt = <1800000>;
163
+
regulator-enable-ramp-delay = <325>;
164
+
};
165
+
166
+
mt6358_vcn18_reg: ldo_vcn18 {
167
+
compatible = "regulator-fixed";
168
+
regulator-name = "vcn18";
169
+
regulator-min-microvolt = <1800000>;
170
+
regulator-max-microvolt = <1800000>;
171
+
regulator-enable-ramp-delay = <270>;
172
+
};
173
+
174
+
mt6358_vfe28_reg: ldo_vfe28 {
175
+
compatible = "regulator-fixed";
176
+
regulator-name = "vfe28";
177
+
regulator-min-microvolt = <2800000>;
178
+
regulator-max-microvolt = <2800000>;
179
+
regulator-enable-ramp-delay = <270>;
180
+
};
181
+
182
+
mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
183
+
regulator-name = "vsram_proc11";
184
+
regulator-min-microvolt = <500000>;
185
+
regulator-max-microvolt = <1293750>;
186
+
regulator-ramp-delay = <6250>;
187
+
regulator-enable-ramp-delay = <240>;
188
+
regulator-always-on;
189
+
};
190
+
191
+
mt6358_vcn28_reg: ldo_vcn28 {
192
+
compatible = "regulator-fixed";
193
+
regulator-name = "vcn28";
194
+
regulator-min-microvolt = <2800000>;
195
+
regulator-max-microvolt = <2800000>;
196
+
regulator-enable-ramp-delay = <270>;
197
+
};
198
+
199
+
mt6358_vsram_others_reg: ldo_vsram_others {
200
+
regulator-name = "vsram_others";
201
+
regulator-min-microvolt = <500000>;
202
+
regulator-max-microvolt = <1293750>;
203
+
regulator-ramp-delay = <6250>;
204
+
regulator-enable-ramp-delay = <240>;
205
+
regulator-always-on;
206
+
};
207
+
208
+
mt6358_vsram_gpu_reg: ldo_vsram_gpu {
209
+
regulator-name = "vsram_gpu";
210
+
regulator-min-microvolt = <500000>;
211
+
regulator-max-microvolt = <1293750>;
212
+
regulator-ramp-delay = <6250>;
213
+
regulator-enable-ramp-delay = <240>;
214
+
};
215
+
216
+
mt6358_vxo22_reg: ldo_vxo22 {
217
+
compatible = "regulator-fixed";
218
+
regulator-name = "vxo22";
219
+
regulator-min-microvolt = <2200000>;
220
+
regulator-max-microvolt = <2200000>;
221
+
regulator-enable-ramp-delay = <120>;
222
+
regulator-always-on;
223
+
};
224
+
225
+
mt6358_vefuse_reg: ldo_vefuse {
226
+
regulator-name = "vefuse";
227
+
regulator-min-microvolt = <1700000>;
228
+
regulator-max-microvolt = <1900000>;
229
+
regulator-enable-ramp-delay = <270>;
230
+
};
231
+
232
+
mt6358_vaux18_reg: ldo_vaux18 {
233
+
compatible = "regulator-fixed";
234
+
regulator-name = "vaux18";
235
+
regulator-min-microvolt = <1800000>;
236
+
regulator-max-microvolt = <1800000>;
237
+
regulator-enable-ramp-delay = <270>;
238
+
};
239
+
240
+
mt6358_vmch_reg: ldo_vmch {
241
+
regulator-name = "vmch";
242
+
regulator-min-microvolt = <2900000>;
243
+
regulator-max-microvolt = <3300000>;
244
+
regulator-enable-ramp-delay = <60>;
245
+
};
246
+
247
+
mt6358_vbif28_reg: ldo_vbif28 {
248
+
compatible = "regulator-fixed";
249
+
regulator-name = "vbif28";
250
+
regulator-min-microvolt = <2800000>;
251
+
regulator-max-microvolt = <2800000>;
252
+
regulator-enable-ramp-delay = <270>;
253
+
};
254
+
255
+
mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
256
+
regulator-name = "vsram_proc12";
257
+
regulator-min-microvolt = <500000>;
258
+
regulator-max-microvolt = <1293750>;
259
+
regulator-ramp-delay = <6250>;
260
+
regulator-enable-ramp-delay = <240>;
261
+
regulator-always-on;
262
+
};
263
+
264
+
mt6358_vcama1_reg: ldo_vcama1 {
265
+
regulator-name = "vcama1";
266
+
regulator-min-microvolt = <1800000>;
267
+
regulator-max-microvolt = <3000000>;
268
+
regulator-enable-ramp-delay = <325>;
269
+
};
270
+
271
+
mt6358_vemc_reg: ldo_vemc {
272
+
regulator-name = "vemc";
273
+
regulator-min-microvolt = <2900000>;
274
+
regulator-max-microvolt = <3300000>;
275
+
regulator-enable-ramp-delay = <60>;
276
+
};
277
+
278
+
mt6358_vio28_reg: ldo_vio28 {
279
+
compatible = "regulator-fixed";
280
+
regulator-name = "vio28";
281
+
regulator-min-microvolt = <2800000>;
282
+
regulator-max-microvolt = <2800000>;
283
+
regulator-enable-ramp-delay = <270>;
284
+
};
285
+
286
+
mt6358_va12_reg: ldo_va12 {
287
+
compatible = "regulator-fixed";
288
+
regulator-name = "va12";
289
+
regulator-min-microvolt = <1200000>;
290
+
regulator-max-microvolt = <1200000>;
291
+
regulator-enable-ramp-delay = <270>;
292
+
regulator-always-on;
293
+
};
294
+
295
+
mt6358_vrf18_reg: ldo_vrf18 {
296
+
compatible = "regulator-fixed";
297
+
regulator-name = "vrf18";
298
+
regulator-min-microvolt = <1800000>;
299
+
regulator-max-microvolt = <1800000>;
300
+
regulator-enable-ramp-delay = <120>;
301
+
};
302
+
303
+
mt6358_vcn33_bt_reg: ldo_vcn33_bt {
304
+
regulator-name = "vcn33_bt";
305
+
regulator-min-microvolt = <3300000>;
306
+
regulator-max-microvolt = <3500000>;
307
+
regulator-enable-ramp-delay = <270>;
308
+
};
309
+
310
+
mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
311
+
regulator-name = "vcn33_wifi";
312
+
regulator-min-microvolt = <3300000>;
313
+
regulator-max-microvolt = <3500000>;
314
+
regulator-enable-ramp-delay = <270>;
315
+
};
316
+
317
+
mt6358_vcama2_reg: ldo_vcama2 {
318
+
regulator-name = "vcama2";
319
+
regulator-min-microvolt = <1800000>;
320
+
regulator-max-microvolt = <3000000>;
321
+
regulator-enable-ramp-delay = <325>;
322
+
};
323
+
324
+
mt6358_vmc_reg: ldo_vmc {
325
+
regulator-name = "vmc";
326
+
regulator-min-microvolt = <1800000>;
327
+
regulator-max-microvolt = <3300000>;
328
+
regulator-enable-ramp-delay = <60>;
329
+
};
330
+
331
+
mt6358_vldo28_reg: ldo_vldo28 {
332
+
regulator-name = "vldo28";
333
+
regulator-min-microvolt = <2800000>;
334
+
regulator-max-microvolt = <3000000>;
335
+
regulator-enable-ramp-delay = <270>;
336
+
};
337
+
338
+
mt6358_vaud28_reg: ldo_vaud28 {
339
+
compatible = "regulator-fixed";
340
+
regulator-name = "vaud28";
341
+
regulator-min-microvolt = <2800000>;
342
+
regulator-max-microvolt = <2800000>;
343
+
regulator-enable-ramp-delay = <270>;
344
+
};
345
+
346
+
mt6358_vsim2_reg: ldo_vsim2 {
347
+
regulator-name = "vsim2";
348
+
regulator-min-microvolt = <1700000>;
349
+
regulator-max-microvolt = <3100000>;
350
+
regulator-enable-ramp-delay = <540>;
351
+
};
352
+
};
353
+
354
+
mt6358rtc: mt6358rtc {
355
+
compatible = "mediatek,mt6358-rtc";
356
+
};
357
+
};
358
+
};
+1
-1
arch/arm64/boot/dts/mediatek/mt6797.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt6797.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8173.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8173.dtsi
+147
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+147
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
···
7
7
8
8
/dts-v1/;
9
9
#include "mt8183.dtsi"
10
+
#include "mt6358.dtsi"
10
11
11
12
/ {
12
13
model = "MediaTek MT8183 evaluation board";
···
73
72
clock-frequency = <1000000>;
74
73
};
75
74
75
+
&mmc0 {
76
+
status = "okay";
77
+
pinctrl-names = "default", "state_uhs";
78
+
pinctrl-0 = <&mmc0_pins_default>;
79
+
pinctrl-1 = <&mmc0_pins_uhs>;
80
+
bus-width = <8>;
81
+
max-frequency = <200000000>;
82
+
cap-mmc-highspeed;
83
+
mmc-hs200-1_8v;
84
+
mmc-hs400-1_8v;
85
+
cap-mmc-hw-reset;
86
+
no-sdio;
87
+
no-sd;
88
+
hs400-ds-delay = <0x12814>;
89
+
vmmc-supply = <&mt6358_vemc_reg>;
90
+
vqmmc-supply = <&mt6358_vio18_reg>;
91
+
assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
92
+
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
93
+
non-removable;
94
+
};
95
+
96
+
&mmc1 {
97
+
status = "okay";
98
+
pinctrl-names = "default", "state_uhs";
99
+
pinctrl-0 = <&mmc1_pins_default>;
100
+
pinctrl-1 = <&mmc1_pins_uhs>;
101
+
bus-width = <4>;
102
+
max-frequency = <200000000>;
103
+
cap-sd-highspeed;
104
+
sd-uhs-sdr50;
105
+
sd-uhs-sdr104;
106
+
cap-sdio-irq;
107
+
no-mmc;
108
+
no-sd;
109
+
vmmc-supply = <&mt6358_vmch_reg>;
110
+
vqmmc-supply = <&mt6358_vmc_reg>;
111
+
keep-power-in-suspend;
112
+
enable-sdio-wakeup;
113
+
non-removable;
114
+
};
115
+
76
116
&pio {
77
117
i2c_pins_0: i2c0{
78
118
pins_i2c{
···
176
134
<PINMUX_GPIO87__FUNC_SPI0_MO>,
177
135
<PINMUX_GPIO88__FUNC_SPI0_CLK>;
178
136
bias-disable;
137
+
};
138
+
};
139
+
140
+
mmc0_pins_default: mmc0default {
141
+
pins_cmd_dat {
142
+
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
143
+
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
144
+
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
145
+
<PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
146
+
<PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
147
+
<PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
148
+
<PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
149
+
<PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
150
+
<PINMUX_GPIO122__FUNC_MSDC0_CMD>;
151
+
input-enable;
152
+
bias-pull-up;
153
+
};
154
+
155
+
pins_clk {
156
+
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
157
+
bias-pull-down;
158
+
};
159
+
160
+
pins_rst {
161
+
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
162
+
bias-pull-up;
163
+
};
164
+
};
165
+
166
+
mmc0_pins_uhs: mmc0@0{
167
+
pins_cmd_dat {
168
+
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
169
+
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
170
+
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
171
+
<PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
172
+
<PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
173
+
<PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
174
+
<PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
175
+
<PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
176
+
<PINMUX_GPIO122__FUNC_MSDC0_CMD>;
177
+
input-enable;
178
+
drive-strength = <MTK_DRIVE_10mA>;
179
+
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
180
+
};
181
+
182
+
pins_clk {
183
+
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
184
+
drive-strength = <MTK_DRIVE_10mA>;
185
+
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
186
+
};
187
+
188
+
pins_ds {
189
+
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
190
+
drive-strength = <MTK_DRIVE_10mA>;
191
+
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
192
+
};
193
+
194
+
pins_rst {
195
+
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
196
+
drive-strength = <MTK_DRIVE_10mA>;
197
+
bias-pull-up;
198
+
};
199
+
};
200
+
201
+
mmc1_pins_default: mmc1default {
202
+
pins_cmd_dat {
203
+
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
204
+
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
205
+
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
206
+
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
207
+
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
208
+
input-enable;
209
+
bias-pull-up;
210
+
};
211
+
212
+
pins_clk {
213
+
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
214
+
input-enable;
215
+
bias-pull-down;
216
+
};
217
+
218
+
pins_pmu {
219
+
pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
220
+
<PINMUX_GPIO166__FUNC_GPIO166>;
221
+
output-high;
222
+
};
223
+
};
224
+
225
+
mmc1_pins_uhs: mmc1@0{
226
+
pins_cmd_dat {
227
+
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
228
+
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
229
+
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
230
+
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
231
+
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
232
+
drive-strength = <MTK_DRIVE_6mA>;
233
+
input-enable;
234
+
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
235
+
};
236
+
237
+
pins_clk {
238
+
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
239
+
drive-strength = <MTK_DRIVE_6mA>;
240
+
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
241
+
input-enable;
179
242
};
180
243
};
181
244
+24
arch/arm64/boot/dts/mediatek/mt8183.dtsi
+24
arch/arm64/boot/dts/mediatek/mt8183.dtsi
···
648
648
#clock-cells = <1>;
649
649
};
650
650
651
+
mmc0: mmc@11230000 {
652
+
compatible = "mediatek,mt8183-mmc";
653
+
reg = <0 0x11230000 0 0x1000>,
654
+
<0 0x11f50000 0 0x1000>;
655
+
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
656
+
clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
657
+
<&infracfg CLK_INFRA_MSDC0>,
658
+
<&infracfg CLK_INFRA_MSDC0_SCK>;
659
+
clock-names = "source", "hclk", "source_cg";
660
+
status = "disabled";
661
+
};
662
+
663
+
mmc1: mmc@11240000 {
664
+
compatible = "mediatek,mt8183-mmc";
665
+
reg = <0 0x11240000 0 0x1000>,
666
+
<0 0x11e10000 0 0x1000>;
667
+
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
668
+
clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
669
+
<&infracfg CLK_INFRA_MSDC1>,
670
+
<&infracfg CLK_INFRA_MSDC1_SCK>;
671
+
clock-names = "source", "hclk", "source_cg";
672
+
status = "disabled";
673
+
};
674
+
651
675
efuse: efuse@11f10000 {
652
676
compatible = "mediatek,mt8183-efuse",
653
677
"mediatek,efuse";