ARM64: dts: meson-gx: fix UART pclk clock name

The clock-names for pclk was wrongly set to "core", but the bindings
specifies "pclk".
This was not cathed until the legacy non-documented bindings were removed.

Reported-by: Andreas Färber <afaerber@suse.de>
Fixes: f72d6f6037b7 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

authored by Neil Armstrong and committed by Kevin Hilman 39005e56 044d71bc

+5 -5
+2 -2
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
··· 753 754 &uart_B { 755 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 756 - clock-names = "xtal", "core", "baud"; 757 }; 758 759 &uart_C { 760 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 761 - clock-names = "xtal", "core", "baud"; 762 }; 763 764 &vpu {
··· 753 754 &uart_B { 755 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 756 + clock-names = "xtal", "pclk", "baud"; 757 }; 758 759 &uart_C { 760 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 761 + clock-names = "xtal", "pclk", "baud"; 762 }; 763 764 &vpu {
+3 -3
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
··· 688 689 &uart_A { 690 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 691 - clock-names = "xtal", "core", "baud"; 692 }; 693 694 &uart_AO { ··· 703 704 &uart_B { 705 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 706 - clock-names = "xtal", "core", "baud"; 707 }; 708 709 &uart_C { 710 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 711 - clock-names = "xtal", "core", "baud"; 712 }; 713 714 &vpu {
··· 688 689 &uart_A { 690 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 691 + clock-names = "xtal", "pclk", "baud"; 692 }; 693 694 &uart_AO { ··· 703 704 &uart_B { 705 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 706 + clock-names = "xtal", "pclk", "baud"; 707 }; 708 709 &uart_C { 710 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 711 + clock-names = "xtal", "pclk", "baud"; 712 }; 713 714 &vpu {