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dt-bindings: clock: add QCOM SM6115 display clock bindings
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM6115 SoC.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[bjorn: Minor fix of binding description]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220911164635.182973-2-a39.skl@gmail.com
authored by
Adam Skladowski
and committed by
Bjorn Andersson
38557c6f
1a58ee13
+106
+70
Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock Controller for SM6115
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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description: |
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Qualcomm display clock control module which supports the clocks and
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power domains on SM6115.
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See also:
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include/dt-bindings/clock/qcom,sm6115-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,sm6115-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board sleep clock
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: GPLL0 DISP DIV clock from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm6115.h>
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clock-controller@5f00000 {
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compatible = "qcom,sm6115-dispcc";
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reg = <0x5f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&sleep_clk>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,sm6115-dispcc.h
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include/dt-bindings/clock/qcom,sm6115-dispcc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_PLL0_OUT_MAIN 1
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#define DISP_CC_MDSS_AHB_CLK 2
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#define DISP_CC_MDSS_AHB_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_CLK 4
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK 8
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#define DISP_CC_MDSS_ESC0_CLK_SRC 9
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#define DISP_CC_MDSS_MDP_CLK 10
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#define DISP_CC_MDSS_MDP_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_LUT_CLK 12
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 13
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#define DISP_CC_MDSS_PCLK0_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 15
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#define DISP_CC_MDSS_ROT_CLK 16
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#define DISP_CC_MDSS_ROT_CLK_SRC 17
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#define DISP_CC_MDSS_VSYNC_CLK 18
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 19
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#define DISP_CC_SLEEP_CLK 20
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#define DISP_CC_SLEEP_CLK_SRC 21
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#endif