[ALSA] cs4281 - Fix the check of timeout in probe

Fix the check of timeout in probe routines to work properly
reagrdless of HZ (ALSA bug#1976).

Signed-off-by: Takashi Iwai <tiwai@suse.de>

authored by Takashi Iwai and committed by Jaroslav Kysela 38223daa e860f000

+13 -13
+13 -13
sound/pci/cs4281.c
··· 1416 1416 static int snd_cs4281_chip_init(struct cs4281 *chip) 1417 1417 { 1418 1418 unsigned int tmp; 1419 - int timeout; 1419 + unsigned long end_time; 1420 1420 int retry_count = 2; 1421 1421 1422 1422 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ ··· 1496 1496 /* 1497 1497 * Wait for the DLL ready signal from the clock logic. 1498 1498 */ 1499 - timeout = 100; 1499 + end_time = jiffies + HZ; 1500 1500 do { 1501 1501 /* 1502 1502 * Read the AC97 status register to see if we've seen a CODEC ··· 1504 1504 */ 1505 1505 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1506 1506 goto __ok0; 1507 - msleep(1); 1508 - } while (timeout-- > 0); 1507 + schedule_timeout_uninterruptible(1); 1508 + } while (time_after_eq(end_time, jiffies)); 1509 1509 1510 1510 snd_printk(KERN_ERR "DLLRDY not seen\n"); 1511 1511 return -EIO; ··· 1522 1522 /* 1523 1523 * Wait for the codec ready signal from the AC97 codec. 1524 1524 */ 1525 - timeout = 100; 1525 + end_time = jiffies + HZ; 1526 1526 do { 1527 1527 /* 1528 1528 * Read the AC97 status register to see if we've seen a CODEC ··· 1530 1530 */ 1531 1531 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1532 1532 goto __ok1; 1533 - msleep(1); 1534 - } while (timeout-- > 0); 1533 + schedule_timeout_uninterruptible(1); 1534 + } while (time_after_eq(end_time, jiffies)); 1535 1535 1536 1536 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1537 1537 return -EIO; 1538 1538 1539 1539 __ok1: 1540 1540 if (chip->dual_codec) { 1541 - timeout = 100; 1541 + end_time = jiffies + HZ; 1542 1542 do { 1543 1543 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1544 1544 goto __codec2_ok; 1545 - msleep(1); 1546 - } while (timeout-- > 0); 1545 + schedule_timeout_uninterruptible(1); 1546 + } while (time_after_eq(end_time, jiffies)); 1547 1547 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); 1548 1548 chip->dual_codec = 0; 1549 1549 __codec2_ok: ; ··· 1561 1561 * the codec is pumping ADC data across the AC-link. 1562 1562 */ 1563 1563 1564 - timeout = 100; 1564 + end_time = jiffies + HZ; 1565 1565 do { 1566 1566 /* 1567 1567 * Read the input slot valid register and see if input slots 3 ··· 1569 1569 */ 1570 1570 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1571 1571 goto __ok2; 1572 - msleep(1); 1573 - } while (timeout-- > 0); 1572 + schedule_timeout_uninterruptible(1); 1573 + } while (time_after_eq(end_time, jiffies)); 1574 1574 1575 1575 if (--retry_count > 0) 1576 1576 goto __retry;