tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
tools: arm64: Update sysreg.h header files
Created with the following:
cp include/linux/kasan-tags.h tools/include/linux/
cp arch/arm64/include/asm/sysreg.h tools/arch/arm64/include/asm/
Update the tools copy of sysreg.h so that the next commit to add a new
register doesn't have unrelated changes in it. Because the new version
of sysreg.h includes kasan-tags.h, that file also now needs to be copied
into tools.
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Clark <james.clark@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20250106142446.628923-3-james.clark@linaro.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
authored by
James Clark
and committed by
Marc Zyngier
38138762
c4a6ed85
+405
-8
+390
-8
tools/arch/arm64/include/asm/sysreg.h
+390
-8
tools/arch/arm64/include/asm/sysreg.h
···
11
11
12
12
#include <linux/bits.h>
13
13
#include <linux/stringify.h>
14
+
#include <linux/kasan-tags.h>
14
15
15
16
#include <asm/gpr-num.h>
16
17
···
109
108
#define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
110
109
#define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x))
111
110
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+
/* Register-based PAN access, for save/restore purposes */
112
+
#define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
113
+
112
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#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
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__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
114
116
···
126
122
#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127
123
#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128
124
#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
125
+
126
+
#define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
127
+
#define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
128
+
#define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
129
+
130
+
#define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
131
+
#define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
132
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#define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
133
+
134
+
#define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
135
+
#define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
136
+
#define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
137
+
138
+
#define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
139
+
140
+
#define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
141
+
#define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
142
+
#define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
143
+
144
+
#define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
145
+
#define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
146
+
#define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
147
+
148
+
#define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
149
+
#define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
150
+
#define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
151
+
152
+
/* Data cache zero operations */
153
+
#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
154
+
#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
155
+
#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
129
156
130
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/*
131
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* Automatically generated definitions for system registers, the
···
196
161
#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197
162
#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198
163
#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
164
+
165
+
#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
166
+
#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
167
+
#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
168
+
#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
169
+
#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
170
+
#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
171
+
#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
172
+
173
+
#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
174
+
#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
175
+
#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
176
+
177
+
#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
178
+
#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
179
+
#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
180
+
#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
181
+
#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
182
+
#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
183
+
#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
184
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#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
185
+
#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
186
+
#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
187
+
#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
188
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#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
189
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#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
190
+
#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
191
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#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
192
+
#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
193
+
#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
194
+
#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
195
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#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
196
+
#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
197
+
#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
198
+
#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
199
+
#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
200
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#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
201
+
#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
202
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#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
203
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#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
204
+
#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
205
+
#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
206
+
#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
207
+
#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
208
+
#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
209
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#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
210
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#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
211
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#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
212
+
#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
213
+
#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
214
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#define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
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#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
216
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#define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
217
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#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
218
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#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
219
+
#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
220
+
#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
221
+
#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
222
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#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
223
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#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
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#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
225
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#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
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#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
227
+
#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
228
+
#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
229
+
#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
230
+
#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
231
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#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
232
+
#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
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+
#define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
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#define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
235
+
#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
236
+
#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
237
+
238
+
/* ETM */
239
+
#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
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+
241
+
#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
199
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200
243
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
201
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#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
···
315
202
#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
316
203
#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
317
204
#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
205
+
#define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
206
+
#define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
207
+
#define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
318
208
#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
319
209
#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
210
+
#define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
211
+
#define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
320
212
#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
321
213
#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
322
214
323
215
#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
324
216
325
217
#define SYS_PAR_EL1_F BIT(0)
218
+
/* When PAR_EL1.F == 1 */
326
219
#define SYS_PAR_EL1_FST GENMASK(6, 1)
220
+
#define SYS_PAR_EL1_PTW BIT(8)
221
+
#define SYS_PAR_EL1_S BIT(9)
222
+
#define SYS_PAR_EL1_AssuredOnly BIT(12)
223
+
#define SYS_PAR_EL1_TopLevel BIT(13)
224
+
#define SYS_PAR_EL1_Overlay BIT(14)
225
+
#define SYS_PAR_EL1_DirtyBit BIT(15)
226
+
#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)
227
+
#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
228
+
#define SYS_PAR_EL1_RES1 BIT(11)
229
+
/* When PAR_EL1.F == 0 */
230
+
#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
231
+
#define SYS_PAR_EL1_NS BIT(9)
232
+
#define SYS_PAR_EL1_F0_IMPDEF BIT(10)
233
+
#define SYS_PAR_EL1_NSE BIT(11)
234
+
#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)
235
+
#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)
236
+
#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
327
237
328
238
/*** Statistical Profiling Extension ***/
329
239
#define PMSEVFR_EL1_RES0_IMP \
···
410
274
#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
411
275
#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
412
276
277
+
#define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
278
+
413
279
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
414
280
415
281
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
···
424
286
#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
425
287
#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
426
288
#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
427
-
#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
428
289
#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
429
290
#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
430
291
#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
···
506
369
507
370
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
508
371
#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
372
+
#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
509
373
#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
510
374
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
511
375
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
···
520
382
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
521
383
522
384
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
523
-
#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
524
-
#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
385
+
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
525
386
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
526
387
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
527
388
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
528
389
#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
390
+
#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
391
+
#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
392
+
#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
393
+
#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
529
394
#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
530
395
#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
531
396
#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
···
590
449
591
450
#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
592
451
#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
452
+
#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
453
+
454
+
#define __AMEV_op2(m) (m & 0x7)
455
+
#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
456
+
#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
457
+
#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
458
+
#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
459
+
#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
593
460
594
461
#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
595
462
#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
463
+
#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
464
+
#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
465
+
#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
466
+
#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
467
+
#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
468
+
#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
596
469
597
470
/* VHE encodings for architectural EL0/1 system registers */
471
+
#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
598
472
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
473
+
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
474
+
#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
475
+
#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
476
+
#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
477
+
#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
599
478
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
600
479
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
601
480
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
481
+
#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
602
482
#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
603
483
#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
604
484
#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
605
485
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
606
486
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
607
487
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
488
+
#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
489
+
#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
608
490
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
609
491
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
610
492
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
493
+
#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
494
+
#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
611
495
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
612
496
#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
613
497
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
···
642
476
#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
643
477
644
478
#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
479
+
480
+
/* AT instructions */
481
+
#define AT_Op0 1
482
+
#define AT_CRn 7
483
+
484
+
#define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
485
+
#define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
486
+
#define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
487
+
#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
488
+
#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
489
+
#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
490
+
#define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
491
+
#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
492
+
#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
493
+
#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
494
+
#define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
495
+
#define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
496
+
#define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
497
+
#define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
498
+
499
+
/* TLBI instructions */
500
+
#define TLBI_Op0 1
501
+
502
+
#define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */
503
+
#define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */
504
+
505
+
#define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
506
+
#define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
507
+
508
+
#define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
509
+
#define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
510
+
#define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
511
+
#define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
512
+
#define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
513
+
#define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
514
+
#define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
515
+
#define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
516
+
517
+
#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
518
+
#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
519
+
#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
520
+
#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
521
+
#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
522
+
#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
523
+
#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
524
+
#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
525
+
#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
526
+
#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
527
+
#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
528
+
#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
529
+
#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
530
+
#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
531
+
#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
532
+
#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
533
+
#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
534
+
#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
535
+
#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
536
+
#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
537
+
#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
538
+
#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
539
+
#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
540
+
#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
541
+
#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
542
+
#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
543
+
#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
544
+
#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
545
+
#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
546
+
#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
547
+
#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
548
+
#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
549
+
#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
550
+
#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
551
+
#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
552
+
#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
553
+
#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
554
+
#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
555
+
#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
556
+
#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
557
+
#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
558
+
#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
559
+
#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
560
+
#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
561
+
#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
562
+
#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
563
+
#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
564
+
#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
565
+
#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
566
+
#define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
567
+
#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
568
+
#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
569
+
#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
570
+
#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
571
+
#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
572
+
#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
573
+
#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
574
+
#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
575
+
#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
576
+
#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
577
+
#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
578
+
#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
579
+
#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
580
+
#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
581
+
#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
582
+
#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
583
+
#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
584
+
#define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
585
+
#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
586
+
#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
587
+
#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
588
+
#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
589
+
#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
590
+
#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
591
+
#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
592
+
#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
593
+
#define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
594
+
#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
595
+
#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
596
+
#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
597
+
#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
598
+
#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
599
+
#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
600
+
#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
601
+
#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
602
+
#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
603
+
#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
604
+
#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
605
+
#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
606
+
#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
607
+
#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
608
+
#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
609
+
#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
610
+
#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
611
+
#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
612
+
#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
613
+
#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
614
+
#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
615
+
#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
616
+
#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
617
+
#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
618
+
#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
619
+
#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
620
+
#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
621
+
#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
622
+
#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
623
+
#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
624
+
#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
625
+
#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
626
+
#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
627
+
#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
628
+
#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
629
+
#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
630
+
#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
631
+
#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
632
+
#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
633
+
#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
634
+
#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
635
+
#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
636
+
#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
637
+
#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
638
+
#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
639
+
#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
640
+
#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
641
+
#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
642
+
#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
643
+
644
+
/* Misc instructions */
645
+
#define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
646
+
#define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
647
+
#define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
648
+
#define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
649
+
650
+
#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
651
+
#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
652
+
#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
653
+
#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
654
+
#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
655
+
#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
645
656
646
657
/* Common SCTLR_ELx flags. */
647
658
#define SCTLR_ELx_ENTP2 (BIT(60))
···
898
555
/* Position the attr at the correct index */
899
556
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
900
557
901
-
/* id_aa64pfr0 */
902
-
#define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1
903
-
#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2
904
-
905
558
/* id_aa64mmfr0 */
906
559
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
560
+
#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
907
561
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
908
562
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
909
563
#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
910
564
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
565
+
#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
911
566
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
912
567
913
568
#define ARM64_MIN_PARANGE_BITS 32
···
913
572
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
914
573
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
915
574
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
575
+
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3
916
576
#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
917
577
918
578
#ifdef CONFIG_ARM64_PA_BITS_52
···
924
582
925
583
#if defined(CONFIG_ARM64_4K_PAGES)
926
584
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
585
+
#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
927
586
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
928
587
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
929
588
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
930
589
#elif defined(CONFIG_ARM64_16K_PAGES)
931
590
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
591
+
#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
932
592
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
933
593
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
934
594
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
···
953
609
/* GCR_EL1 Definitions */
954
610
#define SYS_GCR_EL1_RRND (BIT(16))
955
611
#define SYS_GCR_EL1_EXCL_MASK 0xffffUL
612
+
613
+
#ifdef CONFIG_KASAN_HW_TAGS
614
+
/*
615
+
* KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
616
+
* only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
617
+
*/
618
+
#define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
619
+
#define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
620
+
#define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
621
+
#define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
622
+
#else
623
+
#define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
624
+
#endif
956
625
957
626
#define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
958
627
···
1073
716
1074
717
#define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4))
1075
718
719
+
/*
720
+
* Permission Overlay Extension (POE) permission encodings.
721
+
*/
722
+
#define POE_NONE UL(0x0)
723
+
#define POE_R UL(0x1)
724
+
#define POE_X UL(0x2)
725
+
#define POE_RX UL(0x3)
726
+
#define POE_W UL(0x4)
727
+
#define POE_RW UL(0x5)
728
+
#define POE_XW UL(0x6)
729
+
#define POE_RXW UL(0x7)
730
+
#define POE_MASK UL(0xf)
731
+
732
+
/* Initial value for Permission Overlay Extension for EL0 */
733
+
#define POR_EL0_INIT POE_RXW
734
+
1076
735
#define ARM64_FEATURE_FIELD_BITS 4
1077
736
1078
737
/* Defined for compatibility only, do not add new users. */
···
1162
789
/*
1163
790
* For registers without architectural names, or simply unsupported by
1164
791
* GAS.
792
+
*
793
+
* __check_r forces warnings to be generated by the compiler when
794
+
* evaluating r which wouldn't normally happen due to being passed to
795
+
* the assembler via __stringify(r).
1165
796
*/
1166
797
#define read_sysreg_s(r) ({ \
1167
798
u64 __val; \
799
+
u32 __maybe_unused __check_r = (u32)(r); \
1168
800
asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1169
801
__val; \
1170
802
})
1171
803
1172
804
#define write_sysreg_s(v, r) do { \
1173
805
u64 __val = (u64)(v); \
806
+
u32 __maybe_unused __check_r = (u32)(r); \
1174
807
asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
1175
808
} while (0)
1176
809
···
1206
827
par; \
1207
828
})
1208
829
830
+
#define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val
831
+
1209
832
#define SYS_FIELD_GET(reg, field, val) \
1210
833
FIELD_GET(reg##_##field##_MASK, val)
1211
834
···
1215
834
FIELD_PREP(reg##_##field##_MASK, val)
1216
835
1217
836
#define SYS_FIELD_PREP_ENUM(reg, field, val) \
1218
-
FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
837
+
FIELD_PREP(reg##_##field##_MASK, \
838
+
SYS_FIELD_VALUE(reg, field, val))
1219
839
1220
840
#endif
1221
841