tjh.dev / kernel
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ARM: dts: socfpga: update missing reset property peripherals

Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and
watchdog on base socfpga and socfpga_arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Dinh Nguyen 37f7453a d031ee53

+30
+12
arch/arm/boot/dts/socfpga.dtsi
··· 585 585 compatible = "snps,dw-apb-gpio"; 586 586 reg = <0xff708000 0x1000>; 587 587 clocks = <&l4_mp_clk>; 588 + resets = <&rst GPIO0_RESET>; 588 589 status = "disabled"; 589 590 590 591 porta: gpio-controller@0 { ··· 606 605 compatible = "snps,dw-apb-gpio"; 607 606 reg = <0xff709000 0x1000>; 608 607 clocks = <&l4_mp_clk>; 608 + resets = <&rst GPIO1_RESET>; 609 609 status = "disabled"; 610 610 611 611 portb: gpio-controller@0 { ··· 627 625 compatible = "snps,dw-apb-gpio"; 628 626 reg = <0xff70a000 0x1000>; 629 627 clocks = <&l4_mp_clk>; 628 + resets = <&rst GPIO2_RESET>; 630 629 status = "disabled"; 631 630 632 631 portc: gpio-controller@0 { ··· 738 735 #size-cells = <0>; 739 736 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 740 737 clock-names = "biu", "ciu"; 738 + resets = <&rst SDMMC_RESET>; 741 739 status = "disabled"; 742 740 }; 743 741 ··· 752 748 interrupts = <0x0 0x90 0x4>; 753 749 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 754 750 clock-names = "nand", "nand_x", "ecc"; 751 + resets = <&rst NAND_RESET>; 755 752 status = "disabled"; 756 753 }; 757 754 ··· 772 767 cdns,fifo-width = <4>; 773 768 cdns,trigger-address = <0x00000000>; 774 769 clocks = <&qspi_clk>; 770 + resets = <&rst QSPI_RESET>; 775 771 status = "disabled"; 776 772 }; 777 773 ··· 807 801 interrupts = <0 154 4>; 808 802 num-cs = <4>; 809 803 clocks = <&spi_m_clk>; 804 + resets = <&rst SPIM0_RESET>; 810 805 status = "disabled"; 811 806 }; 812 807 ··· 819 812 interrupts = <0 155 4>; 820 813 num-cs = <4>; 821 814 clocks = <&spi_m_clk>; 815 + resets = <&rst SPIM1_RESET>; 822 816 status = "disabled"; 823 817 }; 824 818 ··· 886 878 dmas = <&pdma 28>, 887 879 <&pdma 29>; 888 880 dma-names = "tx", "rx"; 881 + resets = <&rst UART0_RESET>; 889 882 }; 890 883 891 884 uart1: serial1@ffc03000 { ··· 899 890 dmas = <&pdma 30>, 900 891 <&pdma 31>; 901 892 dma-names = "tx", "rx"; 893 + resets = <&rst UART1_RESET>; 902 894 }; 903 895 904 896 usbphy0: usbphy { ··· 939 929 reg = <0xffd02000 0x1000>; 940 930 interrupts = <0 171 4>; 941 931 clocks = <&osc1>; 932 + resets = <&rst L4WD0_RESET>; 942 933 status = "disabled"; 943 934 }; 944 935 ··· 948 937 reg = <0xffd03000 0x1000>; 949 938 interrupts = <0 172 4>; 950 939 clocks = <&osc1>; 940 + resets = <&rst L4WD1_RESET>; 951 941 status = "disabled"; 952 942 }; 953 943 };
+18
arch/arm/boot/dts/socfpga_arria10.dtsi
··· 470 470 tx-fifo-depth = <4096>; 471 471 rx-fifo-depth = <16384>; 472 472 clocks = <&l4_mp_clk>; 473 + resets = <&rst EMAC2_RESET>; 473 474 clock-names = "stmmaceth"; 474 475 snps,axi-config = <&socfpga_axi_setup>; 475 476 status = "disabled"; ··· 481 480 #size-cells = <0>; 482 481 compatible = "snps,dw-apb-gpio"; 483 482 reg = <0xffc02900 0x100>; 483 + resets = <&rst GPIO0_RESET>; 484 484 status = "disabled"; 485 485 486 486 porta: gpio-controller@0 { ··· 501 499 #size-cells = <0>; 502 500 compatible = "snps,dw-apb-gpio"; 503 501 reg = <0xffc02a00 0x100>; 502 + resets = <&rst GPIO1_RESET>; 504 503 status = "disabled"; 505 504 506 505 portb: gpio-controller@0 { ··· 521 518 #size-cells = <0>; 522 519 compatible = "snps,dw-apb-gpio"; 523 520 reg = <0xffc02b00 0x100>; 521 + resets = <&rst GPIO2_RESET>; 524 522 status = "disabled"; 525 523 526 524 portc: gpio-controller@0 { ··· 552 548 reg = <0xffc02200 0x100>; 553 549 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 554 550 clocks = <&l4_sp_clk>; 551 + resets = <&rst I2C0_RESET>; 555 552 status = "disabled"; 556 553 }; 557 554 ··· 563 558 reg = <0xffc02300 0x100>; 564 559 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 565 560 clocks = <&l4_sp_clk>; 561 + resets = <&rst I2C1_RESET>; 566 562 status = "disabled"; 567 563 }; 568 564 ··· 574 568 reg = <0xffc02400 0x100>; 575 569 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 576 570 clocks = <&l4_sp_clk>; 571 + resets = <&rst I2C2_RESET>; 577 572 status = "disabled"; 578 573 }; 579 574 ··· 585 578 reg = <0xffc02500 0x100>; 586 579 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 587 580 clocks = <&l4_sp_clk>; 581 + resets = <&rst I2C3_RESET>; 588 582 status = "disabled"; 589 583 }; 590 584 ··· 596 588 reg = <0xffc02600 0x100>; 597 589 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 598 590 clocks = <&l4_sp_clk>; 591 + resets = <&rst I2C4_RESET>; 599 592 status = "disabled"; 600 593 }; 601 594 ··· 609 600 num-cs = <4>; 610 601 /*32bit_access;*/ 611 602 clocks = <&spi_m_clk>; 603 + resets = <&rst SPIM0_RESET>; 612 604 status = "disabled"; 613 605 }; 614 606 ··· 624 614 tx-dma-channel = <&pdma 16>; 625 615 rx-dma-channel = <&pdma 17>; 626 616 clocks = <&spi_m_clk>; 617 + resets = <&rst SPIM1_RESET>; 627 618 status = "disabled"; 628 619 }; 629 620 ··· 653 642 fifo-depth = <0x400>; 654 643 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 655 644 clock-names = "biu", "ciu"; 645 + resets = <&rst SDMMC_RESET>; 656 646 status = "disabled"; 657 647 }; 658 648 ··· 667 655 interrupts = <0 99 4>; 668 656 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 669 657 clock-names = "nand", "nand_x", "ecc"; 658 + resets = <&rst NAND_RESET>; 670 659 status = "disabled"; 671 660 }; 672 661 ··· 752 739 cdns,fifo-width = <4>; 753 740 cdns,trigger-address = <0x00000000>; 754 741 clocks = <&qspi_clk>; 742 + resets = <&rst QSPI_RESET>; 755 743 status = "disabled"; 756 744 }; 757 745 ··· 829 815 reg-shift = <2>; 830 816 reg-io-width = <4>; 831 817 clocks = <&l4_sp_clk>; 818 + resets = <&rst UART0_RESET>; 832 819 status = "disabled"; 833 820 }; 834 821 ··· 840 825 reg-shift = <2>; 841 826 reg-io-width = <4>; 842 827 clocks = <&l4_sp_clk>; 828 + resets = <&rst UART1_RESET>; 843 829 status = "disabled"; 844 830 }; 845 831 ··· 881 865 reg = <0xffd00200 0x100>; 882 866 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; 883 867 clocks = <&l4_sys_free_clk>; 868 + resets = <&rst L4WD0_RESET>; 884 869 status = "disabled"; 885 870 }; 886 871 ··· 890 873 reg = <0xffd00300 0x100>; 891 874 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 892 875 clocks = <&l4_sys_free_clk>; 876 + resets = <&rst L4WD1_RESET>; 893 877 status = "disabled"; 894 878 }; 895 879 };