Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: add cp queue registers print for gfx9_4_3

Add gfx9_4_3 print support of CP queue registers
for all queues to be used by devcoredump.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sunil Khatri and committed by
Alex Deucher
37ee1456 f9e491c8

+40 -2
+40 -2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 4362 4362 static void gfx_v9_4_3_ip_print(void *handle, struct drm_printer *p) 4363 4363 { 4364 4364 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4365 - uint32_t i; 4366 - uint32_t xcc_id, xcc_offset, num_xcc; 4365 + uint32_t i, j, k; 4366 + uint32_t xcc_id, xcc_offset, inst_offset; 4367 + uint32_t num_xcc, reg, num_inst; 4367 4368 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4368 4369 4369 4370 if (!adev->gfx.ip_dump_core) ··· 4379 4378 drm_printf(p, "%-50s \t 0x%08x\n", 4380 4379 gc_reg_list_9_4_3[i].reg_name, 4381 4380 adev->gfx.ip_dump_core[xcc_offset + i]); 4381 + } 4382 + 4383 + /* print compute queue registers for all instances */ 4384 + if (!adev->gfx.ip_dump_compute_queues) 4385 + return; 4386 + 4387 + num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4388 + adev->gfx.mec.num_queue_per_pipe; 4389 + 4390 + reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4391 + drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4392 + num_xcc, 4393 + adev->gfx.mec.num_mec, 4394 + adev->gfx.mec.num_pipe_per_mec, 4395 + adev->gfx.mec.num_queue_per_pipe); 4396 + 4397 + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4398 + xcc_offset = xcc_id * reg_count * num_inst; 4399 + inst_offset = 0; 4400 + for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4401 + for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4402 + for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4403 + drm_printf(p, 4404 + "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4405 + xcc_id, i, j, k); 4406 + for (reg = 0; reg < reg_count; reg++) { 4407 + drm_printf(p, 4408 + "%-50s \t 0x%08x\n", 4409 + gc_cp_reg_list_9_4_3[reg].reg_name, 4410 + adev->gfx.ip_dump_compute_queues 4411 + [xcc_offset + inst_offset + 4412 + reg]); 4413 + } 4414 + inst_offset += reg_count; 4415 + } 4416 + } 4417 + } 4382 4418 } 4383 4419 } 4384 4420