tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: fsl: cpm1: tsa: Use BIT(), GENMASK() and FIELD_PREP() macros
checkpatch.pl signals the following improvement for tsa.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-5-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
authored by
Herve Codina
and committed by
Christophe Leroy
37dbcd59
47a347ba
+68
-59
+68
-59
drivers/soc/fsl/qe/tsa.c
+68
-59
drivers/soc/fsl/qe/tsa.c
···
9
9
10
10
#include "tsa.h"
11
11
#include <dt-bindings/soc/cpm1-fsl,tsa.h>
12
+
#include <linux/bitfield.h>
12
13
#include <linux/clk.h>
13
14
#include <linux/io.h>
14
15
#include <linux/module.h>
···
20
19
21
20
22
21
/* TSA SI RAM routing tables entry */
23
-
#define TSA_SIRAM_ENTRY_LAST (1 << 16)
24
-
#define TSA_SIRAM_ENTRY_BYTE (1 << 17)
25
-
#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18)
26
-
#define TSA_SIRAM_ENTRY_CSEL_MASK (0x7 << 22)
27
-
#define TSA_SIRAM_ENTRY_CSEL_NU (0x0 << 22)
28
-
#define TSA_SIRAM_ENTRY_CSEL_SCC2 (0x2 << 22)
29
-
#define TSA_SIRAM_ENTRY_CSEL_SCC3 (0x3 << 22)
30
-
#define TSA_SIRAM_ENTRY_CSEL_SCC4 (0x4 << 22)
31
-
#define TSA_SIRAM_ENTRY_CSEL_SMC1 (0x5 << 22)
32
-
#define TSA_SIRAM_ENTRY_CSEL_SMC2 (0x6 << 22)
22
+
#define TSA_SIRAM_ENTRY_LAST BIT(16)
23
+
#define TSA_SIRAM_ENTRY_BYTE BIT(17)
24
+
#define TSA_SIRAM_ENTRY_CNT_MASK GENMASK(21, 18)
25
+
#define TSA_SIRAM_ENTRY_CNT(x) FIELD_PREP(TSA_SIRAM_ENTRY_CNT_MASK, x)
26
+
#define TSA_SIRAM_ENTRY_CSEL_MASK GENMASK(24, 22)
27
+
#define TSA_SIRAM_ENTRY_CSEL_NU FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x0)
28
+
#define TSA_SIRAM_ENTRY_CSEL_SCC2 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x2)
29
+
#define TSA_SIRAM_ENTRY_CSEL_SCC3 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x3)
30
+
#define TSA_SIRAM_ENTRY_CSEL_SCC4 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x4)
31
+
#define TSA_SIRAM_ENTRY_CSEL_SMC1 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x5)
32
+
#define TSA_SIRAM_ENTRY_CSEL_SMC2 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x6)
33
33
34
34
/* SI mode register (32 bits) */
35
35
#define TSA_SIMODE 0x00
36
-
#define TSA_SIMODE_SMC2 0x80000000
37
-
#define TSA_SIMODE_SMC1 0x00008000
38
-
#define TSA_SIMODE_TDMA(x) ((x) << 0)
39
-
#define TSA_SIMODE_TDMB(x) ((x) << 16)
40
-
#define TSA_SIMODE_TDM_MASK 0x0fff
41
-
#define TSA_SIMODE_TDM_SDM_MASK 0x0c00
42
-
#define TSA_SIMODE_TDM_SDM_NORM 0x0000
43
-
#define TSA_SIMODE_TDM_SDM_ECHO 0x0400
44
-
#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800
45
-
#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00
46
-
#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8)
47
-
#define TSA_SIMODE_TDM_DSC 0x0080
48
-
#define TSA_SIMODE_TDM_CRT 0x0040
49
-
#define TSA_SIMODE_TDM_STZ 0x0020
50
-
#define TSA_SIMODE_TDM_CE 0x0010
51
-
#define TSA_SIMODE_TDM_FE 0x0008
52
-
#define TSA_SIMODE_TDM_GM 0x0004
53
-
#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0)
36
+
#define TSA_SIMODE_SMC2 BIT(31)
37
+
#define TSA_SIMODE_SMC1 BIT(15)
38
+
#define TSA_SIMODE_TDMA_MASK GENMASK(11, 0)
39
+
#define TSA_SIMODE_TDMA(x) FIELD_PREP(TSA_SIMODE_TDMA_MASK, x)
40
+
#define TSA_SIMODE_TDMB_MASK GENMASK(27, 16)
41
+
#define TSA_SIMODE_TDMB(x) FIELD_PREP(TSA_SIMODE_TDMB_MASK, x)
42
+
#define TSA_SIMODE_TDM_MASK GENMASK(11, 0)
43
+
#define TSA_SIMODE_TDM_SDM_MASK GENMASK(11, 10)
44
+
#define TSA_SIMODE_TDM_SDM_NORM FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x0)
45
+
#define TSA_SIMODE_TDM_SDM_ECHO FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x1)
46
+
#define TSA_SIMODE_TDM_SDM_INTL_LOOP FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x2)
47
+
#define TSA_SIMODE_TDM_SDM_LOOP_CTRL FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x3)
48
+
#define TSA_SIMODE_TDM_RFSD_MASK GENMASK(9, 8)
49
+
#define TSA_SIMODE_TDM_RFSD(x) FIELD_PREP(TSA_SIMODE_TDM_RFSD_MASK, x)
50
+
#define TSA_SIMODE_TDM_DSC BIT(7)
51
+
#define TSA_SIMODE_TDM_CRT BIT(6)
52
+
#define TSA_SIMODE_TDM_STZ BIT(5)
53
+
#define TSA_SIMODE_TDM_CE BIT(4)
54
+
#define TSA_SIMODE_TDM_FE BIT(3)
55
+
#define TSA_SIMODE_TDM_GM BIT(2)
56
+
#define TSA_SIMODE_TDM_TFSD_MASK GENMASK(1, 0)
57
+
#define TSA_SIMODE_TDM_TFSD(x) FIELD_PREP(TSA_SIMODE_TDM_TFSD_MASK, x)
54
58
55
59
/* SI global mode register (8 bits) */
56
60
#define TSA_SIGMR 0x04
57
-
#define TSA_SIGMR_ENB (1<<3)
58
-
#define TSA_SIGMR_ENA (1<<2)
59
-
#define TSA_SIGMR_RDM_MASK 0x03
60
-
#define TSA_SIGMR_RDM_STATIC_TDMA 0x00
61
-
#define TSA_SIGMR_RDM_DYN_TDMA 0x01
62
-
#define TSA_SIGMR_RDM_STATIC_TDMAB 0x02
63
-
#define TSA_SIGMR_RDM_DYN_TDMAB 0x03
61
+
#define TSA_SIGMR_ENB BIT(3)
62
+
#define TSA_SIGMR_ENA BIT(2)
63
+
#define TSA_SIGMR_RDM_MASK GENMASK(1, 0)
64
+
#define TSA_SIGMR_RDM_STATIC_TDMA FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x0)
65
+
#define TSA_SIGMR_RDM_DYN_TDMA FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x1)
66
+
#define TSA_SIGMR_RDM_STATIC_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x2)
67
+
#define TSA_SIGMR_RDM_DYN_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x3)
64
68
65
69
/* SI status register (8 bits) */
66
70
#define TSA_SISTR 0x06
···
75
69
76
70
/* SI clock route register (32 bits) */
77
71
#define TSA_SICR 0x0C
78
-
#define TSA_SICR_SCC2(x) ((x) << 8)
79
-
#define TSA_SICR_SCC3(x) ((x) << 16)
80
-
#define TSA_SICR_SCC4(x) ((x) << 24)
81
-
#define TSA_SICR_SCC_MASK 0x0ff
82
-
#define TSA_SICR_SCC_GRX (1 << 7)
83
-
#define TSA_SICR_SCC_SCX_TSA (1 << 6)
84
-
#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3)
85
-
#define TSA_SICR_SCC_RXCS_BRG1 (0x0 << 3)
86
-
#define TSA_SICR_SCC_RXCS_BRG2 (0x1 << 3)
87
-
#define TSA_SICR_SCC_RXCS_BRG3 (0x2 << 3)
88
-
#define TSA_SICR_SCC_RXCS_BRG4 (0x3 << 3)
89
-
#define TSA_SICR_SCC_RXCS_CLK15 (0x4 << 3)
90
-
#define TSA_SICR_SCC_RXCS_CLK26 (0x5 << 3)
91
-
#define TSA_SICR_SCC_RXCS_CLK37 (0x6 << 3)
92
-
#define TSA_SICR_SCC_RXCS_CLK48 (0x7 << 3)
93
-
#define TSA_SICR_SCC_TXCS_MASK (0x7 << 0)
94
-
#define TSA_SICR_SCC_TXCS_BRG1 (0x0 << 0)
95
-
#define TSA_SICR_SCC_TXCS_BRG2 (0x1 << 0)
96
-
#define TSA_SICR_SCC_TXCS_BRG3 (0x2 << 0)
97
-
#define TSA_SICR_SCC_TXCS_BRG4 (0x3 << 0)
98
-
#define TSA_SICR_SCC_TXCS_CLK15 (0x4 << 0)
99
-
#define TSA_SICR_SCC_TXCS_CLK26 (0x5 << 0)
100
-
#define TSA_SICR_SCC_TXCS_CLK37 (0x6 << 0)
101
-
#define TSA_SICR_SCC_TXCS_CLK48 (0x7 << 0)
72
+
#define TSA_SICR_SCC2_MASK GENMASK(15, 8)
73
+
#define TSA_SICR_SCC2(x) FIELD_PREP(TSA_SICR_SCC2_MASK, x)
74
+
#define TSA_SICR_SCC3_MASK GENMASK(23, 16)
75
+
#define TSA_SICR_SCC3(x) FIELD_PREP(TSA_SICR_SCC3_MASK, x)
76
+
#define TSA_SICR_SCC4_MASK GENMASK(31, 24)
77
+
#define TSA_SICR_SCC4(x) FIELD_PREP(TSA_SICR_SCC4_MASK, x)
78
+
#define TSA_SICR_SCC_MASK GENMASK(7, 0)
79
+
#define TSA_SICR_SCC_GRX BIT(7)
80
+
#define TSA_SICR_SCC_SCX_TSA BIT(6)
81
+
#define TSA_SICR_SCC_RXCS_MASK GENMASK(5, 3)
82
+
#define TSA_SICR_SCC_RXCS_BRG1 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x0)
83
+
#define TSA_SICR_SCC_RXCS_BRG2 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x1)
84
+
#define TSA_SICR_SCC_RXCS_BRG3 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x2)
85
+
#define TSA_SICR_SCC_RXCS_BRG4 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x3)
86
+
#define TSA_SICR_SCC_RXCS_CLK15 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x4)
87
+
#define TSA_SICR_SCC_RXCS_CLK26 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x5)
88
+
#define TSA_SICR_SCC_RXCS_CLK37 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x6)
89
+
#define TSA_SICR_SCC_RXCS_CLK48 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x7)
90
+
#define TSA_SICR_SCC_TXCS_MASK GENMASK(2, 0)
91
+
#define TSA_SICR_SCC_TXCS_BRG1 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x0)
92
+
#define TSA_SICR_SCC_TXCS_BRG2 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x1)
93
+
#define TSA_SICR_SCC_TXCS_BRG3 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x2)
94
+
#define TSA_SICR_SCC_TXCS_BRG4 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x3)
95
+
#define TSA_SICR_SCC_TXCS_CLK15 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x4)
96
+
#define TSA_SICR_SCC_TXCS_CLK26 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x5)
97
+
#define TSA_SICR_SCC_TXCS_CLK37 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x6)
98
+
#define TSA_SICR_SCC_TXCS_CLK48 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x7)
102
99
103
100
/* Serial interface RAM pointer register (32 bits) */
104
101
#define TSA_SIRP 0x10