tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'qcom-drivers-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for 6.1
The icc-bwmon driver is expected to support measuring LLCC/DDR bandwidth
on SDM845 and SC7280.
The LLCC driver is extended to provide per-platform register mappings to
the LLCC EDAC driver. The QMI encoder/decoder is updated to allow the
passed qmi_elem_info to be const.
Support for SDM845 is added to the sleep stats driver. Power-domains for
the SM6375 platform is added to RPMPD and the platform is added to
socinfo, together with the PM6125 pmic id.
A couple of of_node reference issues are corrected in the smem state and
smsm drivers.
The Qualcomm SCM driver binding is converted to YAML.
* tag 'qcom-drivers-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (29 commits)
soc: qcom: rpmpd: Add SM6375 support
dt-bindings: power: rpmpd: Add SM6375 power domains
firmware: qcom: scm: remove unused __qcom_scm_init declaration
dt-bindings: power: qcom,rpmpd: drop non-working codeaurora.org emails
soc: qcom: icc-bwmon: force clear counter/irq registers
soc: qcom: icc-bwmon: add support for sc7280 LLCC BWMON
dt-bindings: interconnect: qcom,msm8998-bwmon: Add support for sc7280 BWMONs
soc: qcom: llcc: Pass LLCC version based register offsets to EDAC driver
soc: qcom: llcc: Rename reg_offset structs to reflect LLCC version
soc: qcom: qmi: use const for struct qmi_elem_info
soc: qcom: icc-bwmon: remove redundant ret variable
dt-bindings: soc: qcom: stats: Document SDM845 compatible
soc: qcom: stats: Add SDM845 stats config and compatible
dt-bindings: firmware: document Qualcomm SM6115 SCM
soc: qcom: Make QCOM_RPMPD depend on OF
dt-bindings: firmware: convert Qualcomm SCM binding to the yaml
soc: qcom: socinfo: Add PM6125 ID
soc: qcom: socinfo: Add an ID for SM6375
soc: qcom: smem_state: Add refcounting for the 'state->of_node'
soc: qcom: smsm: Fix refcount leak bugs in qcom_smsm_probe()
...
Link: https://lore.kernel.org/r/20220921155753.1316308-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+751
-226
-61
Documentation/devicetree/bindings/firmware/qcom,scm.txt
-61
Documentation/devicetree/bindings/firmware/qcom,scm.txt
···
1
-
QCOM Secure Channel Manager (SCM)
2
-
3
-
Qualcomm processors include an interface to communicate to the secure firmware.
4
-
This interface allows for clients to request different types of actions. These
5
-
can include CPU power up/down, HDCP requests, loading of firmware, and other
6
-
assorted actions.
7
-
8
-
Required properties:
9
-
- compatible: must contain one of the following:
10
-
* "qcom,scm-apq8064"
11
-
* "qcom,scm-apq8084"
12
-
* "qcom,scm-ipq4019"
13
-
* "qcom,scm-ipq806x"
14
-
* "qcom,scm-ipq8074"
15
-
* "qcom,scm-mdm9607"
16
-
* "qcom,scm-msm8226"
17
-
* "qcom,scm-msm8660"
18
-
* "qcom,scm-msm8916"
19
-
* "qcom,scm-msm8953"
20
-
* "qcom,scm-msm8960"
21
-
* "qcom,scm-msm8974"
22
-
* "qcom,scm-msm8976"
23
-
* "qcom,scm-msm8994"
24
-
* "qcom,scm-msm8996"
25
-
* "qcom,scm-msm8998"
26
-
* "qcom,scm-qcs404"
27
-
* "qcom,scm-sc7180"
28
-
* "qcom,scm-sc7280"
29
-
* "qcom,scm-sm6125"
30
-
* "qcom,scm-sdm845"
31
-
* "qcom,scm-sdx55"
32
-
* "qcom,scm-sdx65"
33
-
* "qcom,scm-sm6350"
34
-
* "qcom,scm-sm8150"
35
-
* "qcom,scm-sm8250"
36
-
* "qcom,scm-sm8350"
37
-
* "qcom,scm-sm8450"
38
-
and:
39
-
* "qcom,scm"
40
-
- clocks: Specifies clocks needed by the SCM interface, if any:
41
-
* core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
42
-
"qcom,scm-msm8960"
43
-
* core, iface and bus clocks required for "qcom,scm-apq8084",
44
-
"qcom,scm-msm8916", "qcom,scm-msm8953", "qcom,scm-msm8974" and "qcom,scm-msm8976"
45
-
- clock-names: Must contain "core" for the core clock, "iface" for the interface
46
-
clock and "bus" for the bus clock per the requirements of the compatible.
47
-
- qcom,dload-mode: phandle to the TCSR hardware block and offset of the
48
-
download mode control register (optional)
49
-
- interconnects: Specifies the bandwidth requirements of the SCM interface (optional)
50
-
51
-
Example for MSM8916:
52
-
53
-
firmware {
54
-
scm {
55
-
compatible = "qcom,msm8916", "qcom,scm";
56
-
clocks = <&gcc GCC_CRYPTO_CLK> ,
57
-
<&gcc GCC_CRYPTO_AXI_CLK>,
58
-
<&gcc GCC_CRYPTO_AHB_CLK>;
59
-
clock-names = "core", "bus", "iface";
60
-
};
61
-
};
+148
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+148
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/firmware/qcom,scm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: QCOM Secure Channel Manager (SCM)
8
+
9
+
description: |
10
+
Qualcomm processors include an interface to communicate to the secure firmware.
11
+
This interface allows for clients to request different types of actions.
12
+
These can include CPU power up/down, HDCP requests, loading of firmware,
13
+
and other assorted actions.
14
+
15
+
maintainers:
16
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
17
+
- Robert Marko <robimarko@gmail.com>
18
+
- Guru Das Srinagesh <quic_gurus@quicinc.com>
19
+
20
+
properties:
21
+
compatible:
22
+
items:
23
+
- enum:
24
+
- qcom,scm-apq8064
25
+
- qcom,scm-apq8084
26
+
- qcom,scm-ipq4019
27
+
- qcom,scm-ipq6018
28
+
- qcom,scm-ipq806x
29
+
- qcom,scm-ipq8074
30
+
- qcom,scm-mdm9607
31
+
- qcom,scm-msm8226
32
+
- qcom,scm-msm8660
33
+
- qcom,scm-msm8916
34
+
- qcom,scm-msm8953
35
+
- qcom,scm-msm8960
36
+
- qcom,scm-msm8974
37
+
- qcom,scm-msm8976
38
+
- qcom,scm-msm8994
39
+
- qcom,scm-msm8996
40
+
- qcom,scm-msm8998
41
+
- qcom,scm-sc7180
42
+
- qcom,scm-sc7280
43
+
- qcom,scm-sc8280xp
44
+
- qcom,scm-sdm845
45
+
- qcom,scm-sdx55
46
+
- qcom,scm-sdx65
47
+
- qcom,scm-sm6115
48
+
- qcom,scm-sm6125
49
+
- qcom,scm-sm6350
50
+
- qcom,scm-sm8150
51
+
- qcom,scm-sm8250
52
+
- qcom,scm-sm8350
53
+
- qcom,scm-sm8450
54
+
- qcom,scm-qcs404
55
+
- const: qcom,scm
56
+
57
+
clocks:
58
+
minItems: 1
59
+
maxItems: 3
60
+
61
+
clock-names:
62
+
minItems: 1
63
+
maxItems: 3
64
+
65
+
interconnects:
66
+
maxItems: 1
67
+
68
+
interconnect-names:
69
+
maxItems: 1
70
+
71
+
'#reset-cells':
72
+
const: 1
73
+
74
+
qcom,dload-mode:
75
+
$ref: /schemas/types.yaml#/definitions/phandle-array
76
+
items:
77
+
- items:
78
+
- description: phandle to TCSR hardware block
79
+
- description: offset of the download mode control register
80
+
description: TCSR hardware block
81
+
82
+
allOf:
83
+
- if:
84
+
properties:
85
+
compatible:
86
+
contains:
87
+
enum:
88
+
- qcom,scm-apq8064
89
+
- qcom,scm-msm8660
90
+
- qcom,scm-msm8960
91
+
then:
92
+
properties:
93
+
clock-names:
94
+
items:
95
+
- const: core
96
+
97
+
clocks:
98
+
maxItems: 1
99
+
100
+
required:
101
+
- clocks
102
+
- clock-names
103
+
104
+
- if:
105
+
properties:
106
+
compatible:
107
+
contains:
108
+
enum:
109
+
- qcom,scm-apq8084
110
+
- qcom,scm-mdm9607
111
+
- qcom,scm-msm8916
112
+
- qcom,scm-msm8953
113
+
- qcom,scm-msm8974
114
+
- qcom,scm-msm8976
115
+
then:
116
+
properties:
117
+
clock-names:
118
+
items:
119
+
- const: core
120
+
- const: bus
121
+
- const: iface
122
+
123
+
clocks:
124
+
minItems: 3
125
+
maxItems: 3
126
+
127
+
required:
128
+
- clocks
129
+
- clock-names
130
+
131
+
required:
132
+
- compatible
133
+
134
+
additionalProperties: false
135
+
136
+
examples:
137
+
- |
138
+
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
139
+
140
+
firmware {
141
+
scm {
142
+
compatible = "qcom,scm-msm8916", "qcom,scm";
143
+
clocks = <&gcc GCC_CRYPTO_CLK>,
144
+
<&gcc GCC_CRYPTO_AXI_CLK>,
145
+
<&gcc GCC_CRYPTO_AHB_CLK>;
146
+
clock-names = "core", "bus", "iface";
147
+
};
148
+
};
+3
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+3
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
···
24
24
oneOf:
25
25
- items:
26
26
- enum:
27
+
- qcom,sc7280-bwmon
27
28
- qcom,sdm845-bwmon
28
29
- const: qcom,msm8998-bwmon
29
30
- const: qcom,msm8998-bwmon # BWMON v4
31
+
- const: qcom,sc7280-llcc-bwmon # BWMON v5
32
+
- const: qcom,sdm845-llcc-bwmon # BWMON v5
30
33
31
34
interconnects:
32
35
maxItems: 1
+2
-1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+2
-1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
···
7
7
title: Qualcomm RPM/RPMh Power domains
8
8
9
9
maintainers:
10
-
- Rajendra Nayak <rnayak@codeaurora.org>
10
+
- Bjorn Andersson <andersson@kernel.org>
11
11
12
12
description:
13
13
For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
···
40
40
- qcom,sm6115-rpmpd
41
41
- qcom,sm6125-rpmpd
42
42
- qcom,sm6350-rpmhpd
43
+
- qcom,sm6375-rpmpd
43
44
- qcom,sm8150-rpmhpd
44
45
- qcom,sm8250-rpmhpd
45
46
- qcom,sm8350-rpmhpd
+1
Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml
+1
Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml
-2
drivers/firmware/qcom_scm.h
-2
drivers/firmware/qcom_scm.h
+1
-1
drivers/soc/qcom/Kconfig
+1
-1
drivers/soc/qcom/Kconfig
+379
-96
drivers/soc/qcom/icc-bwmon.c
+379
-96
drivers/soc/qcom/icc-bwmon.c
···
5
5
* Author: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, based on
6
6
* previous work of Thara Gopinath and msm-4.9 downstream sources.
7
7
*/
8
+
9
+
#include <linux/err.h>
8
10
#include <linux/interconnect.h>
9
11
#include <linux/interrupt.h>
10
12
#include <linux/io.h>
···
15
13
#include <linux/of_device.h>
16
14
#include <linux/platform_device.h>
17
15
#include <linux/pm_opp.h>
16
+
#include <linux/regmap.h>
18
17
#include <linux/sizes.h>
19
18
20
19
/*
···
34
31
/* Internal sampling clock frequency */
35
32
#define HW_TIMER_HZ 19200000
36
33
37
-
#define BWMON_GLOBAL_IRQ_STATUS 0x0
38
-
#define BWMON_GLOBAL_IRQ_CLEAR 0x8
39
-
#define BWMON_GLOBAL_IRQ_ENABLE 0xc
40
-
#define BWMON_GLOBAL_IRQ_ENABLE_ENABLE BIT(0)
34
+
#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x008
35
+
#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x00c
36
+
/*
37
+
* All values here and further are matching regmap fields, so without absolute
38
+
* register offsets.
39
+
*/
40
+
#define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0)
41
41
42
-
#define BWMON_IRQ_STATUS 0x100
43
-
#define BWMON_IRQ_STATUS_ZONE_SHIFT 4
44
-
#define BWMON_IRQ_CLEAR 0x108
45
-
#define BWMON_IRQ_ENABLE 0x10c
46
-
#define BWMON_IRQ_ENABLE_ZONE1_SHIFT 5
47
-
#define BWMON_IRQ_ENABLE_ZONE2_SHIFT 6
48
-
#define BWMON_IRQ_ENABLE_ZONE3_SHIFT 7
49
-
#define BWMON_IRQ_ENABLE_MASK (BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT) | \
50
-
BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT))
42
+
#define BWMON_V4_IRQ_STATUS 0x100
43
+
#define BWMON_V4_IRQ_CLEAR 0x108
51
44
52
-
#define BWMON_ENABLE 0x2a0
45
+
#define BWMON_V4_IRQ_ENABLE 0x10c
46
+
#define BWMON_IRQ_ENABLE_MASK (BIT(1) | BIT(3))
47
+
#define BWMON_V5_IRQ_STATUS 0x000
48
+
#define BWMON_V5_IRQ_CLEAR 0x008
49
+
#define BWMON_V5_IRQ_ENABLE 0x00c
50
+
51
+
#define BWMON_V4_ENABLE 0x2a0
52
+
#define BWMON_V5_ENABLE 0x010
53
53
#define BWMON_ENABLE_ENABLE BIT(0)
54
54
55
-
#define BWMON_CLEAR 0x2a4
55
+
#define BWMON_V4_CLEAR 0x2a4
56
+
#define BWMON_V5_CLEAR 0x014
56
57
#define BWMON_CLEAR_CLEAR BIT(0)
58
+
#define BWMON_CLEAR_CLEAR_ALL BIT(1)
57
59
58
-
#define BWMON_SAMPLE_WINDOW 0x2a8
59
-
#define BWMON_THRESHOLD_HIGH 0x2ac
60
-
#define BWMON_THRESHOLD_MED 0x2b0
61
-
#define BWMON_THRESHOLD_LOW 0x2b4
60
+
#define BWMON_V4_SAMPLE_WINDOW 0x2a8
61
+
#define BWMON_V5_SAMPLE_WINDOW 0x020
62
62
63
-
#define BWMON_ZONE_ACTIONS 0x2b8
63
+
#define BWMON_V4_THRESHOLD_HIGH 0x2ac
64
+
#define BWMON_V4_THRESHOLD_MED 0x2b0
65
+
#define BWMON_V4_THRESHOLD_LOW 0x2b4
66
+
#define BWMON_V5_THRESHOLD_HIGH 0x024
67
+
#define BWMON_V5_THRESHOLD_MED 0x028
68
+
#define BWMON_V5_THRESHOLD_LOW 0x02c
69
+
70
+
#define BWMON_V4_ZONE_ACTIONS 0x2b8
71
+
#define BWMON_V5_ZONE_ACTIONS 0x030
64
72
/*
65
73
* Actions to perform on some zone 'z' when current zone hits the threshold:
66
74
* Increment counter of zone 'z'
···
97
83
BWMON_ZONE_ACTIONS_CLEAR(2) | \
98
84
BWMON_ZONE_ACTIONS_CLEAR(1) | \
99
85
BWMON_ZONE_ACTIONS_CLEAR(0))
100
-
/* Value for BWMON_ZONE_ACTIONS */
101
-
#define BWMON_ZONE_ACTIONS_DEFAULT (BWMON_ZONE_ACTIONS_ZONE0 | \
102
-
BWMON_ZONE_ACTIONS_ZONE1 << 8 | \
103
-
BWMON_ZONE_ACTIONS_ZONE2 << 16 | \
104
-
BWMON_ZONE_ACTIONS_ZONE3 << 24)
105
86
106
87
/*
107
-
* There is no clear documentation/explanation of BWMON_THRESHOLD_COUNT
88
+
* There is no clear documentation/explanation of BWMON_V4_THRESHOLD_COUNT
108
89
* register. Based on observations, this is number of times one threshold has to
109
90
* be reached, to trigger interrupt in given zone.
110
91
*
111
92
* 0xff are maximum values meant to ignore the zones 0 and 2.
112
93
*/
113
-
#define BWMON_THRESHOLD_COUNT 0x2bc
114
-
#define BWMON_THRESHOLD_COUNT_ZONE1_SHIFT 8
115
-
#define BWMON_THRESHOLD_COUNT_ZONE2_SHIFT 16
116
-
#define BWMON_THRESHOLD_COUNT_ZONE3_SHIFT 24
94
+
#define BWMON_V4_THRESHOLD_COUNT 0x2bc
95
+
#define BWMON_V5_THRESHOLD_COUNT 0x034
117
96
#define BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT 0xff
118
97
#define BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT 0xff
119
98
120
-
/* BWMONv4 count registers use count unit of 64 kB */
121
-
#define BWMON_COUNT_UNIT_KB 64
122
-
#define BWMON_ZONE_COUNT 0x2d8
123
-
#define BWMON_ZONE_MAX(zone) (0x2e0 + 4 * (zone))
99
+
#define BWMON_V4_ZONE_MAX(zone) (0x2e0 + 4 * (zone))
100
+
#define BWMON_V5_ZONE_MAX(zone) (0x044 + 4 * (zone))
101
+
102
+
/* Quirks for specific BWMON types */
103
+
#define BWMON_HAS_GLOBAL_IRQ BIT(0)
104
+
#define BWMON_NEEDS_FORCE_CLEAR BIT(1)
105
+
106
+
enum bwmon_fields {
107
+
F_GLOBAL_IRQ_CLEAR,
108
+
F_GLOBAL_IRQ_ENABLE,
109
+
F_IRQ_STATUS,
110
+
F_IRQ_CLEAR,
111
+
F_IRQ_ENABLE,
112
+
F_ENABLE,
113
+
F_CLEAR,
114
+
F_SAMPLE_WINDOW,
115
+
F_THRESHOLD_HIGH,
116
+
F_THRESHOLD_MED,
117
+
F_THRESHOLD_LOW,
118
+
F_ZONE_ACTIONS_ZONE0,
119
+
F_ZONE_ACTIONS_ZONE1,
120
+
F_ZONE_ACTIONS_ZONE2,
121
+
F_ZONE_ACTIONS_ZONE3,
122
+
F_THRESHOLD_COUNT_ZONE0,
123
+
F_THRESHOLD_COUNT_ZONE1,
124
+
F_THRESHOLD_COUNT_ZONE2,
125
+
F_THRESHOLD_COUNT_ZONE3,
126
+
F_ZONE0_MAX,
127
+
F_ZONE1_MAX,
128
+
F_ZONE2_MAX,
129
+
F_ZONE3_MAX,
130
+
131
+
F_NUM_FIELDS
132
+
};
124
133
125
134
struct icc_bwmon_data {
126
135
unsigned int sample_ms;
136
+
unsigned int count_unit_kb; /* kbytes */
127
137
unsigned int default_highbw_kbps;
128
138
unsigned int default_medbw_kbps;
129
139
unsigned int default_lowbw_kbps;
130
140
u8 zone1_thres_count;
131
141
u8 zone3_thres_count;
142
+
unsigned int quirks;
143
+
144
+
const struct regmap_config *regmap_cfg;
145
+
const struct reg_field *regmap_fields;
132
146
};
133
147
134
148
struct icc_bwmon {
135
149
struct device *dev;
136
-
void __iomem *base;
150
+
const struct icc_bwmon_data *data;
137
151
int irq;
138
152
139
-
unsigned int default_lowbw_kbps;
140
-
unsigned int sample_ms;
153
+
struct regmap *regmap;
154
+
struct regmap_field *regs[F_NUM_FIELDS];
155
+
141
156
unsigned int max_bw_kbps;
142
157
unsigned int min_bw_kbps;
143
158
unsigned int target_kbps;
144
159
unsigned int current_kbps;
145
160
};
146
161
147
-
static void bwmon_clear_counters(struct icc_bwmon *bwmon)
162
+
/* BWMON v4 */
163
+
static const struct reg_field msm8998_bwmon_reg_fields[] = {
164
+
[F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0),
165
+
[F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0),
166
+
[F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7),
167
+
[F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7),
168
+
[F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7),
169
+
/* F_ENABLE covers entire register to disable other features */
170
+
[F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31),
171
+
[F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1),
172
+
[F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23),
173
+
[F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11),
174
+
[F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11),
175
+
[F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11),
176
+
[F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7),
177
+
[F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15),
178
+
[F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23),
179
+
[F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31),
180
+
[F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7),
181
+
[F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15),
182
+
[F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23),
183
+
[F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31),
184
+
[F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11),
185
+
[F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11),
186
+
[F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11),
187
+
[F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11),
188
+
};
189
+
190
+
static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] = {
191
+
regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR),
192
+
regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR),
193
+
regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR),
194
+
};
195
+
196
+
static const struct regmap_access_table msm8998_bwmon_reg_read_table = {
197
+
.no_ranges = msm8998_bwmon_reg_noread_ranges,
198
+
.n_no_ranges = ARRAY_SIZE(msm8998_bwmon_reg_noread_ranges),
199
+
};
200
+
201
+
static const struct regmap_range msm8998_bwmon_reg_volatile_ranges[] = {
202
+
regmap_reg_range(BWMON_V4_IRQ_STATUS, BWMON_V4_IRQ_STATUS),
203
+
regmap_reg_range(BWMON_V4_ZONE_MAX(0), BWMON_V4_ZONE_MAX(3)),
204
+
};
205
+
206
+
static const struct regmap_access_table msm8998_bwmon_reg_volatile_table = {
207
+
.yes_ranges = msm8998_bwmon_reg_volatile_ranges,
208
+
.n_yes_ranges = ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges),
209
+
};
210
+
211
+
/*
212
+
* Fill the cache for non-readable registers only as rest does not really
213
+
* matter and can be read from the device.
214
+
*/
215
+
static const struct reg_default msm8998_bwmon_reg_defaults[] = {
216
+
{ BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 },
217
+
{ BWMON_V4_IRQ_CLEAR, 0x0 },
218
+
{ BWMON_V4_CLEAR, 0x0 },
219
+
};
220
+
221
+
static const struct regmap_config msm8998_bwmon_regmap_cfg = {
222
+
.reg_bits = 32,
223
+
.reg_stride = 4,
224
+
.val_bits = 32,
225
+
/*
226
+
* No concurrent access expected - driver has one interrupt handler,
227
+
* regmap is not shared, no driver or user-space API.
228
+
*/
229
+
.disable_locking = true,
230
+
.rd_table = &msm8998_bwmon_reg_read_table,
231
+
.volatile_table = &msm8998_bwmon_reg_volatile_table,
232
+
.reg_defaults = msm8998_bwmon_reg_defaults,
233
+
.num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_reg_defaults),
234
+
/*
235
+
* Cache is necessary for using regmap fields with non-readable
236
+
* registers.
237
+
*/
238
+
.cache_type = REGCACHE_RBTREE,
239
+
};
240
+
241
+
/* BWMON v5 */
242
+
static const struct reg_field sdm845_llcc_bwmon_reg_fields[] = {
243
+
[F_GLOBAL_IRQ_CLEAR] = {},
244
+
[F_GLOBAL_IRQ_ENABLE] = {},
245
+
[F_IRQ_STATUS] = REG_FIELD(BWMON_V5_IRQ_STATUS, 0, 3),
246
+
[F_IRQ_CLEAR] = REG_FIELD(BWMON_V5_IRQ_CLEAR, 0, 3),
247
+
[F_IRQ_ENABLE] = REG_FIELD(BWMON_V5_IRQ_ENABLE, 0, 3),
248
+
/* F_ENABLE covers entire register to disable other features */
249
+
[F_ENABLE] = REG_FIELD(BWMON_V5_ENABLE, 0, 31),
250
+
[F_CLEAR] = REG_FIELD(BWMON_V5_CLEAR, 0, 1),
251
+
[F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V5_SAMPLE_WINDOW, 0, 19),
252
+
[F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V5_THRESHOLD_HIGH, 0, 11),
253
+
[F_THRESHOLD_MED] = REG_FIELD(BWMON_V5_THRESHOLD_MED, 0, 11),
254
+
[F_THRESHOLD_LOW] = REG_FIELD(BWMON_V5_THRESHOLD_LOW, 0, 11),
255
+
[F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 0, 7),
256
+
[F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 8, 15),
257
+
[F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 16, 23),
258
+
[F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 24, 31),
259
+
[F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 0, 7),
260
+
[F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 8, 15),
261
+
[F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 16, 23),
262
+
[F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 24, 31),
263
+
[F_ZONE0_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(0), 0, 11),
264
+
[F_ZONE1_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(1), 0, 11),
265
+
[F_ZONE2_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(2), 0, 11),
266
+
[F_ZONE3_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(3), 0, 11),
267
+
};
268
+
269
+
static const struct regmap_range sdm845_llcc_bwmon_reg_noread_ranges[] = {
270
+
regmap_reg_range(BWMON_V5_IRQ_CLEAR, BWMON_V5_IRQ_CLEAR),
271
+
regmap_reg_range(BWMON_V5_CLEAR, BWMON_V5_CLEAR),
272
+
};
273
+
274
+
static const struct regmap_access_table sdm845_llcc_bwmon_reg_read_table = {
275
+
.no_ranges = sdm845_llcc_bwmon_reg_noread_ranges,
276
+
.n_no_ranges = ARRAY_SIZE(sdm845_llcc_bwmon_reg_noread_ranges),
277
+
};
278
+
279
+
static const struct regmap_range sdm845_llcc_bwmon_reg_volatile_ranges[] = {
280
+
regmap_reg_range(BWMON_V5_IRQ_STATUS, BWMON_V5_IRQ_STATUS),
281
+
regmap_reg_range(BWMON_V5_ZONE_MAX(0), BWMON_V5_ZONE_MAX(3)),
282
+
};
283
+
284
+
static const struct regmap_access_table sdm845_llcc_bwmon_reg_volatile_table = {
285
+
.yes_ranges = sdm845_llcc_bwmon_reg_volatile_ranges,
286
+
.n_yes_ranges = ARRAY_SIZE(sdm845_llcc_bwmon_reg_volatile_ranges),
287
+
};
288
+
289
+
/*
290
+
* Fill the cache for non-readable registers only as rest does not really
291
+
* matter and can be read from the device.
292
+
*/
293
+
static const struct reg_default sdm845_llcc_bwmon_reg_defaults[] = {
294
+
{ BWMON_V5_IRQ_CLEAR, 0x0 },
295
+
{ BWMON_V5_CLEAR, 0x0 },
296
+
};
297
+
298
+
static const struct regmap_config sdm845_llcc_bwmon_regmap_cfg = {
299
+
.reg_bits = 32,
300
+
.reg_stride = 4,
301
+
.val_bits = 32,
302
+
/*
303
+
* No concurrent access expected - driver has one interrupt handler,
304
+
* regmap is not shared, no driver or user-space API.
305
+
*/
306
+
.disable_locking = true,
307
+
.rd_table = &sdm845_llcc_bwmon_reg_read_table,
308
+
.volatile_table = &sdm845_llcc_bwmon_reg_volatile_table,
309
+
.reg_defaults = sdm845_llcc_bwmon_reg_defaults,
310
+
.num_reg_defaults = ARRAY_SIZE(sdm845_llcc_bwmon_reg_defaults),
311
+
/*
312
+
* Cache is necessary for using regmap fields with non-readable
313
+
* registers.
314
+
*/
315
+
.cache_type = REGCACHE_RBTREE,
316
+
};
317
+
318
+
static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all)
148
319
{
320
+
unsigned int val = BWMON_CLEAR_CLEAR;
321
+
322
+
if (clear_all)
323
+
val |= BWMON_CLEAR_CLEAR_ALL;
149
324
/*
150
325
* Clear counters. The order and barriers are
151
326
* important. Quoting downstream Qualcomm msm-4.9 tree:
···
343
140
* region. So, we need to make sure the counter clear is completed
344
141
* before we try to clear the IRQ or do any other counter operations.
345
142
*/
346
-
writel(BWMON_CLEAR_CLEAR, bwmon->base + BWMON_CLEAR);
143
+
regmap_field_force_write(bwmon->regs[F_CLEAR], val);
144
+
if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR)
145
+
regmap_field_force_write(bwmon->regs[F_CLEAR], 0);
347
146
}
348
147
349
148
static void bwmon_clear_irq(struct icc_bwmon *bwmon)
···
366
161
* clearing here so that local writes don't happen before the
367
162
* interrupt is cleared.
368
163
*/
369
-
writel(BWMON_IRQ_ENABLE_MASK, bwmon->base + BWMON_IRQ_CLEAR);
370
-
writel(BIT(0), bwmon->base + BWMON_GLOBAL_IRQ_CLEAR);
164
+
regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], BWMON_IRQ_ENABLE_MASK);
165
+
if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR)
166
+
regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0);
167
+
if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ)
168
+
regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR],
169
+
BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE);
371
170
}
372
171
373
172
static void bwmon_disable(struct icc_bwmon *bwmon)
374
173
{
375
174
/* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */
376
-
writel(0x0, bwmon->base + BWMON_GLOBAL_IRQ_ENABLE);
377
-
writel(0x0, bwmon->base + BWMON_IRQ_ENABLE);
175
+
if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ)
176
+
regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0);
177
+
regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0);
378
178
379
179
/*
380
180
* Disable bwmon. Must happen before bwmon_clear_irq() to avoid spurious
381
181
* IRQ.
382
182
*/
383
-
writel(0x0, bwmon->base + BWMON_ENABLE);
183
+
regmap_field_write(bwmon->regs[F_ENABLE], 0x0);
384
184
}
385
185
386
186
static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable)
387
187
{
388
188
/* Enable interrupts */
389
-
writel(BWMON_GLOBAL_IRQ_ENABLE_ENABLE,
390
-
bwmon->base + BWMON_GLOBAL_IRQ_ENABLE);
391
-
writel(irq_enable, bwmon->base + BWMON_IRQ_ENABLE);
189
+
if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ)
190
+
regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE],
191
+
BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE);
192
+
regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable);
392
193
393
194
/* Enable bwmon */
394
-
writel(BWMON_ENABLE_ENABLE, bwmon->base + BWMON_ENABLE);
195
+
regmap_field_write(bwmon->regs[F_ENABLE], BWMON_ENABLE_ENABLE);
395
196
}
396
197
397
-
static unsigned int bwmon_kbps_to_count(unsigned int kbps)
198
+
static unsigned int bwmon_kbps_to_count(struct icc_bwmon *bwmon,
199
+
unsigned int kbps)
398
200
{
399
-
return kbps / BWMON_COUNT_UNIT_KB;
201
+
return kbps / bwmon->data->count_unit_kb;
400
202
}
401
203
402
-
static void bwmon_set_threshold(struct icc_bwmon *bwmon, unsigned int reg,
403
-
unsigned int kbps)
204
+
static void bwmon_set_threshold(struct icc_bwmon *bwmon,
205
+
struct regmap_field *reg, unsigned int kbps)
404
206
{
405
207
unsigned int thres;
406
208
407
-
thres = mult_frac(bwmon_kbps_to_count(kbps), bwmon->sample_ms,
408
-
MSEC_PER_SEC);
409
-
writel_relaxed(thres, bwmon->base + reg);
209
+
thres = mult_frac(bwmon_kbps_to_count(bwmon, kbps),
210
+
bwmon->data->sample_ms, MSEC_PER_SEC);
211
+
regmap_field_write(reg, thres);
410
212
}
411
213
412
-
static void bwmon_start(struct icc_bwmon *bwmon,
413
-
const struct icc_bwmon_data *data)
214
+
static void bwmon_start(struct icc_bwmon *bwmon)
414
215
{
415
-
unsigned int thres_count;
216
+
const struct icc_bwmon_data *data = bwmon->data;
416
217
int window;
417
218
418
-
bwmon_clear_counters(bwmon);
219
+
bwmon_clear_counters(bwmon, true);
419
220
420
-
window = mult_frac(bwmon->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC);
421
-
/* Maximum sampling window: 0xfffff */
422
-
writel_relaxed(window, bwmon->base + BWMON_SAMPLE_WINDOW);
221
+
window = mult_frac(bwmon->data->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC);
222
+
/* Maximum sampling window: 0xffffff for v4 and 0xfffff for v5 */
223
+
regmap_field_write(bwmon->regs[F_SAMPLE_WINDOW], window);
423
224
424
-
bwmon_set_threshold(bwmon, BWMON_THRESHOLD_HIGH,
225
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH],
425
226
data->default_highbw_kbps);
426
-
bwmon_set_threshold(bwmon, BWMON_THRESHOLD_MED,
227
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED],
427
228
data->default_medbw_kbps);
428
-
bwmon_set_threshold(bwmon, BWMON_THRESHOLD_LOW,
229
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW],
429
230
data->default_lowbw_kbps);
430
231
431
-
thres_count = data->zone3_thres_count << BWMON_THRESHOLD_COUNT_ZONE3_SHIFT |
432
-
BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT << BWMON_THRESHOLD_COUNT_ZONE2_SHIFT |
433
-
data->zone1_thres_count << BWMON_THRESHOLD_COUNT_ZONE1_SHIFT |
434
-
BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT;
435
-
writel_relaxed(thres_count, bwmon->base + BWMON_THRESHOLD_COUNT);
436
-
writel_relaxed(BWMON_ZONE_ACTIONS_DEFAULT,
437
-
bwmon->base + BWMON_ZONE_ACTIONS);
438
-
/* Write barriers in bwmon_clear_irq() */
232
+
regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE0],
233
+
BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT);
234
+
regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE1],
235
+
data->zone1_thres_count);
236
+
regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE2],
237
+
BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT);
238
+
regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE3],
239
+
data->zone3_thres_count);
240
+
241
+
regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE0],
242
+
BWMON_ZONE_ACTIONS_ZONE0);
243
+
regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE1],
244
+
BWMON_ZONE_ACTIONS_ZONE1);
245
+
regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE2],
246
+
BWMON_ZONE_ACTIONS_ZONE2);
247
+
regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE3],
248
+
BWMON_ZONE_ACTIONS_ZONE3);
439
249
440
250
bwmon_clear_irq(bwmon);
441
251
bwmon_enable(bwmon, BWMON_IRQ_ENABLE_MASK);
···
462
242
unsigned int status, max;
463
243
int zone;
464
244
465
-
status = readl(bwmon->base + BWMON_IRQ_STATUS);
245
+
if (regmap_field_read(bwmon->regs[F_IRQ_STATUS], &status))
246
+
return IRQ_NONE;
247
+
466
248
status &= BWMON_IRQ_ENABLE_MASK;
467
249
if (!status) {
468
250
/*
···
481
259
482
260
bwmon_disable(bwmon);
483
261
484
-
zone = get_bitmask_order(status >> BWMON_IRQ_STATUS_ZONE_SHIFT) - 1;
262
+
zone = get_bitmask_order(status) - 1;
485
263
/*
486
264
* Zone max bytes count register returns count units within sampling
487
265
* window. Downstream kernel for BWMONv4 (called BWMON type 2 in
488
266
* downstream) always increments the max bytes count by one.
489
267
*/
490
-
max = readl(bwmon->base + BWMON_ZONE_MAX(zone)) + 1;
491
-
max *= BWMON_COUNT_UNIT_KB;
492
-
bwmon->target_kbps = mult_frac(max, MSEC_PER_SEC, bwmon->sample_ms);
268
+
if (regmap_field_read(bwmon->regs[F_ZONE0_MAX + zone], &max))
269
+
return IRQ_NONE;
270
+
271
+
max += 1;
272
+
max *= bwmon->data->count_unit_kb;
273
+
bwmon->target_kbps = mult_frac(max, MSEC_PER_SEC, bwmon->data->sample_ms);
493
274
494
275
return IRQ_WAKE_THREAD;
495
276
}
···
522
297
up_kbps = bwmon->target_kbps + 1;
523
298
524
299
if (bwmon->target_kbps >= bwmon->max_bw_kbps)
525
-
irq_enable = BIT(BWMON_IRQ_ENABLE_ZONE1_SHIFT);
300
+
irq_enable = BIT(1);
526
301
else if (bwmon->target_kbps <= bwmon->min_bw_kbps)
527
-
irq_enable = BIT(BWMON_IRQ_ENABLE_ZONE3_SHIFT);
302
+
irq_enable = BIT(3);
528
303
else
529
304
irq_enable = BWMON_IRQ_ENABLE_MASK;
530
305
531
-
bwmon_set_threshold(bwmon, BWMON_THRESHOLD_HIGH, up_kbps);
532
-
bwmon_set_threshold(bwmon, BWMON_THRESHOLD_MED, down_kbps);
533
-
/* Write barriers in bwmon_clear_counters() */
534
-
bwmon_clear_counters(bwmon);
306
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH],
307
+
up_kbps);
308
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED],
309
+
down_kbps);
310
+
bwmon_clear_counters(bwmon, false);
535
311
bwmon_clear_irq(bwmon);
536
312
bwmon_enable(bwmon, irq_enable);
537
313
···
550
324
return IRQ_HANDLED;
551
325
}
552
326
327
+
static int bwmon_init_regmap(struct platform_device *pdev,
328
+
struct icc_bwmon *bwmon)
329
+
{
330
+
struct device *dev = &pdev->dev;
331
+
void __iomem *base;
332
+
struct regmap *map;
333
+
334
+
base = devm_platform_ioremap_resource(pdev, 0);
335
+
if (IS_ERR(base))
336
+
return dev_err_probe(dev, PTR_ERR(base),
337
+
"failed to map bwmon registers\n");
338
+
339
+
map = devm_regmap_init_mmio(dev, base, bwmon->data->regmap_cfg);
340
+
if (IS_ERR(map))
341
+
return dev_err_probe(dev, PTR_ERR(map),
342
+
"failed to initialize regmap\n");
343
+
344
+
BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) != F_NUM_FIELDS);
345
+
BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) != F_NUM_FIELDS);
346
+
347
+
return devm_regmap_field_bulk_alloc(dev, map, bwmon->regs,
348
+
bwmon->data->regmap_fields,
349
+
F_NUM_FIELDS);
350
+
}
351
+
553
352
static int bwmon_probe(struct platform_device *pdev)
554
353
{
555
354
struct device *dev = &pdev->dev;
556
355
struct dev_pm_opp *opp;
557
356
struct icc_bwmon *bwmon;
558
-
const struct icc_bwmon_data *data;
559
357
int ret;
560
358
561
359
bwmon = devm_kzalloc(dev, sizeof(*bwmon), GFP_KERNEL);
562
360
if (!bwmon)
563
361
return -ENOMEM;
564
362
565
-
data = of_device_get_match_data(dev);
363
+
bwmon->data = of_device_get_match_data(dev);
566
364
567
-
bwmon->base = devm_platform_ioremap_resource(pdev, 0);
568
-
if (IS_ERR(bwmon->base)) {
569
-
dev_err(dev, "failed to map bwmon registers\n");
570
-
return PTR_ERR(bwmon->base);
571
-
}
365
+
ret = bwmon_init_regmap(pdev, bwmon);
366
+
if (ret)
367
+
return ret;
572
368
573
369
bwmon->irq = platform_get_irq(pdev, 0);
574
370
if (bwmon->irq < 0)
···
610
362
if (IS_ERR(opp))
611
363
return dev_err_probe(dev, ret, "failed to find min peak bandwidth\n");
612
364
613
-
bwmon->sample_ms = data->sample_ms;
614
-
bwmon->default_lowbw_kbps = data->default_lowbw_kbps;
615
365
bwmon->dev = dev;
616
366
617
367
bwmon_disable(bwmon);
···
620
374
return dev_err_probe(dev, ret, "failed to request IRQ\n");
621
375
622
376
platform_set_drvdata(pdev, bwmon);
623
-
bwmon_start(bwmon, data);
377
+
bwmon_start(bwmon);
624
378
625
379
return 0;
626
380
}
···
634
388
return 0;
635
389
}
636
390
637
-
/* BWMON v4 */
638
391
static const struct icc_bwmon_data msm8998_bwmon_data = {
639
392
.sample_ms = 4,
393
+
.count_unit_kb = 64,
640
394
.default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */
641
395
.default_medbw_kbps = 512 * 1024, /* 512 MBps */
642
396
.default_lowbw_kbps = 0,
643
397
.zone1_thres_count = 16,
644
398
.zone3_thres_count = 1,
399
+
.quirks = BWMON_HAS_GLOBAL_IRQ,
400
+
.regmap_fields = msm8998_bwmon_reg_fields,
401
+
.regmap_cfg = &msm8998_bwmon_regmap_cfg,
402
+
};
403
+
404
+
static const struct icc_bwmon_data sdm845_llcc_bwmon_data = {
405
+
.sample_ms = 4,
406
+
.count_unit_kb = 1024,
407
+
.default_highbw_kbps = 800 * 1024, /* 800 MBps */
408
+
.default_medbw_kbps = 256 * 1024, /* 256 MBps */
409
+
.default_lowbw_kbps = 0,
410
+
.zone1_thres_count = 16,
411
+
.zone3_thres_count = 1,
412
+
.regmap_fields = sdm845_llcc_bwmon_reg_fields,
413
+
.regmap_cfg = &sdm845_llcc_bwmon_regmap_cfg,
414
+
};
415
+
416
+
static const struct icc_bwmon_data sc7280_llcc_bwmon_data = {
417
+
.sample_ms = 4,
418
+
.count_unit_kb = 64,
419
+
.default_highbw_kbps = 800 * 1024, /* 800 MBps */
420
+
.default_medbw_kbps = 256 * 1024, /* 256 MBps */
421
+
.default_lowbw_kbps = 0,
422
+
.zone1_thres_count = 16,
423
+
.zone3_thres_count = 1,
424
+
.quirks = BWMON_NEEDS_FORCE_CLEAR,
425
+
.regmap_fields = sdm845_llcc_bwmon_reg_fields,
426
+
.regmap_cfg = &sdm845_llcc_bwmon_regmap_cfg,
645
427
};
646
428
647
429
static const struct of_device_id bwmon_of_match[] = {
648
-
{ .compatible = "qcom,msm8998-bwmon", .data = &msm8998_bwmon_data },
430
+
{
431
+
.compatible = "qcom,msm8998-bwmon",
432
+
.data = &msm8998_bwmon_data
433
+
}, {
434
+
.compatible = "qcom,sdm845-llcc-bwmon",
435
+
.data = &sdm845_llcc_bwmon_data
436
+
}, {
437
+
.compatible = "qcom,sc7280-llcc-bwmon",
438
+
.data = &sc7280_llcc_bwmon_data
439
+
},
649
440
{}
650
441
};
651
442
MODULE_DEVICE_TABLE(of, bwmon_of_match);
+80
-12
drivers/soc/qcom/llcc-qcom.c
+80
-12
drivers/soc/qcom/llcc-qcom.c
···
104
104
int size;
105
105
bool need_llcc_cfg;
106
106
const u32 *reg_offset;
107
+
const struct llcc_edac_reg_offset *edac_reg_offset;
107
108
};
108
109
109
110
enum llcc_reg_offset {
···
297
296
{LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 },
298
297
};
299
298
300
-
static const u32 llcc_v1_2_reg_offset[] = {
299
+
static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
300
+
.trp_ecc_error_status0 = 0x20344,
301
+
.trp_ecc_error_status1 = 0x20348,
302
+
.trp_ecc_sb_err_syn0 = 0x2304c,
303
+
.trp_ecc_db_err_syn0 = 0x20370,
304
+
.trp_ecc_error_cntr_clear = 0x20440,
305
+
.trp_interrupt_0_status = 0x20480,
306
+
.trp_interrupt_0_clear = 0x20484,
307
+
.trp_interrupt_0_enable = 0x20488,
308
+
309
+
/* LLCC Common registers */
310
+
.cmn_status0 = 0x3000c,
311
+
.cmn_interrupt_0_enable = 0x3001c,
312
+
.cmn_interrupt_2_enable = 0x3003c,
313
+
314
+
/* LLCC DRP registers */
315
+
.drp_ecc_error_cfg = 0x40000,
316
+
.drp_ecc_error_cntr_clear = 0x40004,
317
+
.drp_interrupt_status = 0x41000,
318
+
.drp_interrupt_clear = 0x41008,
319
+
.drp_interrupt_enable = 0x4100c,
320
+
.drp_ecc_error_status0 = 0x42044,
321
+
.drp_ecc_error_status1 = 0x42048,
322
+
.drp_ecc_sb_err_syn0 = 0x4204c,
323
+
.drp_ecc_db_err_syn0 = 0x42070,
324
+
};
325
+
326
+
static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
327
+
.trp_ecc_error_status0 = 0x20344,
328
+
.trp_ecc_error_status1 = 0x20348,
329
+
.trp_ecc_sb_err_syn0 = 0x2034c,
330
+
.trp_ecc_db_err_syn0 = 0x20370,
331
+
.trp_ecc_error_cntr_clear = 0x20440,
332
+
.trp_interrupt_0_status = 0x20480,
333
+
.trp_interrupt_0_clear = 0x20484,
334
+
.trp_interrupt_0_enable = 0x20488,
335
+
336
+
/* LLCC Common registers */
337
+
.cmn_status0 = 0x3400c,
338
+
.cmn_interrupt_0_enable = 0x3401c,
339
+
.cmn_interrupt_2_enable = 0x3403c,
340
+
341
+
/* LLCC DRP registers */
342
+
.drp_ecc_error_cfg = 0x50000,
343
+
.drp_ecc_error_cntr_clear = 0x50004,
344
+
.drp_interrupt_status = 0x50020,
345
+
.drp_interrupt_clear = 0x50028,
346
+
.drp_interrupt_enable = 0x5002c,
347
+
.drp_ecc_error_status0 = 0x520f4,
348
+
.drp_ecc_error_status1 = 0x520f8,
349
+
.drp_ecc_sb_err_syn0 = 0x520fc,
350
+
.drp_ecc_db_err_syn0 = 0x52120,
351
+
};
352
+
353
+
/* LLCC register offset starting from v1.0.0 */
354
+
static const u32 llcc_v1_reg_offset[] = {
301
355
[LLCC_COMMON_HW_INFO] = 0x00030000,
302
356
[LLCC_COMMON_STATUS0] = 0x0003000c,
303
357
};
304
358
305
-
static const u32 llcc_v21_reg_offset[] = {
359
+
/* LLCC register offset starting from v2.0.1 */
360
+
static const u32 llcc_v2_1_reg_offset[] = {
306
361
[LLCC_COMMON_HW_INFO] = 0x00034000,
307
362
[LLCC_COMMON_STATUS0] = 0x0003400c,
308
363
};
···
367
310
.sct_data = sc7180_data,
368
311
.size = ARRAY_SIZE(sc7180_data),
369
312
.need_llcc_cfg = true,
370
-
.reg_offset = llcc_v1_2_reg_offset,
313
+
.reg_offset = llcc_v1_reg_offset,
314
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
371
315
};
372
316
373
317
static const struct qcom_llcc_config sc7280_cfg = {
374
318
.sct_data = sc7280_data,
375
319
.size = ARRAY_SIZE(sc7280_data),
376
320
.need_llcc_cfg = true,
377
-
.reg_offset = llcc_v1_2_reg_offset,
321
+
.reg_offset = llcc_v1_reg_offset,
322
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
378
323
};
379
324
380
325
static const struct qcom_llcc_config sc8180x_cfg = {
381
326
.sct_data = sc8180x_data,
382
327
.size = ARRAY_SIZE(sc8180x_data),
383
328
.need_llcc_cfg = true,
384
-
.reg_offset = llcc_v1_2_reg_offset,
329
+
.reg_offset = llcc_v1_reg_offset,
330
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
385
331
};
386
332
387
333
static const struct qcom_llcc_config sc8280xp_cfg = {
388
334
.sct_data = sc8280xp_data,
389
335
.size = ARRAY_SIZE(sc8280xp_data),
390
336
.need_llcc_cfg = true,
391
-
.reg_offset = llcc_v1_2_reg_offset,
337
+
.reg_offset = llcc_v1_reg_offset,
338
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
392
339
};
393
340
394
341
static const struct qcom_llcc_config sdm845_cfg = {
395
342
.sct_data = sdm845_data,
396
343
.size = ARRAY_SIZE(sdm845_data),
397
344
.need_llcc_cfg = false,
398
-
.reg_offset = llcc_v1_2_reg_offset,
345
+
.reg_offset = llcc_v1_reg_offset,
346
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
399
347
};
400
348
401
349
static const struct qcom_llcc_config sm6350_cfg = {
402
350
.sct_data = sm6350_data,
403
351
.size = ARRAY_SIZE(sm6350_data),
404
352
.need_llcc_cfg = true,
405
-
.reg_offset = llcc_v1_2_reg_offset,
353
+
.reg_offset = llcc_v1_reg_offset,
354
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
406
355
};
407
356
408
357
static const struct qcom_llcc_config sm8150_cfg = {
409
358
.sct_data = sm8150_data,
410
359
.size = ARRAY_SIZE(sm8150_data),
411
360
.need_llcc_cfg = true,
412
-
.reg_offset = llcc_v1_2_reg_offset,
361
+
.reg_offset = llcc_v1_reg_offset,
362
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
413
363
};
414
364
415
365
static const struct qcom_llcc_config sm8250_cfg = {
416
366
.sct_data = sm8250_data,
417
367
.size = ARRAY_SIZE(sm8250_data),
418
368
.need_llcc_cfg = true,
419
-
.reg_offset = llcc_v1_2_reg_offset,
369
+
.reg_offset = llcc_v1_reg_offset,
370
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
420
371
};
421
372
422
373
static const struct qcom_llcc_config sm8350_cfg = {
423
374
.sct_data = sm8350_data,
424
375
.size = ARRAY_SIZE(sm8350_data),
425
376
.need_llcc_cfg = true,
426
-
.reg_offset = llcc_v1_2_reg_offset,
377
+
.reg_offset = llcc_v1_reg_offset,
378
+
.edac_reg_offset = &llcc_v1_edac_reg_offset,
427
379
};
428
380
429
381
static const struct qcom_llcc_config sm8450_cfg = {
430
382
.sct_data = sm8450_data,
431
383
.size = ARRAY_SIZE(sm8450_data),
432
384
.need_llcc_cfg = true,
433
-
.reg_offset = llcc_v21_reg_offset,
385
+
.reg_offset = llcc_v2_1_reg_offset,
386
+
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
434
387
};
435
388
436
389
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
···
841
774
842
775
drv_data->cfg = llcc_cfg;
843
776
drv_data->cfg_size = sz;
777
+
drv_data->edac_reg_offset = cfg->edac_reg_offset;
844
778
mutex_init(&drv_data->lock);
845
779
platform_set_drvdata(pdev, drv_data);
846
780
+9
drivers/soc/qcom/qcom_stats.c
+9
drivers/soc/qcom/qcom_stats.c
···
246
246
.subsystem_stats_in_smem = false,
247
247
};
248
248
249
+
static const struct stats_config rpmh_data_sdm845 = {
250
+
.stats_offset = 0x48,
251
+
.num_records = 2,
252
+
.appended_stats_avail = false,
253
+
.dynamic_offset = false,
254
+
.subsystem_stats_in_smem = true,
255
+
};
256
+
249
257
static const struct stats_config rpmh_data = {
250
258
.stats_offset = 0x48,
251
259
.num_records = 3,
···
269
261
{ .compatible = "qcom,msm8974-rpm-stats", .data = &rpm_data_dba0 },
270
262
{ .compatible = "qcom,rpm-stats", .data = &rpm_data },
271
263
{ .compatible = "qcom,rpmh-stats", .data = &rpmh_data },
264
+
{ .compatible = "qcom,sdm845-rpmh-stats", .data = &rpmh_data_sdm845 },
272
265
{ }
273
266
};
274
267
MODULE_DEVICE_TABLE(of, qcom_stats_table);
+25
-25
drivers/soc/qcom/qmi_encdec.c
+25
-25
drivers/soc/qcom/qmi_encdec.c
···
57
57
#define TLV_TYPE_SIZE sizeof(u8)
58
58
#define OPTIONAL_TLV_TYPE_START 0x10
59
59
60
-
static int qmi_encode(struct qmi_elem_info *ei_array, void *out_buf,
60
+
static int qmi_encode(const struct qmi_elem_info *ei_array, void *out_buf,
61
61
const void *in_c_struct, u32 out_buf_len,
62
62
int enc_level);
63
63
64
-
static int qmi_decode(struct qmi_elem_info *ei_array, void *out_c_struct,
64
+
static int qmi_decode(const struct qmi_elem_info *ei_array, void *out_c_struct,
65
65
const void *in_buf, u32 in_buf_len, int dec_level);
66
66
67
67
/**
···
76
76
*
77
77
* Return: struct info of the next element that can be encoded.
78
78
*/
79
-
static struct qmi_elem_info *skip_to_next_elem(struct qmi_elem_info *ei_array,
80
-
int level)
79
+
static const struct qmi_elem_info *
80
+
skip_to_next_elem(const struct qmi_elem_info *ei_array, int level)
81
81
{
82
-
struct qmi_elem_info *temp_ei = ei_array;
82
+
const struct qmi_elem_info *temp_ei = ei_array;
83
83
u8 tlv_type;
84
84
85
85
if (level > 1) {
···
101
101
*
102
102
* Return: Expected minimum length of the QMI message or 0 on error.
103
103
*/
104
-
static int qmi_calc_min_msg_len(struct qmi_elem_info *ei_array,
104
+
static int qmi_calc_min_msg_len(const struct qmi_elem_info *ei_array,
105
105
int level)
106
106
{
107
107
int min_msg_len = 0;
108
-
struct qmi_elem_info *temp_ei = ei_array;
108
+
const struct qmi_elem_info *temp_ei = ei_array;
109
109
110
110
if (!ei_array)
111
111
return min_msg_len;
···
194
194
* Return: The number of bytes of encoded information on success or negative
195
195
* errno on error.
196
196
*/
197
-
static int qmi_encode_struct_elem(struct qmi_elem_info *ei_array,
197
+
static int qmi_encode_struct_elem(const struct qmi_elem_info *ei_array,
198
198
void *buf_dst, const void *buf_src,
199
199
u32 elem_len, u32 out_buf_len,
200
200
int enc_level)
201
201
{
202
202
int i, rc, encoded_bytes = 0;
203
-
struct qmi_elem_info *temp_ei = ei_array;
203
+
const struct qmi_elem_info *temp_ei = ei_array;
204
204
205
205
for (i = 0; i < elem_len; i++) {
206
206
rc = qmi_encode(temp_ei->ei_array, buf_dst, buf_src,
···
233
233
* Return: The number of bytes of encoded information on success or negative
234
234
* errno on error.
235
235
*/
236
-
static int qmi_encode_string_elem(struct qmi_elem_info *ei_array,
236
+
static int qmi_encode_string_elem(const struct qmi_elem_info *ei_array,
237
237
void *buf_dst, const void *buf_src,
238
238
u32 out_buf_len, int enc_level)
239
239
{
240
240
int rc;
241
241
int encoded_bytes = 0;
242
-
struct qmi_elem_info *temp_ei = ei_array;
242
+
const struct qmi_elem_info *temp_ei = ei_array;
243
243
u32 string_len = 0;
244
244
u32 string_len_sz = 0;
245
245
···
289
289
* Return: The number of bytes of encoded information on success or negative
290
290
* errno on error.
291
291
*/
292
-
static int qmi_encode(struct qmi_elem_info *ei_array, void *out_buf,
292
+
static int qmi_encode(const struct qmi_elem_info *ei_array, void *out_buf,
293
293
const void *in_c_struct, u32 out_buf_len,
294
294
int enc_level)
295
295
{
296
-
struct qmi_elem_info *temp_ei = ei_array;
296
+
const struct qmi_elem_info *temp_ei = ei_array;
297
297
u8 opt_flag_value = 0;
298
298
u32 data_len_value = 0, data_len_sz;
299
299
u8 *buf_dst = (u8 *)out_buf;
···
468
468
* Return: The total size of the decoded data elements on success, negative
469
469
* errno on error.
470
470
*/
471
-
static int qmi_decode_struct_elem(struct qmi_elem_info *ei_array,
471
+
static int qmi_decode_struct_elem(const struct qmi_elem_info *ei_array,
472
472
void *buf_dst, const void *buf_src,
473
473
u32 elem_len, u32 tlv_len,
474
474
int dec_level)
475
475
{
476
476
int i, rc, decoded_bytes = 0;
477
-
struct qmi_elem_info *temp_ei = ei_array;
477
+
const struct qmi_elem_info *temp_ei = ei_array;
478
478
479
479
for (i = 0; i < elem_len && decoded_bytes < tlv_len; i++) {
480
480
rc = qmi_decode(temp_ei->ei_array, buf_dst, buf_src,
···
514
514
* Return: The total size of the decoded data elements on success, negative
515
515
* errno on error.
516
516
*/
517
-
static int qmi_decode_string_elem(struct qmi_elem_info *ei_array,
517
+
static int qmi_decode_string_elem(const struct qmi_elem_info *ei_array,
518
518
void *buf_dst, const void *buf_src,
519
519
u32 tlv_len, int dec_level)
520
520
{
···
522
522
int decoded_bytes = 0;
523
523
u32 string_len = 0;
524
524
u32 string_len_sz = 0;
525
-
struct qmi_elem_info *temp_ei = ei_array;
525
+
const struct qmi_elem_info *temp_ei = ei_array;
526
526
527
527
if (dec_level == 1) {
528
528
string_len = tlv_len;
···
564
564
*
565
565
* Return: Pointer to struct info, if found
566
566
*/
567
-
static struct qmi_elem_info *find_ei(struct qmi_elem_info *ei_array,
568
-
u32 type)
567
+
static const struct qmi_elem_info *find_ei(const struct qmi_elem_info *ei_array,
568
+
u32 type)
569
569
{
570
-
struct qmi_elem_info *temp_ei = ei_array;
570
+
const struct qmi_elem_info *temp_ei = ei_array;
571
571
572
572
while (temp_ei->data_type != QMI_EOTI) {
573
573
if (temp_ei->tlv_type == (u8)type)
···
590
590
* Return: The number of bytes of decoded information on success, negative
591
591
* errno on error.
592
592
*/
593
-
static int qmi_decode(struct qmi_elem_info *ei_array, void *out_c_struct,
593
+
static int qmi_decode(const struct qmi_elem_info *ei_array, void *out_c_struct,
594
594
const void *in_buf, u32 in_buf_len,
595
595
int dec_level)
596
596
{
597
-
struct qmi_elem_info *temp_ei = ei_array;
597
+
const struct qmi_elem_info *temp_ei = ei_array;
598
598
u8 opt_flag_value = 1;
599
599
u32 data_len_value = 0, data_len_sz = 0;
600
600
u8 *buf_dst = out_c_struct;
···
713
713
* Return: Buffer with encoded message, or negative ERR_PTR() on error
714
714
*/
715
715
void *qmi_encode_message(int type, unsigned int msg_id, size_t *len,
716
-
unsigned int txn_id, struct qmi_elem_info *ei,
716
+
unsigned int txn_id, const struct qmi_elem_info *ei,
717
717
const void *c_struct)
718
718
{
719
719
struct qmi_header *hdr;
···
767
767
* errno on error.
768
768
*/
769
769
int qmi_decode_message(const void *buf, size_t len,
770
-
struct qmi_elem_info *ei, void *c_struct)
770
+
const struct qmi_elem_info *ei, void *c_struct)
771
771
{
772
772
if (!ei)
773
773
return -EINVAL;
···
781
781
EXPORT_SYMBOL(qmi_decode_message);
782
782
783
783
/* Common header in all QMI responses */
784
-
struct qmi_elem_info qmi_response_type_v01_ei[] = {
784
+
const struct qmi_elem_info qmi_response_type_v01_ei[] = {
785
785
{
786
786
.data_type = QMI_SIGNED_2_BYTE_ENUM,
787
787
.elem_len = 1,
+7
-5
drivers/soc/qcom/qmi_interface.c
+7
-5
drivers/soc/qcom/qmi_interface.c
···
305
305
* Return: Transaction id on success, negative errno on failure.
306
306
*/
307
307
int qmi_txn_init(struct qmi_handle *qmi, struct qmi_txn *txn,
308
-
struct qmi_elem_info *ei, void *c_struct)
308
+
const struct qmi_elem_info *ei, void *c_struct)
309
309
{
310
310
int ret;
311
311
···
736
736
static ssize_t qmi_send_message(struct qmi_handle *qmi,
737
737
struct sockaddr_qrtr *sq, struct qmi_txn *txn,
738
738
int type, int msg_id, size_t len,
739
-
struct qmi_elem_info *ei, const void *c_struct)
739
+
const struct qmi_elem_info *ei,
740
+
const void *c_struct)
740
741
{
741
742
struct msghdr msghdr = {};
742
743
struct kvec iv;
···
788
787
*/
789
788
ssize_t qmi_send_request(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
790
789
struct qmi_txn *txn, int msg_id, size_t len,
791
-
struct qmi_elem_info *ei, const void *c_struct)
790
+
const struct qmi_elem_info *ei, const void *c_struct)
792
791
{
793
792
return qmi_send_message(qmi, sq, txn, QMI_REQUEST, msg_id, len, ei,
794
793
c_struct);
···
809
808
*/
810
809
ssize_t qmi_send_response(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
811
810
struct qmi_txn *txn, int msg_id, size_t len,
812
-
struct qmi_elem_info *ei, const void *c_struct)
811
+
const struct qmi_elem_info *ei, const void *c_struct)
813
812
{
814
813
return qmi_send_message(qmi, sq, txn, QMI_RESPONSE, msg_id, len, ei,
815
814
c_struct);
···
828
827
* Return: 0 on success, negative errno on failure.
829
828
*/
830
829
ssize_t qmi_send_indication(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
831
-
int msg_id, size_t len, struct qmi_elem_info *ei,
830
+
int msg_id, size_t len,
831
+
const struct qmi_elem_info *ei,
832
832
const void *c_struct)
833
833
{
834
834
struct qmi_txn txn;
+22
drivers/soc/qcom/rpmpd.c
+22
drivers/soc/qcom/rpmpd.c
···
29
29
#define RPMPD_RWLM 0x6d6c7772
30
30
#define RPMPD_RWSC 0x63737772
31
31
#define RPMPD_RWSM 0x6d737772
32
+
#define RPMPD_RWGX 0x78677772
32
33
33
34
/* Operation Keys */
34
35
#define KEY_CORNER 0x6e726f63 /* corn */
···
434
433
.max_state = RPM_SMD_LEVEL_BINNING,
435
434
};
436
435
436
+
DEFINE_RPMPD_PAIR(sm6375, vddgx, vddgx_ao, RWGX, LEVEL, 0);
437
+
static struct rpmpd *sm6375_rpmpds[] = {
438
+
[SM6375_VDDCX] = &sm6125_vddcx,
439
+
[SM6375_VDDCX_AO] = &sm6125_vddcx_ao,
440
+
[SM6375_VDDCX_VFL] = &sm6125_vddcx_vfl,
441
+
[SM6375_VDDMX] = &sm6125_vddmx,
442
+
[SM6375_VDDMX_AO] = &sm6125_vddmx_ao,
443
+
[SM6375_VDDMX_VFL] = &sm6125_vddmx_vfl,
444
+
[SM6375_VDDGX] = &sm6375_vddgx,
445
+
[SM6375_VDDGX_AO] = &sm6375_vddgx_ao,
446
+
[SM6375_VDD_LPI_CX] = &sm6115_vdd_lpi_cx,
447
+
[SM6375_VDD_LPI_MX] = &sm6115_vdd_lpi_mx,
448
+
};
449
+
450
+
static const struct rpmpd_desc sm6375_desc = {
451
+
.rpmpds = sm6375_rpmpds,
452
+
.num_pds = ARRAY_SIZE(sm6375_rpmpds),
453
+
.max_state = RPM_SMD_LEVEL_TURBO_NO_CPR,
454
+
};
455
+
437
456
static struct rpmpd *qcm2290_rpmpds[] = {
438
457
[QCM2290_VDDCX] = &sm6115_vddcx,
439
458
[QCM2290_VDDCX_AO] = &sm6115_vddcx_ao,
···
487
466
{ .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc },
488
467
{ .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc },
489
468
{ .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc },
469
+
{ .compatible = "qcom,sm6375-rpmpd", .data = &sm6375_desc },
490
470
{ }
491
471
};
492
472
MODULE_DEVICE_TABLE(of, rpmpd_match_table);
+2
-1
drivers/soc/qcom/smem_state.c
+2
-1
drivers/soc/qcom/smem_state.c
···
136
136
struct qcom_smem_state *state = container_of(ref, struct qcom_smem_state, refcount);
137
137
138
138
list_del(&state->list);
139
+
of_node_put(state->of_node);
139
140
kfree(state);
140
141
}
141
142
···
206
205
207
206
kref_init(&state->refcount);
208
207
209
-
state->of_node = of_node;
208
+
state->of_node = of_node_get(of_node);
210
209
state->ops = *ops;
211
210
state->priv = priv;
212
211
+13
-7
drivers/soc/qcom/smsm.c
+13
-7
drivers/soc/qcom/smsm.c
···
526
526
for (id = 0; id < smsm->num_hosts; id++) {
527
527
ret = smsm_parse_ipc(smsm, id);
528
528
if (ret < 0)
529
-
return ret;
529
+
goto out_put;
530
530
}
531
531
532
532
/* Acquire the main SMSM state vector */
···
534
534
smsm->num_entries * sizeof(u32));
535
535
if (ret < 0 && ret != -EEXIST) {
536
536
dev_err(&pdev->dev, "unable to allocate shared state entry\n");
537
-
return ret;
537
+
goto out_put;
538
538
}
539
539
540
540
states = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL);
541
541
if (IS_ERR(states)) {
542
542
dev_err(&pdev->dev, "Unable to acquire shared state entry\n");
543
-
return PTR_ERR(states);
543
+
ret = PTR_ERR(states);
544
+
goto out_put;
544
545
}
545
546
546
547
/* Acquire the list of interrupt mask vectors */
···
549
548
ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, size);
550
549
if (ret < 0 && ret != -EEXIST) {
551
550
dev_err(&pdev->dev, "unable to allocate smsm interrupt mask\n");
552
-
return ret;
551
+
goto out_put;
553
552
}
554
553
555
554
intr_mask = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL);
556
555
if (IS_ERR(intr_mask)) {
557
556
dev_err(&pdev->dev, "unable to acquire shared memory interrupt mask\n");
558
-
return PTR_ERR(intr_mask);
557
+
ret = PTR_ERR(intr_mask);
558
+
goto out_put;
559
559
}
560
560
561
561
/* Setup the reference to the local state bits */
···
567
565
smsm->state = qcom_smem_state_register(local_node, &smsm_state_ops, smsm);
568
566
if (IS_ERR(smsm->state)) {
569
567
dev_err(smsm->dev, "failed to register qcom_smem_state\n");
570
-
return PTR_ERR(smsm->state);
568
+
ret = PTR_ERR(smsm->state);
569
+
goto out_put;
571
570
}
572
571
573
572
/* Register handlers for remote processor entries of interest. */
···
598
595
}
599
596
600
597
platform_set_drvdata(pdev, smsm);
598
+
of_node_put(local_node);
601
599
602
600
return 0;
603
601
604
602
unwind_interfaces:
603
+
of_node_put(node);
605
604
for (id = 0; id < smsm->num_entries; id++)
606
605
if (smsm->entries[id].domain)
607
606
irq_domain_remove(smsm->entries[id].domain);
608
607
609
608
qcom_smem_state_unregister(smsm->state);
610
-
609
+
out_put:
610
+
of_node_put(local_node);
611
611
return ret;
612
612
}
613
613
+2
drivers/soc/qcom/socinfo.c
+2
drivers/soc/qcom/socinfo.c
···
104
104
[36] = "PM8009",
105
105
[38] = "PM8150C",
106
106
[41] = "SMB2351",
107
+
[45] = "PM6125",
107
108
[47] = "PMK8350",
108
109
[48] = "PM8350",
109
110
[49] = "PM8350C",
···
335
334
{ 482, "SM8450" },
336
335
{ 487, "SC7280" },
337
336
{ 495, "SC7180P" },
337
+
{ 507, "SM6375" },
338
338
};
339
339
340
340
static const char *socinfo_machine(struct device *dev, unsigned int id)
+12
include/dt-bindings/power/qcom-rpmpd.h
+12
include/dt-bindings/power/qcom-rpmpd.h
···
36
36
#define SM6350_MSS 4
37
37
#define SM6350_MX 5
38
38
39
+
/* SM6350 Power Domain Indexes */
40
+
#define SM6375_VDDCX 0
41
+
#define SM6375_VDDCX_AO 1
42
+
#define SM6375_VDDCX_VFL 2
43
+
#define SM6375_VDDMX 3
44
+
#define SM6375_VDDMX_AO 4
45
+
#define SM6375_VDDMX_VFL 5
46
+
#define SM6375_VDDGX 6
47
+
#define SM6375_VDDGX_AO 7
48
+
#define SM6375_VDD_LPI_CX 8
49
+
#define SM6375_VDD_LPI_MX 9
50
+
39
51
/* SM8150 Power Domain Indexes */
40
52
#define SM8150_MSS 0
41
53
#define SM8150_EBI 1
+30
include/linux/soc/qcom/llcc-qcom.h
+30
include/linux/soc/qcom/llcc-qcom.h
···
78
78
u8 ways_shift;
79
79
};
80
80
81
+
struct llcc_edac_reg_offset {
82
+
/* LLCC TRP registers */
83
+
u32 trp_ecc_error_status0;
84
+
u32 trp_ecc_error_status1;
85
+
u32 trp_ecc_sb_err_syn0;
86
+
u32 trp_ecc_db_err_syn0;
87
+
u32 trp_ecc_error_cntr_clear;
88
+
u32 trp_interrupt_0_status;
89
+
u32 trp_interrupt_0_clear;
90
+
u32 trp_interrupt_0_enable;
91
+
92
+
/* LLCC Common registers */
93
+
u32 cmn_status0;
94
+
u32 cmn_interrupt_0_enable;
95
+
u32 cmn_interrupt_2_enable;
96
+
97
+
/* LLCC DRP registers */
98
+
u32 drp_ecc_error_cfg;
99
+
u32 drp_ecc_error_cntr_clear;
100
+
u32 drp_interrupt_status;
101
+
u32 drp_interrupt_clear;
102
+
u32 drp_interrupt_enable;
103
+
u32 drp_ecc_error_status0;
104
+
u32 drp_ecc_error_status1;
105
+
u32 drp_ecc_sb_err_syn0;
106
+
u32 drp_ecc_db_err_syn0;
107
+
};
108
+
81
109
/**
82
110
* struct llcc_drv_data - Data associated with the llcc driver
83
111
* @regmap: regmap associated with the llcc device
84
112
* @bcast_regmap: regmap associated with llcc broadcast offset
85
113
* @cfg: pointer to the data structure for slice configuration
114
+
* @edac_reg_offset: Offset of the LLCC EDAC registers
86
115
* @lock: mutex associated with each slice
87
116
* @cfg_size: size of the config data table
88
117
* @max_slices: max slices as read from device tree
···
125
96
struct regmap *regmap;
126
97
struct regmap *bcast_regmap;
127
98
const struct llcc_slice_config *cfg;
99
+
const struct llcc_edac_reg_offset *edac_reg_offset;
128
100
struct mutex lock;
129
101
u32 cfg_size;
130
102
u32 max_slices;
+10
-10
include/linux/soc/qcom/qmi.h
+10
-10
include/linux/soc/qcom/qmi.h
···
75
75
enum qmi_array_type array_type;
76
76
u8 tlv_type;
77
77
u32 offset;
78
-
struct qmi_elem_info *ei_array;
78
+
const struct qmi_elem_info *ei_array;
79
79
};
80
80
81
81
#define QMI_RESULT_SUCCESS_V01 0
···
102
102
u16 error;
103
103
};
104
104
105
-
extern struct qmi_elem_info qmi_response_type_v01_ei[];
105
+
extern const struct qmi_elem_info qmi_response_type_v01_ei[];
106
106
107
107
/**
108
108
* struct qmi_service - context to track lookup-results
···
173
173
struct completion completion;
174
174
int result;
175
175
176
-
struct qmi_elem_info *ei;
176
+
const struct qmi_elem_info *ei;
177
177
void *dest;
178
178
};
179
179
···
189
189
unsigned int type;
190
190
unsigned int msg_id;
191
191
192
-
struct qmi_elem_info *ei;
192
+
const struct qmi_elem_info *ei;
193
193
194
194
size_t decoded_size;
195
195
void (*fn)(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
···
249
249
250
250
ssize_t qmi_send_request(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
251
251
struct qmi_txn *txn, int msg_id, size_t len,
252
-
struct qmi_elem_info *ei, const void *c_struct);
252
+
const struct qmi_elem_info *ei, const void *c_struct);
253
253
ssize_t qmi_send_response(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
254
254
struct qmi_txn *txn, int msg_id, size_t len,
255
-
struct qmi_elem_info *ei, const void *c_struct);
255
+
const struct qmi_elem_info *ei, const void *c_struct);
256
256
ssize_t qmi_send_indication(struct qmi_handle *qmi, struct sockaddr_qrtr *sq,
257
-
int msg_id, size_t len, struct qmi_elem_info *ei,
257
+
int msg_id, size_t len, const struct qmi_elem_info *ei,
258
258
const void *c_struct);
259
259
260
260
void *qmi_encode_message(int type, unsigned int msg_id, size_t *len,
261
-
unsigned int txn_id, struct qmi_elem_info *ei,
261
+
unsigned int txn_id, const struct qmi_elem_info *ei,
262
262
const void *c_struct);
263
263
264
264
int qmi_decode_message(const void *buf, size_t len,
265
-
struct qmi_elem_info *ei, void *c_struct);
265
+
const struct qmi_elem_info *ei, void *c_struct);
266
266
267
267
int qmi_txn_init(struct qmi_handle *qmi, struct qmi_txn *txn,
268
-
struct qmi_elem_info *ei, void *c_struct);
268
+
const struct qmi_elem_info *ei, void *c_struct);
269
269
int qmi_txn_wait(struct qmi_txn *txn, unsigned long timeout);
270
270
void qmi_txn_cancel(struct qmi_txn *txn);
271
271
+5
-5
samples/qmi/qmi_sample_client.c
+5
-5
samples/qmi/qmi_sample_client.c
···
42
42
char name[TEST_MAX_NAME_SIZE_V01];
43
43
};
44
44
45
-
static struct qmi_elem_info test_name_type_v01_ei[] = {
45
+
static const struct qmi_elem_info test_name_type_v01_ei[] = {
46
46
{
47
47
.data_type = QMI_DATA_LEN,
48
48
.elem_len = 1,
···
71
71
struct test_name_type_v01 client_name;
72
72
};
73
73
74
-
static struct qmi_elem_info test_ping_req_msg_v01_ei[] = {
74
+
static const struct qmi_elem_info test_ping_req_msg_v01_ei[] = {
75
75
{
76
76
.data_type = QMI_UNSIGNED_1_BYTE,
77
77
.elem_len = 4,
···
113
113
struct test_name_type_v01 service_name;
114
114
};
115
115
116
-
static struct qmi_elem_info test_ping_resp_msg_v01_ei[] = {
116
+
static const struct qmi_elem_info test_ping_resp_msg_v01_ei[] = {
117
117
{
118
118
.data_type = QMI_STRUCT,
119
119
.elem_len = 1,
···
172
172
struct test_name_type_v01 client_name;
173
173
};
174
174
175
-
static struct qmi_elem_info test_data_req_msg_v01_ei[] = {
175
+
static const struct qmi_elem_info test_data_req_msg_v01_ei[] = {
176
176
{
177
177
.data_type = QMI_DATA_LEN,
178
178
.elem_len = 1,
···
224
224
struct test_name_type_v01 service_name;
225
225
};
226
226
227
-
static struct qmi_elem_info test_data_resp_msg_v01_ei[] = {
227
+
static const struct qmi_elem_info test_data_resp_msg_v01_ei[] = {
228
228
{
229
229
.data_type = QMI_STRUCT,
230
230
.elem_len = 1,