Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next

+1 -2

arch/sparc/Kconfig

··· 31 31 32 32 config SPARC32 33 33 def_bool !64BIT 34 + select GENERIC_ATOMIC64 34 35 35 36 config SPARC64 36 37 def_bool 64BIT ··· 384 383 making when dealing with multi-core CPU chips at a cost of slightly 385 384 increased overhead in some places. If unsure say N here. 386 385 387 - if SPARC64 388 386 source "kernel/Kconfig.preempt" 389 - endif 390 387 391 388 config CMDLINE_BOOL 392 389 bool "Default bootloader kernel arguments"

+1 -103

arch/sparc/include/asm/atomic_32.h

··· 13 13 14 14 #include <linux/types.h> 15 15 16 - #ifdef __KERNEL__ 16 + #include <asm-generic/atomic64.h> 17 17 18 18 #include <asm/system.h> 19 19 ··· 52 52 #define atomic_dec_and_test(v) (atomic_dec_return(v) == 0) 53 53 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) 54 54 55 - 56 - /* This is the old 24-bit implementation. It's still used internally 57 - * by some sparc-specific code, notably the semaphore implementation. 58 - */ 59 - typedef struct { volatile int counter; } atomic24_t; 60 - 61 - #ifndef CONFIG_SMP 62 - 63 - #define ATOMIC24_INIT(i) { (i) } 64 - #define atomic24_read(v) ((v)->counter) 65 - #define atomic24_set(v, i) (((v)->counter) = i) 66 - 67 - #else 68 - /* We do the bulk of the actual work out of line in two common 69 - * routines in assembler, see arch/sparc/lib/atomic.S for the 70 - * "fun" details. 71 - * 72 - * For SMP the trick is you embed the spin lock byte within 73 - * the word, use the low byte so signedness is easily retained 74 - * via a quick arithmetic shift. It looks like this: 75 - * 76 - * ---------------------------------------- 77 - * | signed 24-bit counter value | lock | atomic_t 78 - * ---------------------------------------- 79 - * 31 8 7 0 80 - */ 81 - 82 - #define ATOMIC24_INIT(i) { ((i) << 8) } 83 - 84 - static inline int atomic24_read(const atomic24_t *v) 85 - { 86 - int ret = v->counter; 87 - 88 - while(ret & 0xff) 89 - ret = v->counter; 90 - 91 - return ret >> 8; 92 - } 93 - 94 - #define atomic24_set(v, i) (((v)->counter) = ((i) << 8)) 95 - #endif 96 - 97 - static inline int __atomic24_add(int i, atomic24_t *v) 98 - { 99 - register volatile int *ptr asm("g1"); 100 - register int increment asm("g2"); 101 - register int tmp1 asm("g3"); 102 - register int tmp2 asm("g4"); 103 - register int tmp3 asm("g7"); 104 - 105 - ptr = &v->counter; 106 - increment = i; 107 - 108 - __asm__ __volatile__( 109 - "mov %%o7, %%g4\n\t" 110 - "call ___atomic24_add\n\t" 111 - " add %%o7, 8, %%o7\n" 112 - : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3) 113 - : "0" (increment), "r" (ptr) 114 - : "memory", "cc"); 115 - 116 - return increment; 117 - } 118 - 119 - static inline int __atomic24_sub(int i, atomic24_t *v) 120 - { 121 - register volatile int *ptr asm("g1"); 122 - register int increment asm("g2"); 123 - register int tmp1 asm("g3"); 124 - register int tmp2 asm("g4"); 125 - register int tmp3 asm("g7"); 126 - 127 - ptr = &v->counter; 128 - increment = i; 129 - 130 - __asm__ __volatile__( 131 - "mov %%o7, %%g4\n\t" 132 - "call ___atomic24_sub\n\t" 133 - " add %%o7, 8, %%o7\n" 134 - : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3) 135 - : "0" (increment), "r" (ptr) 136 - : "memory", "cc"); 137 - 138 - return increment; 139 - } 140 - 141 - #define atomic24_add(i, v) ((void)__atomic24_add((i), (v))) 142 - #define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v))) 143 - 144 - #define atomic24_dec_return(v) __atomic24_sub(1, (v)) 145 - #define atomic24_inc_return(v) __atomic24_add(1, (v)) 146 - 147 - #define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0) 148 - #define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0) 149 - 150 - #define atomic24_inc(v) ((void)__atomic24_add(1, (v))) 151 - #define atomic24_dec(v) ((void)__atomic24_sub(1, (v))) 152 - 153 - #define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0) 154 - 155 55 /* Atomic operations are already serializing */ 156 56 #define smp_mb__before_atomic_dec() barrier() 157 57 #define smp_mb__after_atomic_dec() barrier() 158 58 #define smp_mb__before_atomic_inc() barrier() 159 59 #define smp_mb__after_atomic_inc() barrier() 160 - 161 - #endif /* !(__KERNEL__) */ 162 60 163 61 #endif /* !(__ARCH_SPARC_ATOMIC__) */

+3 -7

arch/sparc/include/asm/page_32.h

··· 8 8 #ifndef _SPARC_PAGE_H 9 9 #define _SPARC_PAGE_H 10 10 11 - #define PAGE_SHIFT 12 11 + #include <linux/const.h> 12 12 13 - #ifndef __ASSEMBLY__ 14 - /* I have my suspicions... -DaveM */ 15 - #define PAGE_SIZE (1UL << PAGE_SHIFT) 16 - #else 17 - #define PAGE_SIZE (1 << PAGE_SHIFT) 18 - #endif 13 + #define PAGE_SHIFT 12 14 + #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) 19 15 #define PAGE_MASK (~(PAGE_SIZE-1)) 20 16 21 17 #include <asm/btfixup.h>

-171

arch/sparc/include/asm/pgtsun4.h

··· 1 - /* 2 - * pgtsun4.h: Sun4 specific pgtable.h defines and code. 3 - * 4 - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 - * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 - */ 7 - #ifndef _SPARC_PGTSUN4C_H 8 - #define _SPARC_PGTSUN4C_H 9 - 10 - #include <asm/contregs.h> 11 - 12 - /* PMD_SHIFT determines the size of the area a second-level page table can map */ 13 - #define SUN4C_PMD_SHIFT 23 14 - 15 - /* PGDIR_SHIFT determines what a third-level page table entry can map */ 16 - #define SUN4C_PGDIR_SHIFT 23 17 - #define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT) 18 - #define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1)) 19 - #define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK) 20 - 21 - /* To represent how the sun4c mmu really lays things out. */ 22 - #define SUN4C_REAL_PGDIR_SHIFT 18 23 - #define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT) 24 - #define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1)) 25 - #define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK) 26 - 27 - /* 19 bit PFN on sun4 */ 28 - #define SUN4C_PFN_MASK 0x7ffff 29 - 30 - /* Don't increase these unless the structures in sun4c.c are fixed */ 31 - #define SUN4C_MAX_SEGMAPS 256 32 - #define SUN4C_MAX_CONTEXTS 16 33 - 34 - /* 35 - * To be efficient, and not have to worry about allocating such 36 - * a huge pgd, we make the kernel sun4c tables each hold 1024 37 - * entries and the pgd similarly just like the i386 tables. 38 - */ 39 - #define SUN4C_PTRS_PER_PTE 1024 40 - #define SUN4C_PTRS_PER_PMD 1 41 - #define SUN4C_PTRS_PER_PGD 1024 42 - 43 - /* 44 - * Sparc SUN4C pte fields. 45 - */ 46 - #define _SUN4C_PAGE_VALID 0x80000000 47 - #define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */ 48 - #define _SUN4C_PAGE_DIRTY 0x40000000 49 - #define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */ 50 - #define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */ 51 - #define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */ 52 - #define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */ 53 - #define _SUN4C_PAGE_IO 0x04000000 /* I/O page */ 54 - #define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */ 55 - #define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */ 56 - #define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */ 57 - #define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */ 58 - #define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */ 59 - 60 - #define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\ 61 - _SUN4C_PAGE_ACCESSED) 62 - #define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\ 63 - _SUN4C_PAGE_MODIFIED) 64 - 65 - #define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED) 66 - 67 - #define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT) 68 - #define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\ 69 - _SUN4C_PAGE_WRITE) 70 - #define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE) 71 - #define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE) 72 - #define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\ 73 - _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV) 74 - 75 - /* SUN4C swap entry encoding 76 - * 77 - * We use 5 bits for the type and 19 for the offset. This gives us 78 - * 32 swapfiles of 4GB each. Encoding looks like: 79 - * 80 - * RRRRRRRRooooooooooooooooooottttt 81 - * fedcba9876543210fedcba9876543210 82 - * 83 - * The top 8 bits are reserved for protection and status bits, especially 84 - * FILE and PRESENT. 85 - */ 86 - #define SUN4C_SWP_TYPE_MASK 0x1f 87 - #define SUN4C_SWP_OFF_MASK 0x7ffff 88 - #define SUN4C_SWP_OFF_SHIFT 5 89 - 90 - #ifndef __ASSEMBLY__ 91 - 92 - static inline unsigned long sun4c_get_synchronous_error(void) 93 - { 94 - unsigned long sync_err; 95 - 96 - __asm__ __volatile__("lda [%1] %2, %0\n\t" : 97 - "=r" (sync_err) : 98 - "r" (AC_SYNC_ERR), "i" (ASI_CONTROL)); 99 - return sync_err; 100 - } 101 - 102 - static inline unsigned long sun4c_get_synchronous_address(void) 103 - { 104 - unsigned long sync_addr; 105 - 106 - __asm__ __volatile__("lda [%1] %2, %0\n\t" : 107 - "=r" (sync_addr) : 108 - "r" (AC_SYNC_VA), "i" (ASI_CONTROL)); 109 - return sync_addr; 110 - } 111 - 112 - /* SUN4 pte, segmap, and context manipulation */ 113 - static inline unsigned long sun4c_get_segmap(unsigned long addr) 114 - { 115 - register unsigned long entry; 116 - 117 - __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" : 118 - "=r" (entry) : 119 - "r" (addr), "i" (ASI_SEGMAP)); 120 - return entry; 121 - } 122 - 123 - static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry) 124 - { 125 - __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : : 126 - "r" (addr), "r" (entry), 127 - "i" (ASI_SEGMAP) 128 - : "memory"); 129 - } 130 - 131 - static inline unsigned long sun4c_get_pte(unsigned long addr) 132 - { 133 - register unsigned long entry; 134 - 135 - __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 136 - "=r" (entry) : 137 - "r" (addr), "i" (ASI_PTE)); 138 - return entry; 139 - } 140 - 141 - static inline void sun4c_put_pte(unsigned long addr, unsigned long entry) 142 - { 143 - __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : : 144 - "r" (addr), 145 - "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE) 146 - : "memory"); 147 - } 148 - 149 - static inline int sun4c_get_context(void) 150 - { 151 - register int ctx; 152 - 153 - __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" : 154 - "=r" (ctx) : 155 - "r" (AC_CONTEXT), "i" (ASI_CONTROL)); 156 - 157 - return ctx; 158 - } 159 - 160 - static inline int sun4c_set_context(int ctx) 161 - { 162 - __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : : 163 - "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL) 164 - : "memory"); 165 - 166 - return ctx; 167 - } 168 - 169 - #endif /* !(__ASSEMBLY__) */ 170 - 171 - #endif /* !(_SPARC_PGTSUN4_H) */

+1 -1

arch/sparc/include/asm/thread_info_32.h

··· 95 95 * Observe the order of get_free_pages() in alloc_thread_info_node(). 96 96 * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste. 97 97 */ 98 - #define THREAD_SIZE 8192 98 + #define THREAD_SIZE (2 * PAGE_SIZE) 99 99 100 100 /* 101 101 * Offsets in thread_info structure, used in assembly code

-55

arch/sparc/lib/atomic_32.S

··· 40 40 mov %g4, %o7 41 41 #endif 42 42 43 - /* Read asm-sparc/atomic.h carefully to understand how this works for SMP. 44 - * Really, some things here for SMP are overly clever, go read the header. 45 - */ 46 - .globl ___atomic24_add 47 - ___atomic24_add: 48 - rd %psr, %g3 ! Keep the code small, old way was stupid 49 - nop; nop; nop; ! Let the bits set 50 - or %g3, PSR_PIL, %g7 ! Disable interrupts 51 - wr %g7, 0x0, %psr ! Set %psr 52 - nop; nop; nop; ! Let the bits set 53 - #ifdef CONFIG_SMP 54 - 1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP. 55 - orcc %g7, 0x0, %g0 ! Did we get it? 56 - bne 1b ! Nope... 57 - ld [%g1], %g7 ! Load locked atomic24_t 58 - sra %g7, 8, %g7 ! Get signed 24-bit integer 59 - add %g7, %g2, %g2 ! Add in argument 60 - sll %g2, 8, %g7 ! Transpose back to atomic24_t 61 - st %g7, [%g1] ! Clever: This releases the lock as well. 62 - #else 63 - ld [%g1], %g7 ! Load locked atomic24_t 64 - add %g7, %g2, %g2 ! Add in argument 65 - st %g2, [%g1] ! Store it back 66 - #endif 67 - wr %g3, 0x0, %psr ! Restore original PSR_PIL 68 - nop; nop; nop; ! Let the bits set 69 - jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h 70 - mov %g4, %o7 ! Restore %o7 71 - 72 - .globl ___atomic24_sub 73 - ___atomic24_sub: 74 - rd %psr, %g3 ! Keep the code small, old way was stupid 75 - nop; nop; nop; ! Let the bits set 76 - or %g3, PSR_PIL, %g7 ! Disable interrupts 77 - wr %g7, 0x0, %psr ! Set %psr 78 - nop; nop; nop; ! Let the bits set 79 - #ifdef CONFIG_SMP 80 - 1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP. 81 - orcc %g7, 0x0, %g0 ! Did we get it? 82 - bne 1b ! Nope... 83 - ld [%g1], %g7 ! Load locked atomic24_t 84 - sra %g7, 8, %g7 ! Get signed 24-bit integer 85 - sub %g7, %g2, %g2 ! Subtract argument 86 - sll %g2, 8, %g7 ! Transpose back to atomic24_t 87 - st %g7, [%g1] ! Clever: This releases the lock as well 88 - #else 89 - ld [%g1], %g7 ! Load locked atomic24_t 90 - sub %g7, %g2, %g2 ! Subtract argument 91 - st %g2, [%g1] ! Store it back 92 - #endif 93 - wr %g3, 0x0, %psr ! Restore original PSR_PIL 94 - nop; nop; nop; ! Let the bits set 95 - jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h 96 - mov %g4, %o7 ! Restore %o7 97 - 98 43 .globl __atomic_end 99 44 __atomic_end:

-6

arch/sparc/lib/ksyms.c

··· 62 62 extern void ___rw_read_try(void); 63 63 extern void ___rw_read_exit(void); 64 64 extern void ___rw_write_enter(void); 65 - extern void ___atomic24_add(void); 66 - extern void ___atomic24_sub(void); 67 65 68 66 /* Alias functions whose names begin with "." and export the aliases. 69 67 * The module references will be fixed up by module_frob_arch_sections. ··· 94 96 EXPORT_SYMBOL(___rw_read_exit); 95 97 EXPORT_SYMBOL(___rw_write_enter); 96 98 #endif 97 - 98 - /* Atomic operations. */ 99 - EXPORT_SYMBOL(___atomic24_add); 100 - EXPORT_SYMBOL(___atomic24_sub); 101 99 102 100 EXPORT_SYMBOL(__ashrdi3); 103 101 EXPORT_SYMBOL(__ashldi3);

+2 -2

drivers/tty/serial/apbuart.c

··· 577 577 return 0; 578 578 } 579 579 580 - static struct of_device_id __initdata apbuart_match[] = { 580 + static struct of_device_id apbuart_match[] = { 581 581 { 582 582 .name = "GAISLER_APBUART", 583 583 }, ··· 597 597 }; 598 598 599 599 600 - static int grlib_apbuart_configure(void) 600 + static int __init grlib_apbuart_configure(void) 601 601 { 602 602 struct device_node *np; 603 603 int line = 0;