tjh.dev / kernel
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drm/i915: add panel reset workaround

Ironlake requires that we clear the reset panel bit during power
sequences and restore it afterwards. Uncondtionally add code to do that
since it should be harmless on SNB+.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Jesse Barnes 37c6c9b0 ce171780

+16 -1
unified split
+16 -1
drivers/gpu/drm/i915/intel_dp.c
··· 765 765 return; 766 766 767 767 pp = I915_READ(PCH_PP_CONTROL); 768 + 769 + /* ILK workaround: disable reset around power sequence */ 770 + pp &= ~PANEL_POWER_RESET; 771 + I915_WRITE(PCH_PP_CONTROL, pp); 772 + POSTING_READ(PCH_PP_CONTROL); 773 + 768 774 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 769 775 I915_WRITE(PCH_PP_CONTROL, pp); 770 776 ··· 779 773 I915_READ(PCH_PP_STATUS)); 780 774 781 775 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); 776 + pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 782 777 I915_WRITE(PCH_PP_CONTROL, pp); 778 + POSTING_READ(PCH_PP_CONTROL); 783 779 } 784 780 785 781 static void ironlake_edp_panel_off (struct drm_device *dev) ··· 790 782 u32 pp; 791 783 792 784 pp = I915_READ(PCH_PP_CONTROL); 785 + 786 + /* ILK workaround: disable reset around power sequence */ 787 + pp &= ~PANEL_POWER_RESET; 788 + I915_WRITE(PCH_PP_CONTROL, pp); 789 + POSTING_READ(PCH_PP_CONTROL); 790 + 793 791 pp &= ~POWER_TARGET_ON; 794 792 I915_WRITE(PCH_PP_CONTROL, pp); 795 793 ··· 804 790 I915_READ(PCH_PP_STATUS)); 805 791 806 792 /* Make sure VDD is enabled so DP AUX will work */ 807 - pp |= EDP_FORCE_VDD; 793 + pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ 808 794 I915_WRITE(PCH_PP_CONTROL, pp); 795 + POSTING_READ(PCH_PP_CONTROL); 809 796 } 810 797 811 798 static void ironlake_edp_backlight_on (struct drm_device *dev)