commit 37aa4dac99418efa17329d98c2a0ed372ed9aa9e · tjh.dev/kernel

+1 -1

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

··· 30 30 clock-output-names: 31 31 - "xin24m" - crystal input - required, 32 32 - "ext_i2s" - external I2S clock - optional, 33 - - "ext_gmac" - external GMAC clock - optional 33 + - "rmii_clkin" - external EMAC clock - optional 34 34 35 35 Example: Clock controller node: 36 36

+1 -1

drivers/clk/Makefile

··· 43 43 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o 44 44 obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o 45 45 obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o 46 - obj-$(CONFIG_ARCH_TANGOX) += clk-tango4.o 46 + obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o 47 47 obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o 48 48 obj-$(CONFIG_ARCH_U300) += clk-u300.o 49 49 obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o

+1 -1

drivers/clk/clk-gpio.c

··· 289 289 290 290 num_parents = of_clk_get_parent_count(node); 291 291 if (num_parents < 0) 292 - return; 292 + num_parents = 0; 293 293 294 294 data = kzalloc(sizeof(*data), GFP_KERNEL); 295 295 if (!data)

+1 -1

drivers/clk/clk-scpi.c

··· 299 299 /* Add the virtual cpufreq device */ 300 300 cpufreq_dev = platform_device_register_simple("scpi-cpufreq", 301 301 -1, NULL, 0); 302 - if (!cpufreq_dev) 302 + if (IS_ERR(cpufreq_dev)) 303 303 pr_warn("unable to register cpufreq device"); 304 304 305 305 return 0;

+1 -1

drivers/clk/mvebu/dove-divider.c

··· 247 247 248 248 void __init dove_divider_clk_init(struct device_node *np) 249 249 { 250 - void *base; 250 + void __iomem *base; 251 251 252 252 base = of_iomap(np, 0); 253 253 if (WARN_ON(!base))

-1

drivers/clk/qcom/gcc-apq8084.c

··· 3587 3587 .val_bits = 32, 3588 3588 .max_register = 0x1fc0, 3589 3589 .fast_io = true, 3590 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3591 3590 }; 3592 3591 3593 3592 static const struct qcom_cc_desc gcc_apq8084_desc = {

-1

drivers/clk/qcom/gcc-ipq806x.c

··· 3005 3005 .val_bits = 32, 3006 3006 .max_register = 0x3e40, 3007 3007 .fast_io = true, 3008 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3009 3008 }; 3010 3009 3011 3010 static const struct qcom_cc_desc gcc_ipq806x_desc = {

-1

drivers/clk/qcom/gcc-msm8660.c

··· 2702 2702 .val_bits = 32, 2703 2703 .max_register = 0x363c, 2704 2704 .fast_io = true, 2705 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 2706 2705 }; 2707 2706 2708 2707 static const struct qcom_cc_desc gcc_msm8660_desc = {

-1

drivers/clk/qcom/gcc-msm8916.c

··· 3336 3336 .val_bits = 32, 3337 3337 .max_register = 0x80000, 3338 3338 .fast_io = true, 3339 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3340 3339 }; 3341 3340 3342 3341 static const struct qcom_cc_desc gcc_msm8916_desc = {

-2

drivers/clk/qcom/gcc-msm8960.c

··· 3468 3468 .val_bits = 32, 3469 3469 .max_register = 0x3660, 3470 3470 .fast_io = true, 3471 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3472 3471 }; 3473 3472 3474 3473 static const struct regmap_config gcc_apq8064_regmap_config = { ··· 3476 3477 .val_bits = 32, 3477 3478 .max_register = 0x3880, 3478 3479 .fast_io = true, 3479 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3480 3480 }; 3481 3481 3482 3482 static const struct qcom_cc_desc gcc_msm8960_desc = {

-1

drivers/clk/qcom/gcc-msm8974.c

··· 2680 2680 .val_bits = 32, 2681 2681 .max_register = 0x1fc0, 2682 2682 .fast_io = true, 2683 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 2684 2683 }; 2685 2684 2686 2685 static const struct qcom_cc_desc gcc_msm8974_desc = {

-1

drivers/clk/qcom/lcc-ipq806x.c

··· 419 419 .val_bits = 32, 420 420 .max_register = 0xfc, 421 421 .fast_io = true, 422 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 423 422 }; 424 423 425 424 static const struct qcom_cc_desc lcc_ipq806x_desc = {

-1

drivers/clk/qcom/lcc-msm8960.c

··· 524 524 .val_bits = 32, 525 525 .max_register = 0xfc, 526 526 .fast_io = true, 527 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 528 527 }; 529 528 530 529 static const struct qcom_cc_desc lcc_msm8960_desc = {

-1

drivers/clk/qcom/mmcc-apq8084.c

··· 3368 3368 .val_bits = 32, 3369 3369 .max_register = 0x5104, 3370 3370 .fast_io = true, 3371 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3372 3371 }; 3373 3372 3374 3373 static const struct qcom_cc_desc mmcc_apq8084_desc = {

-2

drivers/clk/qcom/mmcc-msm8960.c

··· 3029 3029 .val_bits = 32, 3030 3030 .max_register = 0x334, 3031 3031 .fast_io = true, 3032 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3033 3032 }; 3034 3033 3035 3034 static const struct regmap_config mmcc_apq8064_regmap_config = { ··· 3037 3038 .val_bits = 32, 3038 3039 .max_register = 0x350, 3039 3040 .fast_io = true, 3040 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 3041 3041 }; 3042 3042 3043 3043 static const struct qcom_cc_desc mmcc_msm8960_desc = {

-1

drivers/clk/qcom/mmcc-msm8974.c

··· 2594 2594 .val_bits = 32, 2595 2595 .max_register = 0x5104, 2596 2596 .fast_io = true, 2597 - .val_format_endian = REGMAP_ENDIAN_LITTLE, 2598 2597 }; 2599 2598 2600 2599 static const struct qcom_cc_desc mmcc_msm8974_desc = {

+13 -13

drivers/clk/rockchip/clk-rk3036.c

··· 133 133 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 134 134 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 135 135 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 136 - PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; 136 + PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" }; 137 137 PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" }; 138 138 139 139 static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = { ··· 224 224 RK2928_CLKGATE_CON(2), 2, GFLAGS), 225 225 226 226 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, 227 - RK2928_CLKSEL_CON(2), 4, 1, DFLAGS, 227 + RK2928_CLKSEL_CON(2), 4, 1, MFLAGS, 228 228 RK2928_CLKGATE_CON(1), 0, GFLAGS), 229 229 COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED, 230 - RK2928_CLKSEL_CON(2), 5, 1, DFLAGS, 230 + RK2928_CLKSEL_CON(2), 5, 1, MFLAGS, 231 231 RK2928_CLKGATE_CON(1), 1, GFLAGS), 232 232 COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED, 233 - RK2928_CLKSEL_CON(2), 6, 1, DFLAGS, 233 + RK2928_CLKSEL_CON(2), 6, 1, MFLAGS, 234 234 RK2928_CLKGATE_CON(2), 4, GFLAGS), 235 235 COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED, 236 - RK2928_CLKSEL_CON(2), 7, 1, DFLAGS, 236 + RK2928_CLKSEL_CON(2), 7, 1, MFLAGS, 237 237 RK2928_CLKGATE_CON(2), 5, GFLAGS), 238 238 239 239 MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, ··· 242 242 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 243 243 RK2928_CLKGATE_CON(1), 8, GFLAGS), 244 244 COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0, 245 - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 246 - RK2928_CLKGATE_CON(1), 8, GFLAGS), 245 + RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 246 + RK2928_CLKGATE_CON(1), 10, GFLAGS), 247 247 COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0, 248 - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 249 - RK2928_CLKGATE_CON(1), 8, GFLAGS), 248 + RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 249 + RK2928_CLKGATE_CON(1), 12, GFLAGS), 250 250 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 251 251 RK2928_CLKSEL_CON(17), 0, 252 252 RK2928_CLKGATE_CON(1), 9, GFLAGS, ··· 279 279 RK2928_CLKGATE_CON(3), 2, GFLAGS), 280 280 281 281 COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0, 282 - RK2928_CLKSEL_CON(12), 8, 2, DFLAGS, 282 + RK2928_CLKSEL_CON(12), 8, 2, MFLAGS, 283 283 RK2928_CLKGATE_CON(2), 11, GFLAGS), 284 284 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0, 285 285 RK2928_CLKSEL_CON(11), 0, 7, DFLAGS), 286 286 287 287 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 288 - RK2928_CLKSEL_CON(12), 10, 2, DFLAGS, 288 + RK2928_CLKSEL_CON(12), 10, 2, MFLAGS, 289 289 RK2928_CLKGATE_CON(2), 13, GFLAGS), 290 290 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 291 291 RK2928_CLKSEL_CON(11), 8, 7, DFLAGS), ··· 344 344 RK2928_CLKGATE_CON(10), 5, GFLAGS), 345 345 346 346 COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, 347 - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS), 347 + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), 348 348 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, 349 349 RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), 350 350 351 351 COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, 352 - RK2928_CLKSEL_CON(21), 9, 5, DFLAGS, 352 + RK2928_CLKSEL_CON(21), 4, 5, DFLAGS, 353 353 RK2928_CLKGATE_CON(2), 6, GFLAGS), 354 354 355 355 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,

+13 -13

drivers/clk/rockchip/clk-rk3368.c

··· 780 780 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS), 781 781 782 782 /* pclk_pd_alive gates */ 783 - GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 8, GFLAGS), 784 - GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 7, GFLAGS), 785 - GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 12, GFLAGS), 786 - GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 11, GFLAGS), 787 - GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 3, GFLAGS), 788 - GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 2, GFLAGS), 789 - GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 1, GFLAGS), 783 + GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS), 784 + GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS), 785 + GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS), 786 + GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS), 787 + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS), 788 + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS), 789 + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS), 790 790 791 791 /* 792 792 * pclk_vio gates ··· 796 796 GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS), 797 797 798 798 /* pclk_pd_pmu gates */ 799 - GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 0, GFLAGS), 800 - GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS), 801 - GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 3, GFLAGS), 802 - GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS), 803 - GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS), 804 - GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS), 799 + GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS), 800 + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS), 801 + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS), 802 + GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS), 803 + GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS), 804 + GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS), 805 805 806 806 /* timer gates */ 807 807 GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),

+4 -2

drivers/clk/tegra/clk-emc.c

··· 450 450 struct emc_timing *timing = tegra->timings + (i++); 451 451 452 452 err = load_one_timing_from_dt(tegra, timing, child); 453 - if (err) 453 + if (err) { 454 + of_node_put(child); 454 455 return err; 456 + } 455 457 456 458 timing->ram_code = ram_code; 457 459 } ··· 501 499 * fuses until the apbmisc driver is loaded. 502 500 */ 503 501 err = load_timings_from_dt(tegra, node, node_ram_code); 502 + of_node_put(node); 504 503 if (err) 505 504 return ERR_PTR(err); 506 - of_node_put(node); 507 505 break; 508 506 } 509 507

+1

drivers/clk/tegra/clk-id.h

··· 11 11 tegra_clk_afi, 12 12 tegra_clk_amx, 13 13 tegra_clk_amx1, 14 + tegra_clk_apb2ape, 14 15 tegra_clk_apbdma, 15 16 tegra_clk_apbif, 16 17 tegra_clk_ape,

+32 -18

drivers/clk/tegra/clk-pll.c

··· 86 86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 87 87 PLLE_SS_CNTL_SSC_BYP) 88 88 #define PLLE_SS_MAX_MASK 0x1ff 89 - #define PLLE_SS_MAX_VAL 0x25 89 + #define PLLE_SS_MAX_VAL_TEGRA114 0x25 90 + #define PLLE_SS_MAX_VAL_TEGRA210 0x21 90 91 #define PLLE_SS_INC_MASK (0xff << 16) 91 92 #define PLLE_SS_INC_VAL (0x1 << 16) 92 93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 93 - #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 94 + #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24) 95 + #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24) 94 96 #define PLLE_SS_COEFFICIENTS_MASK \ 95 97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 96 - #define PLLE_SS_COEFFICIENTS_VAL \ 97 - (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 98 + #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \ 99 + (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\ 100 + PLLE_SS_INCINTRV_VAL_TEGRA114) 101 + #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \ 102 + (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\ 103 + PLLE_SS_INCINTRV_VAL_TEGRA210) 98 104 99 105 #define PLLE_AUX_PLLP_SEL BIT(2) 100 106 #define PLLE_AUX_USE_LOCKDET BIT(3) ··· 886 880 static int clk_plle_enable(struct clk_hw *hw) 887 881 { 888 882 struct tegra_clk_pll *pll = to_clk_pll(hw); 889 - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 883 + unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 890 884 struct tegra_clk_pll_freq_table sel; 891 885 u32 val; 892 886 int err; ··· 1384 1378 u32 val; 1385 1379 int ret; 1386 1380 unsigned long flags = 0; 1387 - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1381 + unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 1388 1382 1389 1383 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1390 1384 return -EINVAL; ··· 1407 1401 val |= PLLE_MISC_IDDQ_SW_CTRL; 1408 1402 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1409 1403 val |= PLLE_MISC_PLLE_PTS; 1410 - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1404 + val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); 1411 1405 pll_writel_misc(val, pll); 1412 1406 udelay(5); 1413 1407 ··· 1434 1428 val = pll_readl(PLLE_SS_CTRL, pll); 1435 1429 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1436 1430 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1437 - val |= PLLE_SS_COEFFICIENTS_VAL; 1431 + val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114; 1438 1432 pll_writel(val, PLLE_SS_CTRL, pll); 1439 1433 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1440 1434 pll_writel(val, PLLE_SS_CTRL, pll); ··· 2018 2012 struct tegra_clk_pll *pll = to_clk_pll(hw); 2019 2013 struct tegra_clk_pll_freq_table sel; 2020 2014 u32 val; 2021 - int ret; 2015 + int ret = 0; 2022 2016 unsigned long flags = 0; 2023 - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 2017 + unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 2024 2018 2025 2019 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 2026 2020 return -EINVAL; ··· 2028 2022 if (pll->lock) 2029 2023 spin_lock_irqsave(pll->lock, flags); 2030 2024 2025 + val = pll_readl(pll->params->aux_reg, pll); 2026 + if (val & PLLE_AUX_SEQ_ENABLE) 2027 + goto out; 2028 + 2031 2029 val = pll_readl_base(pll); 2032 2030 val &= ~BIT(30); /* Disable lock override */ 2033 2031 pll_writel_base(val, pll); 2034 - 2035 - val = pll_readl(pll->params->aux_reg, pll); 2036 - val |= PLLE_AUX_ENABLE_SWCTL; 2037 - val &= ~PLLE_AUX_SEQ_ENABLE; 2038 - pll_writel(val, pll->params->aux_reg, pll); 2039 - udelay(1); 2040 2032 2041 2033 val = pll_readl_misc(pll); 2042 2034 val |= PLLE_MISC_LOCK_ENABLE; 2043 2035 val |= PLLE_MISC_IDDQ_SW_CTRL; 2044 2036 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 2045 2037 val |= PLLE_MISC_PLLE_PTS; 2046 - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 2038 + val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); 2047 2039 pll_writel_misc(val, pll); 2048 2040 udelay(5); 2049 2041 ··· 2071 2067 val = pll_readl(PLLE_SS_CTRL, pll); 2072 2068 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 2073 2069 val &= ~PLLE_SS_COEFFICIENTS_MASK; 2074 - val |= PLLE_SS_COEFFICIENTS_VAL; 2070 + val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210; 2075 2071 pll_writel(val, PLLE_SS_CTRL, pll); 2076 2072 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 2077 2073 pll_writel(val, PLLE_SS_CTRL, pll); ··· 2108 2104 if (pll->lock) 2109 2105 spin_lock_irqsave(pll->lock, flags); 2110 2106 2107 + /* If PLLE HW sequencer is enabled, SW should not disable PLLE */ 2108 + val = pll_readl(pll->params->aux_reg, pll); 2109 + if (val & PLLE_AUX_SEQ_ENABLE) 2110 + goto out; 2111 + 2111 2112 val = pll_readl_base(pll); 2112 2113 val &= ~PLLE_BASE_ENABLE; 2113 2114 pll_writel_base(val, pll); 2115 + 2116 + val = pll_readl(pll->params->aux_reg, pll); 2117 + val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL; 2118 + pll_writel(val, pll->params->aux_reg, pll); 2114 2119 2115 2120 val = pll_readl_misc(pll); 2116 2121 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 2117 2122 pll_writel_misc(val, pll); 2118 2123 udelay(1); 2119 2124 2125 + out: 2120 2126 if (pll->lock) 2121 2127 spin_unlock_irqrestore(pll->lock, flags); 2122 2128 }

+3 -2

drivers/clk/tegra/clk-tegra-periph.c

··· 773 773 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), 774 774 XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8), 775 775 MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb), 776 - MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc), 776 + MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc), 777 777 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec), 778 778 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), 779 779 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), ··· 782 782 NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock), 783 783 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), 784 784 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), 785 - MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c), 785 + I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c), 786 786 MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif), 787 787 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape), 788 788 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb), ··· 829 829 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0), 830 830 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0), 831 831 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0), 832 + GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0), 832 833 }; 833 834 834 835 static struct tegra_periph_init_data div_clks[] = {

+3 -3

drivers/clk/tegra/clk-tegra-super-gen4.c

··· 67 67 "pll_p", "pll_p_out4", "unused", 68 68 "unused", "pll_x", "pll_x_out0" }; 69 69 70 - const struct tegra_super_gen_info tegra_super_gen_info_gen4 = { 70 + static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = { 71 71 .gen = gen4, 72 72 .sclk_parents = sclk_parents, 73 73 .cclk_g_parents = cclk_g_parents, ··· 93 93 "unused", "unused", "unused", "unused", 94 94 "dfllCPU_out" }; 95 95 96 - const struct tegra_super_gen_info tegra_super_gen_info_gen5 = { 96 + static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = { 97 97 .gen = gen5, 98 98 .sclk_parents = sclk_parents_gen5, 99 99 .cclk_g_parents = cclk_g_parents_gen5, ··· 171 171 *dt_clk = clk; 172 172 } 173 173 174 - void __init tegra_super_clk_init(void __iomem *clk_base, 174 + static void __init tegra_super_clk_init(void __iomem *clk_base, 175 175 void __iomem *pmc_base, 176 176 struct tegra_clk *tegra_clks, 177 177 struct tegra_clk_pll_params *params,

+60 -72

drivers/clk/tegra/clk-tegra210.c

··· 59 59 #define PLLC3_MISC3 0x50c 60 60 61 61 #define PLLM_BASE 0x90 62 - #define PLLM_MISC0 0x9c 63 62 #define PLLM_MISC1 0x98 63 + #define PLLM_MISC2 0x9c 64 64 #define PLLP_BASE 0xa0 65 65 #define PLLP_MISC0 0xac 66 66 #define PLLP_MISC1 0x680 ··· 99 99 #define PLLC4_MISC0 0x5a8 100 100 #define PLLC4_OUT 0x5e4 101 101 #define PLLMB_BASE 0x5e8 102 - #define PLLMB_MISC0 0x5ec 102 + #define PLLMB_MISC1 0x5ec 103 103 #define PLLA1_BASE 0x6a4 104 104 #define PLLA1_MISC0 0x6a8 105 105 #define PLLA1_MISC1 0x6ac ··· 243 243 }; 244 244 245 245 static const char *mux_pllmcp_clkm[] = { 246 - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", 246 + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", 247 + "pll_p", 247 248 }; 248 249 #define mux_pllmcp_clkm_idx NULL 249 250 ··· 368 367 /* PLLMB */ 369 368 #define PLLMB_BASE_LOCK (1 << 27) 370 369 371 - #define PLLMB_MISC0_LOCK_OVERRIDE (1 << 18) 372 - #define PLLMB_MISC0_IDDQ (1 << 17) 373 - #define PLLMB_MISC0_LOCK_ENABLE (1 << 16) 370 + #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) 371 + #define PLLMB_MISC1_IDDQ (1 << 17) 372 + #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) 374 373 375 - #define PLLMB_MISC0_DEFAULT_VALUE 0x00030000 376 - #define PLLMB_MISC0_WRITE_MASK 0x0007ffff 374 + #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 375 + #define PLLMB_MISC1_WRITE_MASK 0x0007ffff 377 376 378 377 /* PLLP */ 379 378 #define PLLP_BASE_OVERRIDE (1 << 28) ··· 458 457 PLLCX_MISC3_WRITE_MASK); 459 458 } 460 459 461 - void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx) 460 + static void tegra210_pllcx_set_defaults(const char *name, 461 + struct tegra_clk_pll *pllcx) 462 462 { 463 463 pllcx->params->defaults_set = true; 464 464 ··· 484 482 udelay(1); 485 483 } 486 484 487 - void _pllc_set_defaults(struct tegra_clk_pll *pllcx) 485 + static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) 488 486 { 489 487 tegra210_pllcx_set_defaults("PLL_C", pllcx); 490 488 } 491 489 492 - void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) 490 + static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) 493 491 { 494 492 tegra210_pllcx_set_defaults("PLL_C2", pllcx); 495 493 } 496 494 497 - void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) 495 + static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) 498 496 { 499 497 tegra210_pllcx_set_defaults("PLL_C3", pllcx); 500 498 } 501 499 502 - void _plla1_set_defaults(struct tegra_clk_pll *pllcx) 500 + static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) 503 501 { 504 502 tegra210_pllcx_set_defaults("PLL_A1", pllcx); 505 503 } ··· 509 507 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. 510 508 * Fractional SDM is allowed to provide exact audio rates. 511 509 */ 512 - void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) 510 + static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) 513 511 { 514 512 u32 mask; 515 513 u32 val = readl_relaxed(clk_base + plla->params->base_reg); ··· 561 559 * PLLD 562 560 * PLL with fractional SDM. 563 561 */ 564 - void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) 562 + static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) 565 563 { 566 564 u32 val; 567 565 u32 mask = 0xffff; ··· 700 698 udelay(1); 701 699 } 702 700 703 - void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) 701 + static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) 704 702 { 705 703 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, 706 704 PLLD2_MISC1_CFG_DEFAULT_VALUE, ··· 708 706 PLLD2_MISC3_CTRL2_DEFAULT_VALUE); 709 707 } 710 708 711 - void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) 709 + static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) 712 710 { 713 711 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, 714 712 PLLDP_MISC1_CFG_DEFAULT_VALUE, ··· 721 719 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. 722 720 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. 723 721 */ 724 - void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) 722 + static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) 725 723 { 726 724 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); 727 725 } ··· 730 728 * PLLRE 731 729 * VCO is exposed to the clock tree directly along with post-divider output 732 730 */ 733 - void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) 731 + static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) 734 732 { 735 733 u32 mask; 736 734 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); ··· 782 780 { 783 781 unsigned long input_rate; 784 782 785 - if (!IS_ERR_OR_NULL(hw->clk)) { 783 + /* cf rate */ 784 + if (!IS_ERR_OR_NULL(hw->clk)) 786 785 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 787 - /* cf rate */ 788 - input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); 789 - } else { 786 + else 790 787 input_rate = 38400000; 791 - } 788 + 789 + input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); 792 790 793 791 switch (input_rate) { 794 792 case 12000000: ··· 843 841 PLLX_MISC5_WRITE_MASK); 844 842 } 845 843 846 - void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) 844 + static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) 847 845 { 848 846 u32 val; 849 847 u32 step_a, step_b; ··· 903 901 } 904 902 905 903 /* PLLMB */ 906 - void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) 904 + static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) 907 905 { 908 906 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); 909 907 ··· 916 914 * PLL is ON: check if defaults already set, then set those 917 915 * that can be updated in flight. 918 916 */ 919 - val = PLLMB_MISC0_DEFAULT_VALUE & (~PLLMB_MISC0_IDDQ); 920 - mask = PLLMB_MISC0_LOCK_ENABLE | PLLMB_MISC0_LOCK_OVERRIDE; 917 + val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); 918 + mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; 921 919 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, 922 - ~mask & PLLMB_MISC0_WRITE_MASK); 920 + ~mask & PLLMB_MISC1_WRITE_MASK); 923 921 924 922 /* Enable lock detect */ 925 923 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); 926 924 val &= ~mask; 927 - val |= PLLMB_MISC0_DEFAULT_VALUE & mask; 925 + val |= PLLMB_MISC1_DEFAULT_VALUE & mask; 928 926 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); 929 927 udelay(1); 930 928 ··· 932 930 } 933 931 934 932 /* set IDDQ, enable lock detect */ 935 - writel_relaxed(PLLMB_MISC0_DEFAULT_VALUE, 933 + writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, 936 934 clk_base + pllmb->params->ext_misc_reg[0]); 937 935 udelay(1); 938 936 } ··· 962 960 ~mask & PLLP_MISC1_WRITE_MASK); 963 961 } 964 962 965 - void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) 963 + static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) 966 964 { 967 965 u32 mask; 968 966 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); ··· 1024 1022 ~mask & PLLU_MISC1_WRITE_MASK); 1025 1023 } 1026 1024 1027 - void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) 1025 + static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) 1028 1026 { 1029 1027 u32 val = readl_relaxed(clk_base + pllu->params->base_reg); 1030 1028 ··· 1214 1212 cfg->m *= PLL_SDM_COEFF; 1215 1213 } 1216 1214 1217 - unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, 1218 - unsigned long parent_rate) 1215 + static unsigned long 1216 + tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, 1217 + unsigned long parent_rate) 1219 1218 { 1220 1219 unsigned long vco_min = params->vco_min; 1221 1220 ··· 1389 1386 .mdiv_default = 3, 1390 1387 .div_nmp = &pllc_nmp, 1391 1388 .freq_table = pll_cx_freq_table, 1392 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1389 + .flags = TEGRA_PLL_USE_LOCK, 1393 1390 .set_defaults = _pllc_set_defaults, 1394 1391 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1395 1392 }; ··· 1428 1425 .ext_misc_reg[2] = PLLC2_MISC2, 1429 1426 .ext_misc_reg[3] = PLLC2_MISC3, 1430 1427 .freq_table = pll_cx_freq_table, 1431 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1428 + .flags = TEGRA_PLL_USE_LOCK, 1432 1429 .set_defaults = _pllc2_set_defaults, 1433 1430 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1434 1431 }; ··· 1458 1455 .ext_misc_reg[2] = PLLC3_MISC2, 1459 1456 .ext_misc_reg[3] = PLLC3_MISC3, 1460 1457 .freq_table = pll_cx_freq_table, 1461 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1458 + .flags = TEGRA_PLL_USE_LOCK, 1462 1459 .set_defaults = _pllc3_set_defaults, 1463 1460 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1464 1461 }; ··· 1508 1505 .base_reg = PLLC4_BASE, 1509 1506 .misc_reg = PLLC4_MISC0, 1510 1507 .lock_mask = PLL_BASE_LOCK, 1511 - .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 1512 1508 .lock_delay = 300, 1513 1509 .max_p = PLL_QLIN_PDIV_MAX, 1514 1510 .ext_misc_reg[0] = PLLC4_MISC0, ··· 1519 1517 .div_nmp = &pllss_nmp, 1520 1518 .freq_table = pll_c4_vco_freq_table, 1521 1519 .set_defaults = tegra210_pllc4_set_defaults, 1522 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | 1523 - TEGRA_PLL_VCO_OUT, 1520 + .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1524 1521 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1525 1522 }; 1526 1523 ··· 1560 1559 .vco_min = 800000000, 1561 1560 .vco_max = 1866000000, 1562 1561 .base_reg = PLLM_BASE, 1563 - .misc_reg = PLLM_MISC1, 1562 + .misc_reg = PLLM_MISC2, 1564 1563 .lock_mask = PLL_BASE_LOCK, 1565 1564 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, 1566 1565 .lock_delay = 300, 1567 - .iddq_reg = PLLM_MISC0, 1566 + .iddq_reg = PLLM_MISC2, 1568 1567 .iddq_bit_idx = PLLM_IDDQ_BIT, 1569 1568 .max_p = PLL_QLIN_PDIV_MAX, 1570 - .ext_misc_reg[0] = PLLM_MISC0, 1571 - .ext_misc_reg[0] = PLLM_MISC1, 1569 + .ext_misc_reg[0] = PLLM_MISC2, 1570 + .ext_misc_reg[1] = PLLM_MISC1, 1572 1571 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1573 1572 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1574 1573 .div_nmp = &pllm_nmp, ··· 1587 1586 .vco_min = 800000000, 1588 1587 .vco_max = 1866000000, 1589 1588 .base_reg = PLLMB_BASE, 1590 - .misc_reg = PLLMB_MISC0, 1589 + .misc_reg = PLLMB_MISC1, 1591 1590 .lock_mask = PLL_BASE_LOCK, 1592 - .lock_enable_bit_idx = PLLMB_MISC_LOCK_ENABLE, 1593 1591 .lock_delay = 300, 1594 - .iddq_reg = PLLMB_MISC0, 1592 + .iddq_reg = PLLMB_MISC1, 1595 1593 .iddq_bit_idx = PLLMB_IDDQ_BIT, 1596 1594 .max_p = PLL_QLIN_PDIV_MAX, 1597 - .ext_misc_reg[0] = PLLMB_MISC0, 1595 + .ext_misc_reg[0] = PLLMB_MISC1, 1598 1596 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1599 1597 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1600 1598 .div_nmp = &pllm_nmp, 1601 1599 .freq_table = pll_m_freq_table, 1602 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1600 + .flags = TEGRA_PLL_USE_LOCK, 1603 1601 .set_defaults = tegra210_pllmb_set_defaults, 1604 1602 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1605 1603 }; ··· 1671 1671 .base_reg = PLLRE_BASE, 1672 1672 .misc_reg = PLLRE_MISC0, 1673 1673 .lock_mask = PLLRE_MISC_LOCK, 1674 - .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 1675 1674 .lock_delay = 300, 1676 1675 .max_p = PLL_QLIN_PDIV_MAX, 1677 1676 .ext_misc_reg[0] = PLLRE_MISC0, ··· 1680 1681 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1681 1682 .div_nmp = &pllre_nmp, 1682 1683 .freq_table = pll_re_vco_freq_table, 1683 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | 1684 - TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT, 1684 + .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, 1685 1685 .set_defaults = tegra210_pllre_set_defaults, 1686 1686 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1687 1687 }; ··· 1710 1712 .base_reg = PLLP_BASE, 1711 1713 .misc_reg = PLLP_MISC0, 1712 1714 .lock_mask = PLL_BASE_LOCK, 1713 - .lock_enable_bit_idx = PLLP_MISC_LOCK_ENABLE, 1714 1715 .lock_delay = 300, 1715 1716 .iddq_reg = PLLP_MISC0, 1716 1717 .iddq_bit_idx = PLLXP_IDDQ_BIT, ··· 1718 1721 .div_nmp = &pllp_nmp, 1719 1722 .freq_table = pll_p_freq_table, 1720 1723 .fixed_rate = 408000000, 1721 - .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | 1722 - TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT, 1724 + .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1723 1725 .set_defaults = tegra210_pllp_set_defaults, 1724 1726 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1725 1727 }; ··· 1746 1750 .ext_misc_reg[2] = PLLA1_MISC2, 1747 1751 .ext_misc_reg[3] = PLLA1_MISC3, 1748 1752 .freq_table = pll_cx_freq_table, 1749 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1753 + .flags = TEGRA_PLL_USE_LOCK, 1750 1754 .set_defaults = _plla1_set_defaults, 1751 1755 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1752 1756 }; ··· 1783 1787 .base_reg = PLLA_BASE, 1784 1788 .misc_reg = PLLA_MISC0, 1785 1789 .lock_mask = PLL_BASE_LOCK, 1786 - .lock_enable_bit_idx = PLLA_MISC_LOCK_ENABLE, 1787 1790 .lock_delay = 300, 1788 1791 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1789 1792 .pdiv_tohw = pll_qlin_pdiv_to_hw, ··· 1797 1802 .ext_misc_reg[1] = PLLA_MISC1, 1798 1803 .ext_misc_reg[2] = PLLA_MISC2, 1799 1804 .freq_table = pll_a_freq_table, 1800 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW | 1801 - TEGRA_PLL_HAS_LOCK_ENABLE, 1805 + .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, 1802 1806 .set_defaults = tegra210_plla_set_defaults, 1803 1807 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1804 1808 .set_gain = tegra210_clk_pll_set_gain, ··· 1830 1836 .base_reg = PLLD_BASE, 1831 1837 .misc_reg = PLLD_MISC0, 1832 1838 .lock_mask = PLL_BASE_LOCK, 1833 - .lock_enable_bit_idx = PLLD_MISC_LOCK_ENABLE, 1834 1839 .lock_delay = 1000, 1835 1840 .iddq_reg = PLLD_MISC0, 1836 1841 .iddq_bit_idx = PLLD_IDDQ_BIT, ··· 1843 1850 .ext_misc_reg[0] = PLLD_MISC0, 1844 1851 .ext_misc_reg[1] = PLLD_MISC1, 1845 1852 .freq_table = pll_d_freq_table, 1846 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1853 + .flags = TEGRA_PLL_USE_LOCK, 1847 1854 .mdiv_default = 1, 1848 1855 .set_defaults = tegra210_plld_set_defaults, 1849 1856 .calc_rate = tegra210_pll_fixed_mdiv_cfg, ··· 1869 1876 .base_reg = PLLD2_BASE, 1870 1877 .misc_reg = PLLD2_MISC0, 1871 1878 .lock_mask = PLL_BASE_LOCK, 1872 - .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 1873 1879 .lock_delay = 300, 1874 1880 .iddq_reg = PLLD2_BASE, 1875 1881 .iddq_bit_idx = PLLSS_IDDQ_BIT, ··· 1889 1897 .mdiv_default = 1, 1890 1898 .freq_table = tegra210_pll_d2_freq_table, 1891 1899 .set_defaults = tegra210_plld2_set_defaults, 1892 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1900 + .flags = TEGRA_PLL_USE_LOCK, 1893 1901 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1894 1902 .set_gain = tegra210_clk_pll_set_gain, 1895 1903 .adjust_vco = tegra210_clk_adjust_vco_min, ··· 1912 1920 .base_reg = PLLDP_BASE, 1913 1921 .misc_reg = PLLDP_MISC, 1914 1922 .lock_mask = PLL_BASE_LOCK, 1915 - .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 1916 1923 .lock_delay = 300, 1917 1924 .iddq_reg = PLLDP_BASE, 1918 1925 .iddq_bit_idx = PLLSS_IDDQ_BIT, ··· 1932 1941 .mdiv_default = 1, 1933 1942 .freq_table = pll_dp_freq_table, 1934 1943 .set_defaults = tegra210_plldp_set_defaults, 1935 - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1944 + .flags = TEGRA_PLL_USE_LOCK, 1936 1945 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1937 1946 .set_gain = tegra210_clk_pll_set_gain, 1938 1947 .adjust_vco = tegra210_clk_adjust_vco_min, ··· 1964 1973 .base_reg = PLLU_BASE, 1965 1974 .misc_reg = PLLU_MISC0, 1966 1975 .lock_mask = PLL_BASE_LOCK, 1967 - .lock_enable_bit_idx = PLLU_MISC_LOCK_ENABLE, 1968 1976 .lock_delay = 1000, 1969 1977 .iddq_reg = PLLU_MISC0, 1970 1978 .iddq_bit_idx = PLLU_IDDQ_BIT, ··· 1973 1983 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1974 1984 .div_nmp = &pllu_nmp, 1975 1985 .freq_table = pll_u_freq_table, 1976 - .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | 1977 - TEGRA_PLL_VCO_OUT, 1986 + .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1978 1987 .set_defaults = tegra210_pllu_set_defaults, 1979 1988 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1980 1989 }; ··· 2207 2218 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, 2208 2219 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, 2209 2220 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, 2221 + [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, 2210 2222 }; 2211 2223 2212 2224 static struct tegra_devclk devclks[] __initdata = { ··· 2509 2519 2510 2520 /* PLLU_VCO */ 2511 2521 val = readl(clk_base + pll_u_vco_params.base_reg); 2512 - val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 2522 + val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */ 2513 2523 writel(val, clk_base + pll_u_vco_params.base_reg); 2514 2524 2515 2525 clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc, ··· 2728 2738 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, 2729 2739 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, 2730 2740 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, 2731 - { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, 2732 - { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, 2733 2741 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2734 2742 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, 2735 2743 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },

+3

drivers/clk/versatile/clk-icst.c

··· 78 78 ret = regmap_read(icst->map, icst->vcoreg_off, &val); 79 79 if (ret) 80 80 return ret; 81 + 82 + /* Mask the 18 bits used by the VCO */ 83 + val &= ~0x7ffff; 81 84 val |= vco.v | (vco.r << 9) | (vco.s << 16); 82 85 83 86 /* This magic unlocks the VCO so it can be controlled */

+1 -1

include/dt-bindings/clock/tegra210-car.h

··· 126 126 /* 104 */ 127 127 /* 105 */ 128 128 #define TEGRA210_CLK_D_AUDIO 106 129 - /* 107 ( affects abp -> ape) */ 129 + #define TEGRA210_CLK_APB2APE 107 130 130 /* 108 */ 131 131 /* 109 */ 132 132 /* 110 */