Merge tag 'rtc-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

+70

Documentation/devicetree/bindings/rtc/adi,max31335.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rtc/adi,max31335.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Analog Devices MAX31335 RTC 8 + 9 + maintainers: 10 + - Antoniu Miclaus <antoniu.miclaus@analog.com> 11 + 12 + description: 13 + Analog Devices MAX31335 I2C RTC ±2ppm Automotive Real-Time Clock with 14 + Integrated MEMS Resonator. 15 + 16 + allOf: 17 + - $ref: rtc.yaml# 18 + 19 + properties: 20 + compatible: 21 + const: adi,max31335 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupts: 27 + maxItems: 1 28 + 29 + "#clock-cells": 30 + description: 31 + RTC can be used as a clock source through its clock output pin. 32 + const: 0 33 + 34 + adi,tc-diode: 35 + description: 36 + Select the diode configuration for the trickle charger. 37 + schottky - Schottky diode in series. 38 + standard+schottky - standard diode + Schottky diode in series. 39 + enum: [schottky, standard+schottky] 40 + 41 + trickle-resistor-ohms: 42 + description: 43 + Selected resistor for trickle charger. Should be specified if trickle 44 + charger should be enabled. 45 + enum: [3000, 6000, 11000] 46 + 47 + required: 48 + - compatible 49 + - reg 50 + 51 + unevaluatedProperties: false 52 + 53 + examples: 54 + - | 55 + #include <dt-bindings/interrupt-controller/irq.h> 56 + i2c { 57 + #address-cells = <1>; 58 + #size-cells = <0>; 59 + 60 + rtc@68 { 61 + compatible = "adi,max31335"; 62 + reg = <0x68>; 63 + pinctrl-0 = <&rtc_nint_pins>; 64 + interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>; 65 + aux-voltage-chargeable = <1>; 66 + trickle-resistor-ohms = <6000>; 67 + adi,tc-diode = "schottky"; 68 + }; 69 + }; 70 + ...

+2

Documentation/devicetree/bindings/rtc/epson,rx8900.yaml

··· 29 29 30 30 trickle-diode-disable: true 31 31 32 + wakeup-source: true 33 + 32 34 required: 33 35 - compatible 34 36 - reg

+48

Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rtc/nuvoton,ma35d1-rtc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Nuvoton MA35D1 Real Time Clock 8 + 9 + maintainers: 10 + - Min-Jen Chen <mjchen@nuvoton.com> 11 + 12 + allOf: 13 + - $ref: rtc.yaml# 14 + 15 + properties: 16 + compatible: 17 + enum: 18 + - nuvoton,ma35d1-rtc 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + interrupts: 24 + maxItems: 1 25 + 26 + clocks: 27 + maxItems: 1 28 + 29 + required: 30 + - compatible 31 + - reg 32 + - interrupts 33 + - clocks 34 + 35 + unevaluatedProperties: false 36 + 37 + examples: 38 + - | 39 + #include <dt-bindings/interrupt-controller/arm-gic.h> 40 + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 41 + rtc@40410000 { 42 + compatible = "nuvoton,ma35d1-rtc"; 43 + reg = <0x40410000 0x200>; 44 + interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 45 + clocks = <&clk RTC_GATE>; 46 + }; 47 + 48 + ...

+18 -18

Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml

··· 61 61 62 62 examples: 63 63 - | 64 + #include <dt-bindings/interrupt-controller/irq.h> 64 65 #include <dt-bindings/spmi/spmi.h> 65 - spmi_bus: spmi@c440000 { 66 - reg = <0x0c440000 0x1100>; 67 - #address-cells = <2>; 68 - #size-cells = <0>; 69 - pmicintc: pmic@0 { 70 - reg = <0x0 SPMI_USID>; 71 - compatible = "qcom,pm8921"; 72 - interrupts = <104 8>; 73 - #interrupt-cells = <2>; 74 - interrupt-controller; 75 - #address-cells = <1>; 66 + 67 + spmi { 68 + #address-cells = <2>; 76 69 #size-cells = <0>; 77 70 78 - pm8921_rtc: rtc@11d { 79 - compatible = "qcom,pm8921-rtc"; 80 - reg = <0x11d>; 81 - interrupts = <0x27 0>; 82 - nvmem-cells = <&rtc_offset>; 83 - nvmem-cell-names = "offset"; 71 + pmic@0 { 72 + compatible = "qcom,pm8941", "qcom,spmi-pmic"; 73 + reg = <0x0 SPMI_USID>; 74 + #address-cells = <1>; 75 + #size-cells = <0>; 76 + 77 + rtc@6000 { 78 + compatible = "qcom,pm8941-rtc"; 79 + reg = <0x6000>, <0x6100>; 80 + reg-names = "rtc", "alarm"; 81 + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; 82 + nvmem-cells = <&rtc_offset>; 83 + nvmem-cell-names = "offset"; 84 + }; 84 85 }; 85 - }; 86 86 }; 87 87 ...

+8 -1

MAINTAINERS

··· 13126 13126 F: Documentation/hwmon/max31827.rst 13127 13127 F: drivers/hwmon/max31827.c 13128 13128 13129 + MAX31335 RTC DRIVER 13130 + M: Antoniu Miclaus <antoniu.miclaus@analog.com> 13131 + L: linux-rtc@vger.kernel.org 13132 + S: Supported 13133 + W: https://ez.analog.com/linux-software-drivers 13134 + F: Documentation/devicetree/bindings/rtc/adi,max31335.yaml 13135 + F: drivers/rtc/rtc-max31335.c 13136 + 13129 13137 MAX6650 HARDWARE MONITOR AND FAN CONTROLLER DRIVER 13130 13138 L: linux-hwmon@vger.kernel.org 13131 13139 S: Orphan ··· 18459 18451 X: kernel/rcu/srcu*.c 18460 18452 18461 18453 REAL TIME CLOCK (RTC) SUBSYSTEM 18462 - M: Alessandro Zummo <a.zummo@towertech.it> 18463 18454 M: Alexandre Belloni <alexandre.belloni@bootlin.com> 18464 18455 L: linux-rtc@vger.kernel.org 18465 18456 S: Maintained

+1 -1

arch/alpha/kernel/rtc.c

··· 80 80 static int 81 81 alpha_rtc_read_time(struct device *dev, struct rtc_time *tm) 82 82 { 83 - int ret = mc146818_get_time(tm); 83 + int ret = mc146818_get_time(tm, 10); 84 84 85 85 if (ret < 0) { 86 86 dev_err_ratelimited(dev, "unable to read current time\n");

+1 -1

arch/x86/kernel/hpet.c

··· 1438 1438 memset(&curr_time, 0, sizeof(struct rtc_time)); 1439 1439 1440 1440 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) { 1441 - if (unlikely(mc146818_get_time(&curr_time) < 0)) { 1441 + if (unlikely(mc146818_get_time(&curr_time, 10) < 0)) { 1442 1442 pr_err_ratelimited("unable to read current time from RTC\n"); 1443 1443 return IRQ_HANDLED; 1444 1444 }

+1 -1

arch/x86/kernel/rtc.c

··· 67 67 return; 68 68 } 69 69 70 - if (mc146818_get_time(&tm)) { 70 + if (mc146818_get_time(&tm, 1000)) { 71 71 pr_err("Unable to read current time from RTC\n"); 72 72 now->tv_sec = now->tv_nsec = 0; 73 73 return;

+1 -1

drivers/base/power/trace.c

··· 120 120 struct rtc_time time; 121 121 unsigned int val; 122 122 123 - if (mc146818_get_time(&time) < 0) { 123 + if (mc146818_get_time(&time, 1000) < 0) { 124 124 pr_err("Unable to read current time from RTC\n"); 125 125 return 0; 126 126 }

+37

drivers/rtc/Kconfig

··· 373 373 This driver can also be built as a module. If so, the module 374 374 will be called rtc-max8997. 375 375 376 + config RTC_DRV_MAX31335 377 + tristate "Analog Devices MAX31335" 378 + depends on I2C 379 + depends on COMMON_CLK 380 + depends on HWMON || HWMON=n 381 + select REGMAP_I2C 382 + help 383 + If you say yes here you get support for the Analog Devices 384 + MAX31335. 385 + 386 + This driver can also be built as a module. If so, the module 387 + will be called rtc-max31335. 388 + 376 389 config RTC_DRV_MAX77686 377 390 tristate "Maxim MAX77686" 378 391 depends on MFD_MAX77686 || MFD_MAX77620 || MFD_MAX77714 || COMPILE_TEST ··· 590 577 TI Power Management IC TPS6586X supports RTC functionality 591 578 along with alarm. This driver supports the RTC driver for 592 579 the TPS6586X RTC module. 580 + 581 + config RTC_DRV_TPS6594 582 + tristate "TI TPS6594 RTC driver" 583 + depends on MFD_TPS6594 584 + default MFD_TPS6594 585 + help 586 + TI Power Management IC TPS6594 supports RTC functionality 587 + along with alarm. This driver supports the RTC driver for 588 + the TPS6594 RTC module. 589 + 590 + This driver can also be built as a module. If so, the module 591 + will be called rtc-tps6594. 593 592 594 593 config RTC_DRV_TPS65910 595 594 tristate "TI TPS65910 RTC driver" ··· 1730 1705 tristate "NXP RTC for LPC178x/18xx/408x/43xx" 1731 1706 depends on ARCH_LPC18XX || COMPILE_TEST 1732 1707 depends on OF && HAS_IOMEM 1708 + depends on COMMON_CLK 1733 1709 help 1734 1710 This enables support for the NXP RTC found which can be found on 1735 1711 NXP LPC178x/18xx/408x/43xx devices. ··· 1955 1929 1956 1930 This driver can also be built as a module, if so, the module 1957 1931 will be called "rtc-ti-k3". 1932 + 1933 + config RTC_DRV_MA35D1 1934 + tristate "Nuvoton MA35D1 RTC" 1935 + depends on ARCH_MA35 || COMPILE_TEST 1936 + select REGMAP_MMIO 1937 + help 1938 + If you say yes here you get support for the Nuvoton MA35D1 1939 + On-Chip Real Time Clock. 1940 + 1941 + This driver can also be built as a module, if so, the module 1942 + will be called "rtc-ma35d1". 1958 1943 1959 1944 comment "HID Sensor RTC drivers" 1960 1945

+3

drivers/rtc/Makefile

··· 88 88 obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o 89 89 obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o 90 90 obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o 91 + obj-$(CONFIG_RTC_DRV_MA35D1) += rtc-ma35d1.o 92 + obj-$(CONFIG_RTC_DRV_MAX31335) += rtc-max31335.o 91 93 obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o 92 94 obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o 93 95 obj-$(CONFIG_RTC_DRV_MAX6916) += rtc-max6916.o ··· 178 176 obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o 179 177 obj-$(CONFIG_RTC_DRV_TI_K3) += rtc-ti-k3.o 180 178 obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o 179 + obj-$(CONFIG_RTC_DRV_TPS6594) += rtc-tps6594.o 181 180 obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o 182 181 obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o 183 182 obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o

+1 -1

drivers/rtc/class.c

··· 256 256 of_id = of_alias_get_id(dev->parent->of_node, "rtc"); 257 257 258 258 if (of_id >= 0) { 259 - id = ida_simple_get(&rtc_ida, of_id, of_id + 1, GFP_KERNEL); 259 + id = ida_alloc_range(&rtc_ida, of_id, of_id, GFP_KERNEL); 260 260 if (id < 0) 261 261 dev_warn(dev, "/aliases ID %d not available\n", of_id); 262 262 }

+2 -2

drivers/rtc/rtc-ac100.c

··· 99 99 struct clk_hw_onecell_data *clk_data; 100 100 }; 101 101 102 - /** 102 + /* 103 103 * Clock controls for 3 clock output pins 104 104 */ 105 105 ··· 378 378 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk); 379 379 } 380 380 381 - /** 381 + /* 382 382 * RTC related bits 383 383 */ 384 384 static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)

+17 -11

drivers/rtc/rtc-cmos.c

··· 231 231 if (!pm_trace_rtc_valid()) 232 232 return -EIO; 233 233 234 - ret = mc146818_get_time(t); 234 + ret = mc146818_get_time(t, 1000); 235 235 if (ret < 0) { 236 236 dev_err_ratelimited(dev, "unable to read current time\n"); 237 237 return ret; ··· 292 292 293 293 /* This not only a rtc_op, but also called directly */ 294 294 if (!is_valid_irq(cmos->irq)) 295 - return -EIO; 295 + return -ETIMEDOUT; 296 296 297 297 /* Basic alarms only support hour, minute, and seconds fields. 298 298 * Some also support day and month, for alarms up to a year in ··· 307 307 * 308 308 * Use the mc146818_avoid_UIP() function to avoid this. 309 309 */ 310 - if (!mc146818_avoid_UIP(cmos_read_alarm_callback, &p)) 310 + if (!mc146818_avoid_UIP(cmos_read_alarm_callback, 10, &p)) 311 311 return -EIO; 312 312 313 313 if (!(p.rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { ··· 556 556 * 557 557 * Use mc146818_avoid_UIP() to avoid this. 558 558 */ 559 - if (!mc146818_avoid_UIP(cmos_set_alarm_callback, &p)) 560 - return -EIO; 559 + if (!mc146818_avoid_UIP(cmos_set_alarm_callback, 10, &p)) 560 + return -ETIMEDOUT; 561 561 562 562 cmos->alarm_expires = rtc_tm_to_time64(&t->time); 563 563 ··· 818 818 } 819 819 820 820 #ifdef CONFIG_X86 821 - /* Enable use_acpi_alarm mode for Intel platforms no earlier than 2015 */ 822 821 static void use_acpi_alarm_quirks(void) 823 822 { 824 - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 823 + switch (boot_cpu_data.x86_vendor) { 824 + case X86_VENDOR_INTEL: 825 + if (dmi_get_bios_year() < 2015) 826 + return; 827 + break; 828 + case X86_VENDOR_AMD: 829 + case X86_VENDOR_HYGON: 830 + if (dmi_get_bios_year() < 2021) 831 + return; 832 + break; 833 + default: 825 834 return; 826 - 835 + } 827 836 if (!is_hpet_enabled()) 828 - return; 829 - 830 - if (dmi_get_bios_year() < 2015) 831 837 return; 832 838 833 839 use_acpi_alarm = true;

+40 -48

drivers/rtc/rtc-da9063.c

··· 377 377 { 378 378 struct da9063_compatible_rtc *rtc; 379 379 const struct da9063_compatible_rtc_regmap *config; 380 - const struct of_device_id *match; 381 380 int irq_alarm; 382 381 u8 data[RTC_DATA_LEN]; 383 382 int ret; ··· 384 385 if (!pdev->dev.of_node) 385 386 return -ENXIO; 386 387 387 - match = of_match_node(da9063_compatible_reg_id_table, 388 - pdev->dev.of_node); 389 - 390 388 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 391 389 if (!rtc) 392 390 return -ENOMEM; 393 391 394 - rtc->config = match->data; 392 + rtc->config = device_get_match_data(&pdev->dev); 395 393 if (of_device_is_compatible(pdev->dev.of_node, "dlg,da9063-rtc")) { 396 394 struct da9063 *chip = dev_get_drvdata(pdev->dev.parent); 397 395 ··· 407 411 config->rtc_enable_reg, 408 412 config->rtc_enable_mask, 409 413 config->rtc_enable_mask); 410 - if (ret < 0) { 411 - dev_err(&pdev->dev, "Failed to enable RTC\n"); 412 - return ret; 413 - } 414 + if (ret < 0) 415 + return dev_err_probe(&pdev->dev, ret, "Failed to enable RTC\n"); 414 416 415 417 ret = regmap_update_bits(rtc->regmap, 416 418 config->rtc_enable_32k_crystal_reg, 417 419 config->rtc_crystal_mask, 418 420 config->rtc_crystal_mask); 419 - if (ret < 0) { 420 - dev_err(&pdev->dev, "Failed to run 32kHz oscillator\n"); 421 - return ret; 422 - } 421 + if (ret < 0) 422 + return dev_err_probe(&pdev->dev, ret, 423 + "Failed to run 32kHz oscillator\n"); 423 424 424 425 ret = regmap_update_bits(rtc->regmap, 425 426 config->rtc_alarm_secs_reg, 426 427 config->rtc_alarm_status_mask, 427 428 0); 428 - if (ret < 0) { 429 - dev_err(&pdev->dev, "Failed to access RTC alarm register\n"); 430 - return ret; 431 - } 429 + if (ret < 0) 430 + return dev_err_probe(&pdev->dev, ret, 431 + "Failed to access RTC alarm register\n"); 432 432 433 433 ret = regmap_update_bits(rtc->regmap, 434 434 config->rtc_alarm_secs_reg, 435 435 DA9063_ALARM_STATUS_ALARM, 436 436 DA9063_ALARM_STATUS_ALARM); 437 - if (ret < 0) { 438 - dev_err(&pdev->dev, "Failed to access RTC alarm register\n"); 439 - return ret; 440 - } 437 + if (ret < 0) 438 + return dev_err_probe(&pdev->dev, ret, 439 + "Failed to access RTC alarm register\n"); 441 440 442 441 ret = regmap_update_bits(rtc->regmap, 443 442 config->rtc_alarm_year_reg, 444 443 config->rtc_tick_on_mask, 445 444 0); 446 - if (ret < 0) { 447 - dev_err(&pdev->dev, "Failed to disable TICKs\n"); 448 - return ret; 449 - } 445 + if (ret < 0) 446 + return dev_err_probe(&pdev->dev, ret, 447 + "Failed to disable TICKs\n"); 450 448 451 449 data[RTC_SEC] = 0; 452 450 ret = regmap_bulk_read(rtc->regmap, 453 451 config->rtc_alarm_secs_reg, 454 452 &data[config->rtc_data_start], 455 453 config->rtc_alarm_len); 456 - if (ret < 0) { 457 - dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n", 458 - ret); 459 - return ret; 460 - } 454 + if (ret < 0) 455 + return dev_err_probe(&pdev->dev, ret, 456 + "Failed to read initial alarm data\n"); 461 457 462 458 platform_set_drvdata(pdev, rtc); 463 459 ··· 473 485 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtc_dev->features); 474 486 } 475 487 476 - irq_alarm = platform_get_irq_byname(pdev, "ALARM"); 477 - if (irq_alarm < 0) 488 + irq_alarm = platform_get_irq_byname_optional(pdev, "ALARM"); 489 + if (irq_alarm >= 0) { 490 + ret = devm_request_threaded_irq(&pdev->dev, irq_alarm, NULL, 491 + da9063_alarm_event, 492 + IRQF_TRIGGER_LOW | IRQF_ONESHOT, 493 + "ALARM", rtc); 494 + if (ret) 495 + dev_err(&pdev->dev, 496 + "Failed to request ALARM IRQ %d: %d\n", 497 + irq_alarm, ret); 498 + 499 + ret = dev_pm_set_wake_irq(&pdev->dev, irq_alarm); 500 + if (ret) 501 + dev_warn(&pdev->dev, 502 + "Failed to set IRQ %d as a wake IRQ: %d\n", 503 + irq_alarm, ret); 504 + 505 + device_init_wakeup(&pdev->dev, true); 506 + } else if (irq_alarm != -ENXIO) { 478 507 return irq_alarm; 479 - 480 - ret = devm_request_threaded_irq(&pdev->dev, irq_alarm, NULL, 481 - da9063_alarm_event, 482 - IRQF_TRIGGER_LOW | IRQF_ONESHOT, 483 - "ALARM", rtc); 484 - if (ret) 485 - dev_err(&pdev->dev, "Failed to request ALARM IRQ %d: %d\n", 486 - irq_alarm, ret); 487 - 488 - ret = dev_pm_set_wake_irq(&pdev->dev, irq_alarm); 489 - if (ret) 490 - dev_warn(&pdev->dev, 491 - "Failed to set IRQ %d as a wake IRQ: %d\n", 492 - irq_alarm, ret); 493 - 494 - device_init_wakeup(&pdev->dev, true); 508 + } else { 509 + clear_bit(RTC_FEATURE_ALARM, rtc->rtc_dev->features); 510 + } 495 511 496 512 return devm_rtc_register_device(rtc->rtc_dev); 497 513 }

+2 -2

drivers/rtc/rtc-ds3232.c

··· 536 536 return 0; 537 537 } 538 538 539 + #if IS_ENABLED(CONFIG_I2C) 540 + 539 541 #ifdef CONFIG_PM_SLEEP 540 542 static int ds3232_suspend(struct device *dev) 541 543 { ··· 565 563 static const struct dev_pm_ops ds3232_pm_ops = { 566 564 SET_SYSTEM_SLEEP_PM_OPS(ds3232_suspend, ds3232_resume) 567 565 }; 568 - 569 - #if IS_ENABLED(CONFIG_I2C) 570 566 571 567 static int ds3232_i2c_probe(struct i2c_client *client) 572 568 {

+304

drivers/rtc/rtc-ma35d1.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * RTC driver for Nuvoton MA35D1 4 + * 5 + * Copyright (C) 2023 Nuvoton Technology Corp. 6 + */ 7 + 8 + #include <linux/bcd.h> 9 + #include <linux/clk.h> 10 + #include <linux/delay.h> 11 + #include <linux/init.h> 12 + #include <linux/io.h> 13 + #include <linux/module.h> 14 + #include <linux/of.h> 15 + #include <linux/platform_device.h> 16 + #include <linux/rtc.h> 17 + 18 + /* MA35D1 RTC Control Registers */ 19 + #define MA35_REG_RTC_INIT 0x00 20 + #define MA35_REG_RTC_SINFASTS 0x04 21 + #define MA35_REG_RTC_FREQADJ 0x08 22 + #define MA35_REG_RTC_TIME 0x0c 23 + #define MA35_REG_RTC_CAL 0x10 24 + #define MA35_REG_RTC_CLKFMT 0x14 25 + #define MA35_REG_RTC_WEEKDAY 0x18 26 + #define MA35_REG_RTC_TALM 0x1c 27 + #define MA35_REG_RTC_CALM 0x20 28 + #define MA35_REG_RTC_LEAPYEAR 0x24 29 + #define MA35_REG_RTC_INTEN 0x28 30 + #define MA35_REG_RTC_INTSTS 0x2c 31 + 32 + /* register MA35_REG_RTC_INIT */ 33 + #define RTC_INIT_ACTIVE BIT(0) 34 + #define RTC_INIT_MAGIC_CODE 0xa5eb1357 35 + 36 + /* register MA35_REG_RTC_CLKFMT */ 37 + #define RTC_CLKFMT_24HEN BIT(0) 38 + #define RTC_CLKFMT_DCOMPEN BIT(16) 39 + 40 + /* register MA35_REG_RTC_INTEN */ 41 + #define RTC_INTEN_ALMIEN BIT(0) 42 + #define RTC_INTEN_UIEN BIT(1) 43 + #define RTC_INTEN_CLKFIEN BIT(24) 44 + #define RTC_INTEN_CLKSTIEN BIT(25) 45 + 46 + /* register MA35_REG_RTC_INTSTS */ 47 + #define RTC_INTSTS_ALMIF BIT(0) 48 + #define RTC_INTSTS_UIF BIT(1) 49 + #define RTC_INTSTS_CLKFIF BIT(24) 50 + #define RTC_INTSTS_CLKSTIF BIT(25) 51 + 52 + #define RTC_INIT_TIMEOUT 250 53 + 54 + struct ma35_rtc { 55 + int irq_num; 56 + void __iomem *rtc_reg; 57 + struct rtc_device *rtcdev; 58 + }; 59 + 60 + static u32 rtc_reg_read(struct ma35_rtc *p, u32 offset) 61 + { 62 + return __raw_readl(p->rtc_reg + offset); 63 + } 64 + 65 + static inline void rtc_reg_write(struct ma35_rtc *p, u32 offset, u32 value) 66 + { 67 + __raw_writel(value, p->rtc_reg + offset); 68 + } 69 + 70 + static irqreturn_t ma35d1_rtc_interrupt(int irq, void *data) 71 + { 72 + struct ma35_rtc *rtc = (struct ma35_rtc *)data; 73 + unsigned long events = 0, rtc_irq; 74 + 75 + rtc_irq = rtc_reg_read(rtc, MA35_REG_RTC_INTSTS); 76 + 77 + if (rtc_irq & RTC_INTSTS_ALMIF) { 78 + rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_ALMIF); 79 + events |= RTC_AF | RTC_IRQF; 80 + } 81 + 82 + rtc_update_irq(rtc->rtcdev, 1, events); 83 + 84 + return IRQ_HANDLED; 85 + } 86 + 87 + static int ma35d1_rtc_init(struct ma35_rtc *rtc, u32 ms_timeout) 88 + { 89 + const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 90 + 91 + do { 92 + if (rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE) 93 + return 0; 94 + 95 + rtc_reg_write(rtc, MA35_REG_RTC_INIT, RTC_INIT_MAGIC_CODE); 96 + 97 + mdelay(1); 98 + 99 + } while (time_before(jiffies, timeout)); 100 + 101 + return -ETIMEDOUT; 102 + } 103 + 104 + static int ma35d1_alarm_irq_enable(struct device *dev, u32 enabled) 105 + { 106 + struct ma35_rtc *rtc = dev_get_drvdata(dev); 107 + u32 reg_ien; 108 + 109 + reg_ien = rtc_reg_read(rtc, MA35_REG_RTC_INTEN); 110 + 111 + if (enabled) 112 + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien | RTC_INTEN_ALMIEN); 113 + else 114 + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien & ~RTC_INTEN_ALMIEN); 115 + 116 + return 0; 117 + } 118 + 119 + static int ma35d1_rtc_read_time(struct device *dev, struct rtc_time *tm) 120 + { 121 + struct ma35_rtc *rtc = dev_get_drvdata(dev); 122 + u32 time, cal, wday; 123 + 124 + do { 125 + time = rtc_reg_read(rtc, MA35_REG_RTC_TIME); 126 + cal = rtc_reg_read(rtc, MA35_REG_RTC_CAL); 127 + wday = rtc_reg_read(rtc, MA35_REG_RTC_WEEKDAY); 128 + } while (time != rtc_reg_read(rtc, MA35_REG_RTC_TIME) || 129 + cal != rtc_reg_read(rtc, MA35_REG_RTC_CAL)); 130 + 131 + tm->tm_mday = bcd2bin(cal >> 0); 132 + tm->tm_wday = wday; 133 + tm->tm_mon = bcd2bin(cal >> 8); 134 + tm->tm_mon = tm->tm_mon - 1; 135 + tm->tm_year = bcd2bin(cal >> 16) + 100; 136 + 137 + tm->tm_sec = bcd2bin(time >> 0); 138 + tm->tm_min = bcd2bin(time >> 8); 139 + tm->tm_hour = bcd2bin(time >> 16); 140 + 141 + return rtc_valid_tm(tm); 142 + } 143 + 144 + static int ma35d1_rtc_set_time(struct device *dev, struct rtc_time *tm) 145 + { 146 + struct ma35_rtc *rtc = dev_get_drvdata(dev); 147 + u32 val; 148 + 149 + val = bin2bcd(tm->tm_mday) << 0 | bin2bcd(tm->tm_mon + 1) << 8 | 150 + bin2bcd(tm->tm_year - 100) << 16; 151 + rtc_reg_write(rtc, MA35_REG_RTC_CAL, val); 152 + 153 + val = bin2bcd(tm->tm_sec) << 0 | bin2bcd(tm->tm_min) << 8 | 154 + bin2bcd(tm->tm_hour) << 16; 155 + rtc_reg_write(rtc, MA35_REG_RTC_TIME, val); 156 + 157 + val = tm->tm_wday; 158 + rtc_reg_write(rtc, MA35_REG_RTC_WEEKDAY, val); 159 + 160 + return 0; 161 + } 162 + 163 + static int ma35d1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 164 + { 165 + struct ma35_rtc *rtc = dev_get_drvdata(dev); 166 + u32 talm, calm; 167 + 168 + talm = rtc_reg_read(rtc, MA35_REG_RTC_TALM); 169 + calm = rtc_reg_read(rtc, MA35_REG_RTC_CALM); 170 + 171 + alrm->time.tm_mday = bcd2bin(calm >> 0); 172 + alrm->time.tm_mon = bcd2bin(calm >> 8); 173 + alrm->time.tm_mon = alrm->time.tm_mon - 1; 174 + 175 + alrm->time.tm_year = bcd2bin(calm >> 16) + 100; 176 + 177 + alrm->time.tm_sec = bcd2bin(talm >> 0); 178 + alrm->time.tm_min = bcd2bin(talm >> 8); 179 + alrm->time.tm_hour = bcd2bin(talm >> 16); 180 + 181 + return rtc_valid_tm(&alrm->time); 182 + } 183 + 184 + static int ma35d1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 185 + { 186 + struct ma35_rtc *rtc = dev_get_drvdata(dev); 187 + unsigned long val; 188 + 189 + val = bin2bcd(alrm->time.tm_mday) << 0 | bin2bcd(alrm->time.tm_mon + 1) << 8 | 190 + bin2bcd(alrm->time.tm_year - 100) << 16; 191 + rtc_reg_write(rtc, MA35_REG_RTC_CALM, val); 192 + 193 + val = bin2bcd(alrm->time.tm_sec) << 0 | bin2bcd(alrm->time.tm_min) << 8 | 194 + bin2bcd(alrm->time.tm_hour) << 16; 195 + rtc_reg_write(rtc, MA35_REG_RTC_TALM, val); 196 + 197 + ma35d1_alarm_irq_enable(dev, alrm->enabled); 198 + 199 + return 0; 200 + } 201 + 202 + static const struct rtc_class_ops ma35d1_rtc_ops = { 203 + .read_time = ma35d1_rtc_read_time, 204 + .set_time = ma35d1_rtc_set_time, 205 + .read_alarm = ma35d1_rtc_read_alarm, 206 + .set_alarm = ma35d1_rtc_set_alarm, 207 + .alarm_irq_enable = ma35d1_alarm_irq_enable, 208 + }; 209 + 210 + static int ma35d1_rtc_probe(struct platform_device *pdev) 211 + { 212 + struct ma35_rtc *rtc; 213 + struct clk *clk; 214 + int ret; 215 + 216 + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 217 + if (!rtc) 218 + return -ENOMEM; 219 + 220 + rtc->rtc_reg = devm_platform_ioremap_resource(pdev, 0); 221 + if (IS_ERR(rtc->rtc_reg)) 222 + return PTR_ERR(rtc->rtc_reg); 223 + 224 + clk = of_clk_get(pdev->dev.of_node, 0); 225 + if (IS_ERR(clk)) 226 + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "failed to find rtc clock\n"); 227 + 228 + ret = clk_prepare_enable(clk); 229 + if (ret) 230 + return ret; 231 + 232 + if (!(rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE)) { 233 + ret = ma35d1_rtc_init(rtc, RTC_INIT_TIMEOUT); 234 + if (ret) 235 + return dev_err_probe(&pdev->dev, ret, "rtc init failed\n"); 236 + } 237 + 238 + rtc->irq_num = platform_get_irq(pdev, 0); 239 + 240 + ret = devm_request_irq(&pdev->dev, rtc->irq_num, ma35d1_rtc_interrupt, 241 + IRQF_NO_SUSPEND, "ma35d1rtc", rtc); 242 + if (ret) 243 + return dev_err_probe(&pdev->dev, ret, "Failed to request rtc irq\n"); 244 + 245 + platform_set_drvdata(pdev, rtc); 246 + 247 + device_init_wakeup(&pdev->dev, true); 248 + 249 + rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev); 250 + if (IS_ERR(rtc->rtcdev)) 251 + return PTR_ERR(rtc->rtcdev); 252 + 253 + rtc->rtcdev->ops = &ma35d1_rtc_ops; 254 + rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000; 255 + rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099; 256 + 257 + ret = devm_rtc_register_device(rtc->rtcdev); 258 + if (ret) 259 + return dev_err_probe(&pdev->dev, ret, "Failed to register rtc device\n"); 260 + 261 + return 0; 262 + } 263 + 264 + static int ma35d1_rtc_suspend(struct platform_device *pdev, pm_message_t state) 265 + { 266 + struct ma35_rtc *rtc = platform_get_drvdata(pdev); 267 + 268 + if (device_may_wakeup(&pdev->dev)) 269 + enable_irq_wake(rtc->irq_num); 270 + 271 + return 0; 272 + } 273 + 274 + static int ma35d1_rtc_resume(struct platform_device *pdev) 275 + { 276 + struct ma35_rtc *rtc = platform_get_drvdata(pdev); 277 + 278 + if (device_may_wakeup(&pdev->dev)) 279 + disable_irq_wake(rtc->irq_num); 280 + 281 + return 0; 282 + } 283 + 284 + static const struct of_device_id ma35d1_rtc_of_match[] = { 285 + { .compatible = "nuvoton,ma35d1-rtc", }, 286 + {}, 287 + }; 288 + MODULE_DEVICE_TABLE(of, ma35d1_rtc_of_match); 289 + 290 + static struct platform_driver ma35d1_rtc_driver = { 291 + .suspend = ma35d1_rtc_suspend, 292 + .resume = ma35d1_rtc_resume, 293 + .probe = ma35d1_rtc_probe, 294 + .driver = { 295 + .name = "rtc-ma35d1", 296 + .of_match_table = ma35d1_rtc_of_match, 297 + }, 298 + }; 299 + 300 + module_platform_driver(ma35d1_rtc_driver); 301 + 302 + MODULE_AUTHOR("Ming-Jen Chen <mjchen@nuvoton.com>"); 303 + MODULE_DESCRIPTION("MA35D1 RTC driver"); 304 + MODULE_LICENSE("GPL");

+697

drivers/rtc/rtc-max31335.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * RTC driver for the MAX31335 4 + * 5 + * Copyright (C) 2023 Analog Devices 6 + * 7 + * Antoniu Miclaus <antoniu.miclaus@analog.com> 8 + * 9 + */ 10 + 11 + #include <asm-generic/unaligned.h> 12 + #include <linux/bcd.h> 13 + #include <linux/bitfield.h> 14 + #include <linux/bitops.h> 15 + #include <linux/clk.h> 16 + #include <linux/clk-provider.h> 17 + #include <linux/hwmon.h> 18 + #include <linux/i2c.h> 19 + #include <linux/interrupt.h> 20 + #include <linux/kernel.h> 21 + #include <linux/module.h> 22 + #include <linux/of_device.h> 23 + #include <linux/regmap.h> 24 + #include <linux/rtc.h> 25 + #include <linux/util_macros.h> 26 + 27 + /* MAX31335 Register Map */ 28 + #define MAX31335_STATUS1 0x00 29 + #define MAX31335_INT_EN1 0x01 30 + #define MAX31335_STATUS2 0x02 31 + #define MAX31335_INT_EN2 0x03 32 + #define MAX31335_RTC_RESET 0x04 33 + #define MAX31335_RTC_CONFIG 0x05 34 + #define MAX31335_RTC_CONFIG2 0x06 35 + #define MAX31335_TIMESTAMP_CONFIG 0x07 36 + #define MAX31335_TIMER_CONFIG 0x08 37 + #define MAX31335_SECONDS_1_128 0x09 38 + #define MAX31335_SECONDS 0x0A 39 + #define MAX31335_MINUTES 0x0B 40 + #define MAX31335_HOURS 0x0C 41 + #define MAX31335_DAY 0x0D 42 + #define MAX31335_DATE 0x0E 43 + #define MAX31335_MONTH 0x0F 44 + #define MAX31335_YEAR 0x0F 45 + #define MAX31335_ALM1_SEC 0x11 46 + #define MAX31335_ALM1_MIN 0x12 47 + #define MAX31335_ALM1_HRS 0x13 48 + #define MAX31335_ALM1_DAY_DATE 0x14 49 + #define MAX31335_ALM1_MON 0x15 50 + #define MAX31335_ALM1_YEAR 0x16 51 + #define MAX31335_ALM2_MIN 0x17 52 + #define MAX31335_ALM2_HRS 0x18 53 + #define MAX31335_ALM2_DAY_DATE 0x19 54 + #define MAX31335_TIMER_COUNT 0x1A 55 + #define MAX31335_TIMER_INIT 0x1B 56 + #define MAX31335_PWR_MGMT 0x1C 57 + #define MAX31335_TRICKLE_REG 0x1D 58 + #define MAX31335_AGING_OFFSET 0x1E 59 + #define MAX31335_TS_CONFIG 0x30 60 + #define MAX31335_TEMP_ALARM_HIGH_MSB 0x31 61 + #define MAX31335_TEMP_ALARM_HIGH_LSB 0x32 62 + #define MAX31335_TEMP_ALARM_LOW_MSB 0x33 63 + #define MAX31335_TEMP_ALARM_LOW_LSB 0x34 64 + #define MAX31335_TEMP_DATA_MSB 0x35 65 + #define MAX31335_TEMP_DATA_LSB 0x36 66 + #define MAX31335_TS0_SEC_1_128 0x40 67 + #define MAX31335_TS0_SEC 0x41 68 + #define MAX31335_TS0_MIN 0x42 69 + #define MAX31335_TS0_HOUR 0x43 70 + #define MAX31335_TS0_DATE 0x44 71 + #define MAX31335_TS0_MONTH 0x45 72 + #define MAX31335_TS0_YEAR 0x46 73 + #define MAX31335_TS0_FLAGS 0x47 74 + #define MAX31335_TS1_SEC_1_128 0x48 75 + #define MAX31335_TS1_SEC 0x49 76 + #define MAX31335_TS1_MIN 0x4A 77 + #define MAX31335_TS1_HOUR 0x4B 78 + #define MAX31335_TS1_DATE 0x4C 79 + #define MAX31335_TS1_MONTH 0x4D 80 + #define MAX31335_TS1_YEAR 0x4E 81 + #define MAX31335_TS1_FLAGS 0x4F 82 + #define MAX31335_TS2_SEC_1_128 0x50 83 + #define MAX31335_TS2_SEC 0x51 84 + #define MAX31335_TS2_MIN 0x52 85 + #define MAX31335_TS2_HOUR 0x53 86 + #define MAX31335_TS2_DATE 0x54 87 + #define MAX31335_TS2_MONTH 0x55 88 + #define MAX31335_TS2_YEAR 0x56 89 + #define MAX31335_TS2_FLAGS 0x57 90 + #define MAX31335_TS3_SEC_1_128 0x58 91 + #define MAX31335_TS3_SEC 0x59 92 + #define MAX31335_TS3_MIN 0x5A 93 + #define MAX31335_TS3_HOUR 0x5B 94 + #define MAX31335_TS3_DATE 0x5C 95 + #define MAX31335_TS3_MONTH 0x5D 96 + #define MAX31335_TS3_YEAR 0x5E 97 + #define MAX31335_TS3_FLAGS 0x5F 98 + 99 + /* MAX31335_STATUS1 Bit Definitions */ 100 + #define MAX31335_STATUS1_PSDECT BIT(7) 101 + #define MAX31335_STATUS1_OSF BIT(6) 102 + #define MAX31335_STATUS1_PFAIL BIT(5) 103 + #define MAX31335_STATUS1_VBATLOW BIT(4) 104 + #define MAX31335_STATUS1_DIF BIT(3) 105 + #define MAX31335_STATUS1_TIF BIT(2) 106 + #define MAX31335_STATUS1_A2F BIT(1) 107 + #define MAX31335_STATUS1_A1F BIT(0) 108 + 109 + /* MAX31335_INT_EN1 Bit Definitions */ 110 + #define MAX31335_INT_EN1_DOSF BIT(6) 111 + #define MAX31335_INT_EN1_PFAILE BIT(5) 112 + #define MAX31335_INT_EN1_VBATLOWE BIT(4) 113 + #define MAX31335_INT_EN1_DIE BIT(3) 114 + #define MAX31335_INT_EN1_TIE BIT(2) 115 + #define MAX31335_INT_EN1_A2IE BIT(1) 116 + #define MAX31335_INT_EN1_A1IE BIT(0) 117 + 118 + /* MAX31335_STATUS2 Bit Definitions */ 119 + #define MAX31335_STATUS2_TEMP_RDY BIT(2) 120 + #define MAX31335_STATUS2_OTF BIT(1) 121 + #define MAX31335_STATUS2_UTF BIT(0) 122 + 123 + /* MAX31335_INT_EN2 Bit Definitions */ 124 + #define MAX31335_INT_EN2_TEMP_RDY_EN BIT(2) 125 + #define MAX31335_INT_EN2_OTIE BIT(1) 126 + #define MAX31335_INT_EN2_UTIE BIT(0) 127 + 128 + /* MAX31335_RTC_RESET Bit Definitions */ 129 + #define MAX31335_RTC_RESET_SWRST BIT(0) 130 + 131 + /* MAX31335_RTC_CONFIG1 Bit Definitions */ 132 + #define MAX31335_RTC_CONFIG1_EN_IO BIT(6) 133 + #define MAX31335_RTC_CONFIG1_A1AC GENMASK(5, 4) 134 + #define MAX31335_RTC_CONFIG1_DIP BIT(3) 135 + #define MAX31335_RTC_CONFIG1_I2C_TIMEOUT BIT(1) 136 + #define MAX31335_RTC_CONFIG1_EN_OSC BIT(0) 137 + 138 + /* MAX31335_RTC_CONFIG2 Bit Definitions */ 139 + #define MAX31335_RTC_CONFIG2_ENCLKO BIT(2) 140 + #define MAX31335_RTC_CONFIG2_CLKO_HZ GENMASK(1, 0) 141 + 142 + /* MAX31335_TIMESTAMP_CONFIG Bit Definitions */ 143 + #define MAX31335_TIMESTAMP_CONFIG_TSVLOW BIT(5) 144 + #define MAX31335_TIMESTAMP_CONFIG_TSPWM BIT(4) 145 + #define MAX31335_TIMESTAMP_CONFIG_TSDIN BIT(3) 146 + #define MAX31335_TIMESTAMP_CONFIG_TSOW BIT(2) 147 + #define MAX31335_TIMESTAMP_CONFIG_TSR BIT(1) 148 + #define MAX31335_TIMESTAMP_CONFIG_TSE BIT(0) 149 + 150 + /* MAX31335_TIMER_CONFIG Bit Definitions */ 151 + #define MAX31335_TIMER_CONFIG_TE BIT(4) 152 + #define MAX31335_TIMER_CONFIG_TPAUSE BIT(3) 153 + #define MAX31335_TIMER_CONFIG_TRPT BIT(2) 154 + #define MAX31335_TIMER_CONFIG_TFS GENMASK(1, 0) 155 + 156 + /* MAX31335_HOURS Bit Definitions */ 157 + #define MAX31335_HOURS_F_24_12 BIT(6) 158 + #define MAX31335_HOURS_HR_20_AM_PM BIT(5) 159 + 160 + /* MAX31335_MONTH Bit Definitions */ 161 + #define MAX31335_MONTH_CENTURY BIT(7) 162 + 163 + /* MAX31335_PWR_MGMT Bit Definitions */ 164 + #define MAX31335_PWR_MGMT_PFVT BIT(0) 165 + 166 + /* MAX31335_TRICKLE_REG Bit Definitions */ 167 + #define MAX31335_TRICKLE_REG_TRICKLE GENMASK(3, 1) 168 + #define MAX31335_TRICKLE_REG_EN_TRICKLE BIT(0) 169 + 170 + /* MAX31335_TS_CONFIG Bit Definitions */ 171 + #define MAX31335_TS_CONFIG_AUTO BIT(4) 172 + #define MAX31335_TS_CONFIG_CONVERT_T BIT(3) 173 + #define MAX31335_TS_CONFIG_TSINT GENMASK(2, 0) 174 + 175 + /* MAX31335_TS_FLAGS Bit Definitions */ 176 + #define MAX31335_TS_FLAGS_VLOWF BIT(3) 177 + #define MAX31335_TS_FLAGS_VBATF BIT(2) 178 + #define MAX31335_TS_FLAGS_VCCF BIT(1) 179 + #define MAX31335_TS_FLAGS_DINF BIT(0) 180 + 181 + /* MAX31335 Miscellaneous Definitions */ 182 + #define MAX31335_TRICKLE_SCHOTTKY_DIODE 1 183 + #define MAX31335_TRICKLE_STANDARD_DIODE 4 184 + #define MAX31335_RAM_SIZE 32 185 + #define MAX31335_TIME_SIZE 0x07 186 + 187 + #define clk_hw_to_max31335(_hw) container_of(_hw, struct max31335_data, clkout) 188 + 189 + struct max31335_data { 190 + struct regmap *regmap; 191 + struct rtc_device *rtc; 192 + struct clk_hw clkout; 193 + }; 194 + 195 + static const int max31335_clkout_freq[] = { 1, 64, 1024, 32768 }; 196 + 197 + static const u16 max31335_trickle_resistors[] = {3000, 6000, 11000}; 198 + 199 + static bool max31335_volatile_reg(struct device *dev, unsigned int reg) 200 + { 201 + /* time keeping registers */ 202 + if (reg >= MAX31335_SECONDS && 203 + reg < MAX31335_SECONDS + MAX31335_TIME_SIZE) 204 + return true; 205 + 206 + /* interrupt status register */ 207 + if (reg == MAX31335_INT_EN1_A1IE) 208 + return true; 209 + 210 + /* temperature registers */ 211 + if (reg == MAX31335_TEMP_DATA_MSB || reg == MAX31335_TEMP_DATA_LSB) 212 + return true; 213 + 214 + return false; 215 + } 216 + 217 + static const struct regmap_config regmap_config = { 218 + .reg_bits = 8, 219 + .val_bits = 8, 220 + .max_register = 0x5F, 221 + .volatile_reg = max31335_volatile_reg, 222 + }; 223 + 224 + static int max31335_read_time(struct device *dev, struct rtc_time *tm) 225 + { 226 + struct max31335_data *max31335 = dev_get_drvdata(dev); 227 + u8 date[7]; 228 + int ret; 229 + 230 + ret = regmap_bulk_read(max31335->regmap, MAX31335_SECONDS, date, 231 + sizeof(date)); 232 + if (ret) 233 + return ret; 234 + 235 + tm->tm_sec = bcd2bin(date[0] & 0x7f); 236 + tm->tm_min = bcd2bin(date[1] & 0x7f); 237 + tm->tm_hour = bcd2bin(date[2] & 0x3f); 238 + tm->tm_wday = bcd2bin(date[3] & 0x7) - 1; 239 + tm->tm_mday = bcd2bin(date[4] & 0x3f); 240 + tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1; 241 + tm->tm_year = bcd2bin(date[6]) + 100; 242 + 243 + if (FIELD_GET(MAX31335_MONTH_CENTURY, date[5])) 244 + tm->tm_year += 100; 245 + 246 + return 0; 247 + } 248 + 249 + static int max31335_set_time(struct device *dev, struct rtc_time *tm) 250 + { 251 + struct max31335_data *max31335 = dev_get_drvdata(dev); 252 + u8 date[7]; 253 + 254 + date[0] = bin2bcd(tm->tm_sec); 255 + date[1] = bin2bcd(tm->tm_min); 256 + date[2] = bin2bcd(tm->tm_hour); 257 + date[3] = bin2bcd(tm->tm_wday + 1); 258 + date[4] = bin2bcd(tm->tm_mday); 259 + date[5] = bin2bcd(tm->tm_mon + 1); 260 + date[6] = bin2bcd(tm->tm_year % 100); 261 + 262 + if (tm->tm_year >= 200) 263 + date[5] |= FIELD_PREP(MAX31335_MONTH_CENTURY, 1); 264 + 265 + return regmap_bulk_write(max31335->regmap, MAX31335_SECONDS, date, 266 + sizeof(date)); 267 + } 268 + 269 + static int max31335_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 270 + { 271 + struct max31335_data *max31335 = dev_get_drvdata(dev); 272 + int ret, ctrl, status; 273 + struct rtc_time time; 274 + u8 regs[6]; 275 + 276 + ret = regmap_bulk_read(max31335->regmap, MAX31335_ALM1_SEC, regs, 277 + sizeof(regs)); 278 + if (ret) 279 + return ret; 280 + 281 + alrm->time.tm_sec = bcd2bin(regs[0] & 0x7f); 282 + alrm->time.tm_min = bcd2bin(regs[1] & 0x7f); 283 + alrm->time.tm_hour = bcd2bin(regs[2] & 0x3f); 284 + alrm->time.tm_mday = bcd2bin(regs[3] & 0x3f); 285 + alrm->time.tm_mon = bcd2bin(regs[4] & 0x1f) - 1; 286 + alrm->time.tm_year = bcd2bin(regs[5]) + 100; 287 + 288 + ret = max31335_read_time(dev, &time); 289 + if (ret) 290 + return ret; 291 + 292 + if (time.tm_year >= 200) 293 + alrm->time.tm_year += 100; 294 + 295 + ret = regmap_read(max31335->regmap, MAX31335_INT_EN1, &ctrl); 296 + if (ret) 297 + return ret; 298 + 299 + ret = regmap_read(max31335->regmap, MAX31335_STATUS1, &status); 300 + if (ret) 301 + return ret; 302 + 303 + alrm->enabled = FIELD_GET(MAX31335_INT_EN1_A1IE, ctrl); 304 + alrm->pending = FIELD_GET(MAX31335_STATUS1_A1F, status); 305 + 306 + return 0; 307 + } 308 + 309 + static int max31335_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 310 + { 311 + struct max31335_data *max31335 = dev_get_drvdata(dev); 312 + unsigned int reg; 313 + u8 regs[6]; 314 + int ret; 315 + 316 + regs[0] = bin2bcd(alrm->time.tm_sec); 317 + regs[1] = bin2bcd(alrm->time.tm_min); 318 + regs[2] = bin2bcd(alrm->time.tm_hour); 319 + regs[3] = bin2bcd(alrm->time.tm_mday); 320 + regs[4] = bin2bcd(alrm->time.tm_mon + 1); 321 + regs[5] = bin2bcd(alrm->time.tm_year % 100); 322 + 323 + ret = regmap_bulk_write(max31335->regmap, MAX31335_ALM1_SEC, 324 + regs, sizeof(regs)); 325 + if (ret) 326 + return ret; 327 + 328 + reg = FIELD_PREP(MAX31335_INT_EN1_A1IE, alrm->enabled); 329 + ret = regmap_update_bits(max31335->regmap, MAX31335_INT_EN1, 330 + MAX31335_INT_EN1_A1IE, reg); 331 + if (ret) 332 + return ret; 333 + 334 + ret = regmap_update_bits(max31335->regmap, MAX31335_STATUS1, 335 + MAX31335_STATUS1_A1F, 0); 336 + 337 + return 0; 338 + } 339 + 340 + static int max31335_alarm_irq_enable(struct device *dev, unsigned int enabled) 341 + { 342 + struct max31335_data *max31335 = dev_get_drvdata(dev); 343 + 344 + return regmap_update_bits(max31335->regmap, MAX31335_INT_EN1, 345 + MAX31335_INT_EN1_A1IE, enabled); 346 + } 347 + 348 + static irqreturn_t max31335_handle_irq(int irq, void *dev_id) 349 + { 350 + struct max31335_data *max31335 = dev_id; 351 + bool status; 352 + int ret; 353 + 354 + ret = regmap_update_bits_check(max31335->regmap, MAX31335_STATUS1, 355 + MAX31335_STATUS1_A1F, 0, &status); 356 + if (ret) 357 + return IRQ_HANDLED; 358 + 359 + if (status) 360 + rtc_update_irq(max31335->rtc, 1, RTC_AF | RTC_IRQF); 361 + 362 + return IRQ_HANDLED; 363 + } 364 + 365 + static const struct rtc_class_ops max31335_rtc_ops = { 366 + .read_time = max31335_read_time, 367 + .set_time = max31335_set_time, 368 + .read_alarm = max31335_read_alarm, 369 + .set_alarm = max31335_set_alarm, 370 + .alarm_irq_enable = max31335_alarm_irq_enable, 371 + }; 372 + 373 + static int max31335_trickle_charger_setup(struct device *dev, 374 + struct max31335_data *max31335) 375 + { 376 + u32 ohms, chargeable; 377 + int i, trickle_cfg; 378 + const char *diode; 379 + 380 + if (device_property_read_u32(dev, "aux-voltage-chargeable", 381 + &chargeable)) 382 + return 0; 383 + 384 + if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms)) 385 + return 0; 386 + 387 + if (device_property_read_string(dev, "adi,tc-diode", &diode)) 388 + return 0; 389 + 390 + if (!strcmp(diode, "schottky")) 391 + trickle_cfg = MAX31335_TRICKLE_SCHOTTKY_DIODE; 392 + else if (!strcmp(diode, "standard+schottky")) 393 + trickle_cfg = MAX31335_TRICKLE_STANDARD_DIODE; 394 + else 395 + return dev_err_probe(dev, -EINVAL, 396 + "Invalid tc-diode value: %s\n", diode); 397 + 398 + for (i = 0; i < ARRAY_SIZE(max31335_trickle_resistors); i++) 399 + if (ohms == max31335_trickle_resistors[i]) 400 + break; 401 + 402 + if (i >= ARRAY_SIZE(max31335_trickle_resistors)) 403 + return 0; 404 + 405 + i = i + trickle_cfg; 406 + 407 + return regmap_write(max31335->regmap, MAX31335_TRICKLE_REG, 408 + FIELD_PREP(MAX31335_TRICKLE_REG_TRICKLE, i) | 409 + FIELD_PREP(MAX31335_TRICKLE_REG_EN_TRICKLE, 410 + chargeable)); 411 + } 412 + 413 + static unsigned long max31335_clkout_recalc_rate(struct clk_hw *hw, 414 + unsigned long parent_rate) 415 + { 416 + struct max31335_data *max31335 = clk_hw_to_max31335(hw); 417 + unsigned int freq_mask; 418 + unsigned int reg; 419 + int ret; 420 + 421 + ret = regmap_read(max31335->regmap, MAX31335_RTC_CONFIG2, &reg); 422 + if (ret) 423 + return 0; 424 + 425 + freq_mask = __roundup_pow_of_two(ARRAY_SIZE(max31335_clkout_freq)) - 1; 426 + 427 + return max31335_clkout_freq[reg & freq_mask]; 428 + } 429 + 430 + static long max31335_clkout_round_rate(struct clk_hw *hw, unsigned long rate, 431 + unsigned long *prate) 432 + { 433 + int index; 434 + 435 + index = find_closest(rate, max31335_clkout_freq, 436 + ARRAY_SIZE(max31335_clkout_freq)); 437 + 438 + return max31335_clkout_freq[index]; 439 + } 440 + 441 + static int max31335_clkout_set_rate(struct clk_hw *hw, unsigned long rate, 442 + unsigned long parent_rate) 443 + { 444 + struct max31335_data *max31335 = clk_hw_to_max31335(hw); 445 + unsigned int freq_mask; 446 + int index; 447 + 448 + index = find_closest(rate, max31335_clkout_freq, 449 + ARRAY_SIZE(max31335_clkout_freq)); 450 + freq_mask = __roundup_pow_of_two(ARRAY_SIZE(max31335_clkout_freq)) - 1; 451 + 452 + return regmap_update_bits(max31335->regmap, MAX31335_RTC_CONFIG2, 453 + freq_mask, index); 454 + } 455 + 456 + static int max31335_clkout_enable(struct clk_hw *hw) 457 + { 458 + struct max31335_data *max31335 = clk_hw_to_max31335(hw); 459 + 460 + return regmap_set_bits(max31335->regmap, MAX31335_RTC_CONFIG2, 461 + MAX31335_RTC_CONFIG2_ENCLKO); 462 + } 463 + 464 + static void max31335_clkout_disable(struct clk_hw *hw) 465 + { 466 + struct max31335_data *max31335 = clk_hw_to_max31335(hw); 467 + 468 + regmap_clear_bits(max31335->regmap, MAX31335_RTC_CONFIG2, 469 + MAX31335_RTC_CONFIG2_ENCLKO); 470 + } 471 + 472 + static int max31335_clkout_is_enabled(struct clk_hw *hw) 473 + { 474 + struct max31335_data *max31335 = clk_hw_to_max31335(hw); 475 + unsigned int reg; 476 + int ret; 477 + 478 + ret = regmap_read(max31335->regmap, MAX31335_RTC_CONFIG2, &reg); 479 + if (ret) 480 + return ret; 481 + 482 + return !!(reg & MAX31335_RTC_CONFIG2_ENCLKO); 483 + } 484 + 485 + static const struct clk_ops max31335_clkout_ops = { 486 + .recalc_rate = max31335_clkout_recalc_rate, 487 + .round_rate = max31335_clkout_round_rate, 488 + .set_rate = max31335_clkout_set_rate, 489 + .enable = max31335_clkout_enable, 490 + .disable = max31335_clkout_disable, 491 + .is_enabled = max31335_clkout_is_enabled, 492 + }; 493 + 494 + static struct clk_init_data max31335_clk_init = { 495 + .name = "max31335-clkout", 496 + .ops = &max31335_clkout_ops, 497 + }; 498 + 499 + static int max31335_nvmem_reg_read(void *priv, unsigned int offset, 500 + void *val, size_t bytes) 501 + { 502 + struct max31335_data *max31335 = priv; 503 + unsigned int reg = MAX31335_TS0_SEC_1_128 + offset; 504 + 505 + return regmap_bulk_read(max31335->regmap, reg, val, bytes); 506 + } 507 + 508 + static int max31335_nvmem_reg_write(void *priv, unsigned int offset, 509 + void *val, size_t bytes) 510 + { 511 + struct max31335_data *max31335 = priv; 512 + unsigned int reg = MAX31335_TS0_SEC_1_128 + offset; 513 + 514 + return regmap_bulk_write(max31335->regmap, reg, val, bytes); 515 + } 516 + 517 + static struct nvmem_config max31335_nvmem_cfg = { 518 + .reg_read = max31335_nvmem_reg_read, 519 + .reg_write = max31335_nvmem_reg_write, 520 + .word_size = 8, 521 + .size = MAX31335_RAM_SIZE, 522 + }; 523 + 524 + #if IS_REACHABLE(HWMON) 525 + static int max31335_read_temp(struct device *dev, enum hwmon_sensor_types type, 526 + u32 attr, int channel, long *val) 527 + { 528 + struct max31335_data *max31335 = dev_get_drvdata(dev); 529 + u8 reg[2]; 530 + s16 temp; 531 + int ret; 532 + 533 + if (type != hwmon_temp || attr != hwmon_temp_input) 534 + return -EOPNOTSUPP; 535 + 536 + ret = regmap_bulk_read(max31335->regmap, MAX31335_TEMP_DATA_MSB, 537 + reg, 2); 538 + if (ret) 539 + return ret; 540 + 541 + temp = get_unaligned_be16(reg); 542 + 543 + *val = (temp / 64) * 250; 544 + 545 + return 0; 546 + } 547 + 548 + static umode_t max31335_is_visible(const void *data, 549 + enum hwmon_sensor_types type, 550 + u32 attr, int channel) 551 + { 552 + if (type == hwmon_temp && attr == hwmon_temp_input) 553 + return 0444; 554 + 555 + return 0; 556 + } 557 + 558 + static const struct hwmon_channel_info *max31335_info[] = { 559 + HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 560 + NULL 561 + }; 562 + 563 + static const struct hwmon_ops max31335_hwmon_ops = { 564 + .is_visible = max31335_is_visible, 565 + .read = max31335_read_temp, 566 + }; 567 + 568 + static const struct hwmon_chip_info max31335_chip_info = { 569 + .ops = &max31335_hwmon_ops, 570 + .info = max31335_info, 571 + }; 572 + #endif 573 + 574 + static int max31335_clkout_register(struct device *dev) 575 + { 576 + struct max31335_data *max31335 = dev_get_drvdata(dev); 577 + int ret; 578 + 579 + if (!device_property_present(dev, "#clock-cells")) 580 + return regmap_clear_bits(max31335->regmap, MAX31335_RTC_CONFIG2, 581 + MAX31335_RTC_CONFIG2_ENCLKO); 582 + 583 + max31335->clkout.init = &max31335_clk_init; 584 + 585 + ret = devm_clk_hw_register(dev, &max31335->clkout); 586 + if (ret) 587 + return dev_err_probe(dev, ret, "cannot register clock\n"); 588 + 589 + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 590 + &max31335->clkout); 591 + if (ret) 592 + return dev_err_probe(dev, ret, "cannot add hw provider\n"); 593 + 594 + max31335->clkout.clk = devm_clk_get_enabled(dev, NULL); 595 + if (IS_ERR(max31335->clkout.clk)) 596 + return dev_err_probe(dev, PTR_ERR(max31335->clkout.clk), 597 + "cannot enable clkout\n"); 598 + 599 + return 0; 600 + } 601 + 602 + static int max31335_probe(struct i2c_client *client) 603 + { 604 + struct max31335_data *max31335; 605 + #if IS_REACHABLE(HWMON) 606 + struct device *hwmon; 607 + #endif 608 + int ret; 609 + 610 + max31335 = devm_kzalloc(&client->dev, sizeof(*max31335), GFP_KERNEL); 611 + if (!max31335) 612 + return -ENOMEM; 613 + 614 + max31335->regmap = devm_regmap_init_i2c(client, &regmap_config); 615 + if (IS_ERR(max31335->regmap)) 616 + return PTR_ERR(max31335->regmap); 617 + 618 + i2c_set_clientdata(client, max31335); 619 + 620 + max31335->rtc = devm_rtc_allocate_device(&client->dev); 621 + if (IS_ERR(max31335->rtc)) 622 + return PTR_ERR(max31335->rtc); 623 + 624 + max31335->rtc->ops = &max31335_rtc_ops; 625 + max31335->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 626 + max31335->rtc->range_max = RTC_TIMESTAMP_END_2199; 627 + max31335->rtc->alarm_offset_max = 24 * 60 * 60; 628 + 629 + ret = max31335_clkout_register(&client->dev); 630 + if (ret) 631 + return ret; 632 + 633 + if (client->irq > 0) { 634 + ret = devm_request_threaded_irq(&client->dev, client->irq, 635 + NULL, max31335_handle_irq, 636 + IRQF_ONESHOT, 637 + "max31335", max31335); 638 + if (ret) { 639 + dev_warn(&client->dev, 640 + "unable to request IRQ, alarm max31335 disabled\n"); 641 + client->irq = 0; 642 + } 643 + } 644 + 645 + if (!client->irq) 646 + clear_bit(RTC_FEATURE_ALARM, max31335->rtc->features); 647 + 648 + max31335_nvmem_cfg.priv = max31335; 649 + ret = devm_rtc_nvmem_register(max31335->rtc, &max31335_nvmem_cfg); 650 + if (ret) 651 + return dev_err_probe(&client->dev, ret, 652 + "cannot register rtc nvmem\n"); 653 + 654 + #if IS_REACHABLE(HWMON) 655 + hwmon = devm_hwmon_device_register_with_info(&client->dev, client->name, 656 + max31335, 657 + &max31335_chip_info, 658 + NULL); 659 + if (IS_ERR(hwmon)) 660 + return dev_err_probe(&client->dev, PTR_ERR(hwmon), 661 + "cannot register hwmon device\n"); 662 + #endif 663 + 664 + ret = max31335_trickle_charger_setup(&client->dev, max31335); 665 + if (ret) 666 + return ret; 667 + 668 + return devm_rtc_register_device(max31335->rtc); 669 + } 670 + 671 + static const struct i2c_device_id max31335_id[] = { 672 + { "max31335", 0 }, 673 + { } 674 + }; 675 + 676 + MODULE_DEVICE_TABLE(i2c, max31335_id); 677 + 678 + static const struct of_device_id max31335_of_match[] = { 679 + { .compatible = "adi,max31335" }, 680 + { } 681 + }; 682 + 683 + MODULE_DEVICE_TABLE(of, max31335_of_match); 684 + 685 + static struct i2c_driver max31335_driver = { 686 + .driver = { 687 + .name = "rtc-max31335", 688 + .of_match_table = max31335_of_match, 689 + }, 690 + .probe = max31335_probe, 691 + .id_table = max31335_id, 692 + }; 693 + module_i2c_driver(max31335_driver); 694 + 695 + MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 696 + MODULE_DESCRIPTION("MAX31335 RTC driver"); 697 + MODULE_LICENSE("GPL");

+30 -9

drivers/rtc/rtc-mc146818-lib.c

··· 8 8 #include <linux/acpi.h> 9 9 #endif 10 10 11 + #define UIP_RECHECK_DELAY 100 /* usec */ 12 + #define UIP_RECHECK_DELAY_MS (USEC_PER_MSEC / UIP_RECHECK_DELAY) 13 + #define UIP_RECHECK_LOOPS_MS(x) (x / UIP_RECHECK_DELAY_MS) 14 + 11 15 /* 12 16 * Execute a function while the UIP (Update-in-progress) bit of the RTC is 13 - * unset. 17 + * unset. The timeout is configurable by the caller in ms. 14 18 * 15 19 * Warning: callback may be executed more then once. 16 20 */ 17 21 bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), 22 + int timeout, 18 23 void *param) 19 24 { 20 25 int i; 21 26 unsigned long flags; 22 27 unsigned char seconds; 23 28 24 - for (i = 0; i < 100; i++) { 29 + for (i = 0; UIP_RECHECK_LOOPS_MS(i) < timeout; i++) { 25 30 spin_lock_irqsave(&rtc_lock, flags); 26 31 27 32 /* 28 33 * Check whether there is an update in progress during which the 29 34 * readout is unspecified. The maximum update time is ~2ms. Poll 30 - * every 100 usec for completion. 35 + * for completion. 31 36 * 32 37 * Store the second value before checking UIP so a long lasting 33 38 * NMI which happens to hit after the UIP check cannot make ··· 42 37 43 38 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) { 44 39 spin_unlock_irqrestore(&rtc_lock, flags); 45 - udelay(100); 40 + udelay(UIP_RECHECK_DELAY); 46 41 continue; 47 42 } 48 43 ··· 61 56 */ 62 57 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) { 63 58 spin_unlock_irqrestore(&rtc_lock, flags); 64 - udelay(100); 59 + udelay(UIP_RECHECK_DELAY); 65 60 continue; 66 61 } 67 62 ··· 77 72 } 78 73 spin_unlock_irqrestore(&rtc_lock, flags); 79 74 75 + if (UIP_RECHECK_LOOPS_MS(i) >= 100) 76 + pr_warn("Reading current time from RTC took around %li ms\n", 77 + UIP_RECHECK_LOOPS_MS(i)); 78 + 80 79 return true; 81 80 } 82 81 return false; ··· 93 84 */ 94 85 bool mc146818_does_rtc_work(void) 95 86 { 96 - return mc146818_avoid_UIP(NULL, NULL); 87 + return mc146818_avoid_UIP(NULL, 1000, NULL); 97 88 } 98 89 EXPORT_SYMBOL_GPL(mc146818_does_rtc_work); 99 90 ··· 139 130 p->ctrl = CMOS_READ(RTC_CONTROL); 140 131 } 141 132 142 - int mc146818_get_time(struct rtc_time *time) 133 + /** 134 + * mc146818_get_time - Get the current time from the RTC 135 + * @time: pointer to struct rtc_time to store the current time 136 + * @timeout: timeout value in ms 137 + * 138 + * This function reads the current time from the RTC and stores it in the 139 + * provided struct rtc_time. The timeout parameter specifies the maximum 140 + * time to wait for the RTC to become ready. 141 + * 142 + * Return: 0 on success, -ETIMEDOUT if the RTC did not become ready within 143 + * the specified timeout, or another error code if an error occurred. 144 + */ 145 + int mc146818_get_time(struct rtc_time *time, int timeout) 143 146 { 144 147 struct mc146818_get_time_callback_param p = { 145 148 .time = time 146 149 }; 147 150 148 - if (!mc146818_avoid_UIP(mc146818_get_time_callback, &p)) { 151 + if (!mc146818_avoid_UIP(mc146818_get_time_callback, timeout, &p)) { 149 152 memset(time, 0, sizeof(*time)); 150 - return -EIO; 153 + return -ETIMEDOUT; 151 154 } 152 155 153 156 if (!(p.ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)

+46 -6

drivers/rtc/rtc-nct3018y.c

··· 23 23 #define NCT3018Y_REG_CTRL 0x0A /* timer control */ 24 24 #define NCT3018Y_REG_ST 0x0B /* status */ 25 25 #define NCT3018Y_REG_CLKO 0x0C /* clock out */ 26 + #define NCT3018Y_REG_PART 0x21 /* part info */ 26 27 27 28 #define NCT3018Y_BIT_AF BIT(7) 28 29 #define NCT3018Y_BIT_ST BIT(7) ··· 38 37 #define NCT3018Y_REG_BAT_MASK 0x07 39 38 #define NCT3018Y_REG_CLKO_F_MASK 0x03 /* frequenc mask */ 40 39 #define NCT3018Y_REG_CLKO_CKE 0x80 /* clock out enabled */ 40 + #define NCT3018Y_REG_PART_NCT3018Y 0x02 41 41 42 42 struct nct3018y { 43 43 struct rtc_device *rtc; 44 44 struct i2c_client *client; 45 + int part_num; 45 46 #ifdef CONFIG_COMMON_CLK 46 47 struct clk_hw clkout_hw; 47 48 #endif ··· 180 177 static int nct3018y_rtc_set_time(struct device *dev, struct rtc_time *tm) 181 178 { 182 179 struct i2c_client *client = to_i2c_client(dev); 180 + struct nct3018y *nct3018y = dev_get_drvdata(dev); 183 181 unsigned char buf[4] = {0}; 184 - int err; 182 + int err, flags; 183 + int restore_flags = 0; 184 + 185 + flags = i2c_smbus_read_byte_data(client, NCT3018Y_REG_CTRL); 186 + if (flags < 0) { 187 + dev_dbg(&client->dev, "Failed to read NCT3018Y_REG_CTRL.\n"); 188 + return flags; 189 + } 190 + 191 + /* Check and set TWO bit */ 192 + if (nct3018y->part_num == NCT3018Y_REG_PART_NCT3018Y && !(flags & NCT3018Y_BIT_TWO)) { 193 + restore_flags = 1; 194 + flags |= NCT3018Y_BIT_TWO; 195 + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags); 196 + if (err < 0) { 197 + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL.\n"); 198 + return err; 199 + } 200 + } 185 201 186 202 buf[0] = bin2bcd(tm->tm_sec); 187 203 err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_SC, buf[0]); ··· 232 210 if (err < 0) { 233 211 dev_dbg(&client->dev, "Unable to write for day and mon and year\n"); 234 212 return -EIO; 213 + } 214 + 215 + /* Restore TWO bit */ 216 + if (restore_flags) { 217 + if (nct3018y->part_num == NCT3018Y_REG_PART_NCT3018Y) 218 + flags &= ~NCT3018Y_BIT_TWO; 219 + 220 + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags); 221 + if (err < 0) { 222 + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL.\n"); 223 + return err; 224 + } 235 225 } 236 226 237 227 return err; ··· 513 479 dev_dbg(&client->dev, "%s: NCT3018Y_BIT_TWO is set\n", __func__); 514 480 } 515 481 516 - flags = NCT3018Y_BIT_TWO; 517 - err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags); 518 - if (err < 0) { 519 - dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL\n"); 520 - return err; 482 + nct3018y->part_num = i2c_smbus_read_byte_data(client, NCT3018Y_REG_PART); 483 + if (nct3018y->part_num < 0) { 484 + dev_dbg(&client->dev, "Failed to read NCT3018Y_REG_PART.\n"); 485 + return nct3018y->part_num; 486 + } else if (nct3018y->part_num == NCT3018Y_REG_PART_NCT3018Y) { 487 + flags = NCT3018Y_BIT_HF; 488 + err = i2c_smbus_write_byte_data(client, NCT3018Y_REG_CTRL, flags); 489 + if (err < 0) { 490 + dev_dbg(&client->dev, "Unable to write NCT3018Y_REG_CTRL.\n"); 491 + return err; 492 + } 521 493 } 522 494 523 495 flags = 0;

+34 -2

drivers/rtc/rtc-rv8803.c

··· 17 17 #include <linux/module.h> 18 18 #include <linux/of.h> 19 19 #include <linux/rtc.h> 20 + #include <linux/pm_wakeirq.h> 20 21 21 22 #define RV8803_I2C_TRY_COUNT 4 22 23 ··· 608 607 return 0; 609 608 } 610 609 610 + static int rv8803_resume(struct device *dev) 611 + { 612 + struct rv8803_data *rv8803 = dev_get_drvdata(dev); 613 + 614 + if (rv8803->client->irq > 0 && device_may_wakeup(dev)) 615 + disable_irq_wake(rv8803->client->irq); 616 + 617 + return 0; 618 + } 619 + 620 + static int rv8803_suspend(struct device *dev) 621 + { 622 + struct rv8803_data *rv8803 = dev_get_drvdata(dev); 623 + 624 + if (rv8803->client->irq > 0 && device_may_wakeup(dev)) 625 + enable_irq_wake(rv8803->client->irq); 626 + 627 + return 0; 628 + } 629 + 630 + static DEFINE_SIMPLE_DEV_PM_OPS(rv8803_pm_ops, rv8803_suspend, rv8803_resume); 631 + 611 632 static const struct i2c_device_id rv8803_id[] = { 612 633 { "rv8803", rv_8803 }, 613 634 { "rv8804", rx_8804 }, ··· 706 683 if (err) { 707 684 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); 708 685 client->irq = 0; 686 + } else { 687 + device_init_wakeup(&client->dev, true); 688 + err = dev_pm_set_wake_irq(&client->dev, client->irq); 689 + if (err) 690 + dev_err(&client->dev, "failed to set wake IRQ\n"); 709 691 } 692 + } else { 693 + if (device_property_read_bool(&client->dev, "wakeup-source")) 694 + device_init_wakeup(&client->dev, true); 695 + else 696 + clear_bit(RTC_FEATURE_ALARM, rv8803->rtc->features); 710 697 } 711 - if (!client->irq) 712 - clear_bit(RTC_FEATURE_ALARM, rv8803->rtc->features); 713 698 714 699 if (of_property_read_bool(client->dev.of_node, "epson,vdet-disable")) 715 700 rv8803->backup |= RX8900_FLAG_VDETOFF; ··· 768 737 .driver = { 769 738 .name = "rtc-rv8803", 770 739 .of_match_table = of_match_ptr(rv8803_of_match), 740 + .pm = &rv8803_pm_ops, 771 741 }, 772 742 .probe = rv8803_probe, 773 743 .id_table = rv8803_id,

+454

drivers/rtc/rtc-tps6594.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * RTC driver for tps6594 PMIC 4 + * 5 + * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ 6 + */ 7 + 8 + #include <linux/bcd.h> 9 + #include <linux/errno.h> 10 + #include <linux/init.h> 11 + #include <linux/interrupt.h> 12 + #include <linux/kernel.h> 13 + #include <linux/limits.h> 14 + #include <linux/math64.h> 15 + #include <linux/module.h> 16 + #include <linux/platform_device.h> 17 + #include <linux/mod_devicetable.h> 18 + #include <linux/property.h> 19 + #include <linux/rtc.h> 20 + #include <linux/types.h> 21 + #include <linux/units.h> 22 + 23 + #include <linux/mfd/tps6594.h> 24 + 25 + // Total number of RTC registers needed to set time 26 + #define NUM_TIME_REGS (TPS6594_REG_RTC_WEEKS - TPS6594_REG_RTC_SECONDS + 1) 27 + 28 + // Total number of RTC alarm registers 29 + #define NUM_TIME_ALARM_REGS (NUM_TIME_REGS - 1) 30 + 31 + /* 32 + * Min and max values supported by 'offset' interface (swapped sign). 33 + * After conversion, the values do not exceed the range [-32767, 33767] 34 + * which COMP_REG must conform to. 35 + */ 36 + #define MIN_OFFSET (-277774) 37 + #define MAX_OFFSET (277774) 38 + 39 + // Number of ticks per hour 40 + #define TICKS_PER_HOUR (32768 * 3600) 41 + 42 + // Multiplier for ppb conversions 43 + #define PPB_MULT NANO 44 + 45 + static int tps6594_rtc_alarm_irq_enable(struct device *dev, 46 + unsigned int enabled) 47 + { 48 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 49 + u8 val; 50 + 51 + val = enabled ? TPS6594_BIT_IT_ALARM : 0; 52 + 53 + return regmap_update_bits(tps->regmap, TPS6594_REG_RTC_INTERRUPTS, 54 + TPS6594_BIT_IT_ALARM, val); 55 + } 56 + 57 + /* Pulse GET_TIME field of RTC_CTRL_1 to store a timestamp in shadow registers. */ 58 + static int tps6594_rtc_shadow_timestamp(struct device *dev, struct tps6594 *tps) 59 + { 60 + int ret; 61 + 62 + /* 63 + * Set GET_TIME to 0. Next time we set GET_TIME to 1 we will be sure to store 64 + * an up-to-date timestamp. 65 + */ 66 + ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 67 + TPS6594_BIT_GET_TIME); 68 + if (ret < 0) 69 + return ret; 70 + 71 + /* 72 + * Copy content of RTC registers to shadow registers or latches to read 73 + * a coherent timestamp. 74 + */ 75 + return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 76 + TPS6594_BIT_GET_TIME); 77 + } 78 + 79 + static int tps6594_rtc_read_time(struct device *dev, struct rtc_time *tm) 80 + { 81 + unsigned char rtc_data[NUM_TIME_REGS]; 82 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 83 + int ret; 84 + 85 + // Check if RTC is running. 86 + ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS, 87 + TPS6594_BIT_RUN); 88 + if (ret < 0) 89 + return ret; 90 + if (ret == 0) 91 + return -EINVAL; 92 + 93 + ret = tps6594_rtc_shadow_timestamp(dev, tps); 94 + if (ret < 0) 95 + return ret; 96 + 97 + // Read shadowed RTC registers. 98 + ret = regmap_bulk_read(tps->regmap, TPS6594_REG_RTC_SECONDS, rtc_data, 99 + NUM_TIME_REGS); 100 + if (ret < 0) 101 + return ret; 102 + 103 + tm->tm_sec = bcd2bin(rtc_data[0]); 104 + tm->tm_min = bcd2bin(rtc_data[1]); 105 + tm->tm_hour = bcd2bin(rtc_data[2]); 106 + tm->tm_mday = bcd2bin(rtc_data[3]); 107 + tm->tm_mon = bcd2bin(rtc_data[4]) - 1; 108 + tm->tm_year = bcd2bin(rtc_data[5]) + 100; 109 + tm->tm_wday = bcd2bin(rtc_data[6]); 110 + 111 + return 0; 112 + } 113 + 114 + static int tps6594_rtc_set_time(struct device *dev, struct rtc_time *tm) 115 + { 116 + unsigned char rtc_data[NUM_TIME_REGS]; 117 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 118 + int ret; 119 + 120 + rtc_data[0] = bin2bcd(tm->tm_sec); 121 + rtc_data[1] = bin2bcd(tm->tm_min); 122 + rtc_data[2] = bin2bcd(tm->tm_hour); 123 + rtc_data[3] = bin2bcd(tm->tm_mday); 124 + rtc_data[4] = bin2bcd(tm->tm_mon + 1); 125 + rtc_data[5] = bin2bcd(tm->tm_year - 100); 126 + rtc_data[6] = bin2bcd(tm->tm_wday); 127 + 128 + // Stop RTC while updating the RTC time registers. 129 + ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 130 + TPS6594_BIT_STOP_RTC); 131 + if (ret < 0) 132 + return ret; 133 + 134 + // Update all the time registers in one shot. 135 + ret = regmap_bulk_write(tps->regmap, TPS6594_REG_RTC_SECONDS, rtc_data, 136 + NUM_TIME_REGS); 137 + if (ret < 0) 138 + return ret; 139 + 140 + // Start back RTC. 141 + return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 142 + TPS6594_BIT_STOP_RTC); 143 + } 144 + 145 + static int tps6594_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 146 + { 147 + unsigned char alarm_data[NUM_TIME_ALARM_REGS]; 148 + u32 int_val; 149 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 150 + int ret; 151 + 152 + ret = regmap_bulk_read(tps->regmap, TPS6594_REG_ALARM_SECONDS, 153 + alarm_data, NUM_TIME_ALARM_REGS); 154 + if (ret < 0) 155 + return ret; 156 + 157 + alm->time.tm_sec = bcd2bin(alarm_data[0]); 158 + alm->time.tm_min = bcd2bin(alarm_data[1]); 159 + alm->time.tm_hour = bcd2bin(alarm_data[2]); 160 + alm->time.tm_mday = bcd2bin(alarm_data[3]); 161 + alm->time.tm_mon = bcd2bin(alarm_data[4]) - 1; 162 + alm->time.tm_year = bcd2bin(alarm_data[5]) + 100; 163 + 164 + ret = regmap_read(tps->regmap, TPS6594_REG_RTC_INTERRUPTS, &int_val); 165 + if (ret < 0) 166 + return ret; 167 + 168 + alm->enabled = int_val & TPS6594_BIT_IT_ALARM; 169 + 170 + return 0; 171 + } 172 + 173 + static int tps6594_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 174 + { 175 + unsigned char alarm_data[NUM_TIME_ALARM_REGS]; 176 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 177 + int ret; 178 + 179 + // Disable alarm irq before changing the alarm timestamp. 180 + ret = tps6594_rtc_alarm_irq_enable(dev, 0); 181 + if (ret) 182 + return ret; 183 + 184 + alarm_data[0] = bin2bcd(alm->time.tm_sec); 185 + alarm_data[1] = bin2bcd(alm->time.tm_min); 186 + alarm_data[2] = bin2bcd(alm->time.tm_hour); 187 + alarm_data[3] = bin2bcd(alm->time.tm_mday); 188 + alarm_data[4] = bin2bcd(alm->time.tm_mon + 1); 189 + alarm_data[5] = bin2bcd(alm->time.tm_year - 100); 190 + 191 + // Update all the alarm registers in one shot. 192 + ret = regmap_bulk_write(tps->regmap, TPS6594_REG_ALARM_SECONDS, 193 + alarm_data, NUM_TIME_ALARM_REGS); 194 + if (ret < 0) 195 + return ret; 196 + 197 + if (alm->enabled) 198 + ret = tps6594_rtc_alarm_irq_enable(dev, 1); 199 + 200 + return ret; 201 + } 202 + 203 + static int tps6594_rtc_set_calibration(struct device *dev, int calibration) 204 + { 205 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 206 + __le16 value; 207 + int ret; 208 + 209 + /* 210 + * TPS6594 uses two's complement 16 bit value for compensation of RTC 211 + * crystal inaccuracies. One time every hour when seconds counter 212 + * increments from 0 to 1 compensation value will be added to internal 213 + * RTC counter value. 214 + * 215 + * Valid range for compensation value: [-32767 .. 32767]. 216 + */ 217 + if (calibration < S16_MIN + 1 || calibration > S16_MAX) 218 + return -ERANGE; 219 + 220 + value = cpu_to_le16(calibration); 221 + 222 + // Update all the compensation registers in one shot. 223 + ret = regmap_bulk_write(tps->regmap, TPS6594_REG_RTC_COMP_LSB, &value, 224 + sizeof(value)); 225 + if (ret < 0) 226 + return ret; 227 + 228 + // Enable automatic compensation. 229 + return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 230 + TPS6594_BIT_AUTO_COMP); 231 + } 232 + 233 + static int tps6594_rtc_get_calibration(struct device *dev, int *calibration) 234 + { 235 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 236 + unsigned int ctrl; 237 + __le16 value; 238 + int ret; 239 + 240 + ret = regmap_read(tps->regmap, TPS6594_REG_RTC_CTRL_1, &ctrl); 241 + if (ret < 0) 242 + return ret; 243 + 244 + // If automatic compensation is not enabled report back zero. 245 + if (!(ctrl & TPS6594_BIT_AUTO_COMP)) { 246 + *calibration = 0; 247 + return 0; 248 + } 249 + 250 + ret = regmap_bulk_read(tps->regmap, TPS6594_REG_RTC_COMP_LSB, &value, 251 + sizeof(value)); 252 + if (ret < 0) 253 + return ret; 254 + 255 + *calibration = le16_to_cpu(value); 256 + 257 + return 0; 258 + } 259 + 260 + static int tps6594_rtc_read_offset(struct device *dev, long *offset) 261 + { 262 + int calibration; 263 + s64 tmp; 264 + int ret; 265 + 266 + ret = tps6594_rtc_get_calibration(dev, &calibration); 267 + if (ret < 0) 268 + return ret; 269 + 270 + // Convert from RTC calibration register format to ppb format. 271 + tmp = calibration * PPB_MULT; 272 + 273 + if (tmp < 0) 274 + tmp -= TICKS_PER_HOUR / 2LL; 275 + else 276 + tmp += TICKS_PER_HOUR / 2LL; 277 + tmp = div_s64(tmp, TICKS_PER_HOUR); 278 + 279 + /* 280 + * SAFETY: 281 + * Computatiion is the reverse operation of the one done in 282 + * `tps6594_rtc_set_offset`. The safety remarks applie here too. 283 + */ 284 + 285 + /* 286 + * Offset value operates in negative way, so swap sign. 287 + * See 8.3.10.5, (32768 - COMP_REG). 288 + */ 289 + *offset = (long)-tmp; 290 + 291 + return 0; 292 + } 293 + 294 + static int tps6594_rtc_set_offset(struct device *dev, long offset) 295 + { 296 + int calibration; 297 + s64 tmp; 298 + 299 + // Make sure offset value is within supported range. 300 + if (offset < MIN_OFFSET || offset > MAX_OFFSET) 301 + return -ERANGE; 302 + 303 + // Convert from ppb format to RTC calibration register format. 304 + 305 + tmp = offset * TICKS_PER_HOUR; 306 + if (tmp < 0) 307 + tmp -= PPB_MULT / 2LL; 308 + else 309 + tmp += PPB_MULT / 2LL; 310 + tmp = div_s64(tmp, PPB_MULT); 311 + 312 + /* 313 + * SAFETY: 314 + * - tmp = offset * TICK_PER_HOUR : 315 + * `offset` can't be more than 277774, so `tmp` can't exceed 277774000000000 316 + * which is lower than the maximum value in an `s64` (2^63-1). No overflow here. 317 + * 318 + * - tmp += TICK_PER_HOUR / 2LL : 319 + * tmp will have a maximum value of 277774117964800 which is still inferior to 2^63-1. 320 + */ 321 + 322 + // Offset value operates in negative way, so swap sign. 323 + calibration = (int)-tmp; 324 + 325 + return tps6594_rtc_set_calibration(dev, calibration); 326 + } 327 + 328 + static irqreturn_t tps6594_rtc_interrupt(int irq, void *rtc) 329 + { 330 + struct device *dev = rtc; 331 + struct tps6594 *tps = dev_get_drvdata(dev->parent); 332 + struct rtc_device *rtc_dev = dev_get_drvdata(dev); 333 + int ret; 334 + u32 rtc_reg; 335 + 336 + ret = regmap_read(tps->regmap, TPS6594_REG_RTC_STATUS, &rtc_reg); 337 + if (ret) 338 + return IRQ_NONE; 339 + 340 + rtc_update_irq(rtc_dev, 1, RTC_IRQF | RTC_AF); 341 + 342 + return IRQ_HANDLED; 343 + } 344 + 345 + static const struct rtc_class_ops tps6594_rtc_ops = { 346 + .read_time = tps6594_rtc_read_time, 347 + .set_time = tps6594_rtc_set_time, 348 + .read_alarm = tps6594_rtc_read_alarm, 349 + .set_alarm = tps6594_rtc_set_alarm, 350 + .alarm_irq_enable = tps6594_rtc_alarm_irq_enable, 351 + .read_offset = tps6594_rtc_read_offset, 352 + .set_offset = tps6594_rtc_set_offset, 353 + }; 354 + 355 + static int tps6594_rtc_probe(struct platform_device *pdev) 356 + { 357 + struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent); 358 + struct device *dev = &pdev->dev; 359 + struct rtc_device *rtc; 360 + int irq; 361 + int ret; 362 + 363 + rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); 364 + if (!rtc) 365 + return -ENOMEM; 366 + 367 + rtc = devm_rtc_allocate_device(dev); 368 + if (IS_ERR(rtc)) 369 + return PTR_ERR(rtc); 370 + 371 + // Enable crystal oscillator. 372 + ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_2, 373 + TPS6594_BIT_XTAL_EN); 374 + if (ret < 0) 375 + return ret; 376 + 377 + ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS, 378 + TPS6594_BIT_RUN); 379 + if (ret < 0) 380 + return ret; 381 + // RTC not running. 382 + if (ret == 0) { 383 + ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 384 + TPS6594_BIT_STOP_RTC); 385 + if (ret < 0) 386 + return ret; 387 + 388 + /* 389 + * On some boards, a 40 ms delay is needed before BIT_RUN is set. 390 + * 80 ms should provide sufficient margin. 391 + */ 392 + mdelay(80); 393 + 394 + /* 395 + * RTC should be running now. Check if this is the case. 396 + * If not it might be a missing oscillator. 397 + */ 398 + ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS, 399 + TPS6594_BIT_RUN); 400 + if (ret < 0) 401 + return ret; 402 + if (ret == 0) 403 + return -ENODEV; 404 + 405 + // Stop RTC until first call to `tps6594_rtc_set_time`. 406 + ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1, 407 + TPS6594_BIT_STOP_RTC); 408 + if (ret < 0) 409 + return ret; 410 + } 411 + 412 + platform_set_drvdata(pdev, rtc); 413 + 414 + irq = platform_get_irq_byname(pdev, TPS6594_IRQ_NAME_ALARM); 415 + if (irq < 0) 416 + return dev_err_probe(dev, irq, "Failed to get irq\n"); 417 + 418 + ret = devm_request_threaded_irq(dev, irq, NULL, tps6594_rtc_interrupt, 419 + IRQF_ONESHOT, TPS6594_IRQ_NAME_ALARM, 420 + dev); 421 + if (ret < 0) 422 + return dev_err_probe(dev, ret, 423 + "Failed to request_threaded_irq\n"); 424 + 425 + ret = device_init_wakeup(dev, true); 426 + if (ret < 0) 427 + return dev_err_probe(dev, ret, 428 + "Failed to init rtc as wakeup source\n"); 429 + 430 + rtc->ops = &tps6594_rtc_ops; 431 + rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 432 + rtc->range_max = RTC_TIMESTAMP_END_2099; 433 + 434 + return devm_rtc_register_device(rtc); 435 + } 436 + 437 + static const struct platform_device_id tps6594_rtc_id_table[] = { 438 + { "tps6594-rtc", }, 439 + {} 440 + }; 441 + MODULE_DEVICE_TABLE(platform, tps6594_rtc_id_table); 442 + 443 + static struct platform_driver tps6594_rtc_driver = { 444 + .probe = tps6594_rtc_probe, 445 + .driver = { 446 + .name = "tps6594-rtc", 447 + }, 448 + .id_table = tps6594_rtc_id_table, 449 + }; 450 + 451 + module_platform_driver(tps6594_rtc_driver); 452 + MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>"); 453 + MODULE_DESCRIPTION("TPS6594 RTC driver"); 454 + MODULE_LICENSE("GPL");

+2 -1

include/linux/mc146818rtc.h

··· 126 126 #endif /* ARCH_RTC_LOCATION */ 127 127 128 128 bool mc146818_does_rtc_work(void); 129 - int mc146818_get_time(struct rtc_time *time); 129 + int mc146818_get_time(struct rtc_time *time, int timeout); 130 130 int mc146818_set_time(struct rtc_time *time); 131 131 132 132 bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), 133 + int timeout, 133 134 void *param); 134 135 135 136 #endif /* _MC146818RTC_H */