Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

PCI: pciehp: Clean up debug logging

The pciehp debug logging is overly verbose and often redundant. Almost all
of the information printed by dbg_ctrl() is also printed by the normal PCI
core enumeration code and by pcie_init().

Remove the redundant debug info.

When claiming a pciehp bridge, we print the slot characteristics, e.g.,

Slot #6 AttnBtn- AttnInd- PwrInd- PwrCtrl- MRL- Interlock- NoCompl+ LLActRep+

Add the Hot-Plug Capable and Hot-Plug Surprise bits to this information,
and print it all in the same order as lspci does.

No functional change except the message text changes.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>

+20 -111
+3 -36
drivers/pci/hotplug/pciehp_core.c
··· 77 77 */ 78 78 static void release_slot(struct hotplug_slot *hotplug_slot) 79 79 { 80 - struct slot *slot = hotplug_slot->private; 81 - 82 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 83 - __func__, hotplug_slot_name(hotplug_slot)); 84 - 85 80 kfree(hotplug_slot->ops); 86 81 kfree(hotplug_slot->info); 87 82 kfree(hotplug_slot); ··· 124 129 slot->hotplug_slot = hotplug; 125 130 snprintf(name, SLOT_NAME_SIZE, "%u", PSN(ctrl)); 126 131 127 - ctrl_dbg(ctrl, "Registering domain:bus:dev=%04x:%02x:00 sun=%x\n", 128 - pci_domain_nr(ctrl->pcie->port->subordinate), 129 - ctrl->pcie->port->subordinate->number, PSN(ctrl)); 130 132 retval = pci_hp_register(hotplug, 131 133 ctrl->pcie->port->subordinate, 0, name); 132 134 if (retval) 133 - ctrl_err(ctrl, 134 - "pci_hp_register failed with error %d\n", retval); 135 + ctrl_err(ctrl, "pci_hp_register failed: error %d\n", retval); 135 136 out: 136 137 if (retval) { 137 138 kfree(ops); ··· 149 158 { 150 159 struct slot *slot = hotplug_slot->private; 151 160 152 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 153 - __func__, slot_name(slot)); 154 - 155 161 pciehp_set_attention_status(slot, status); 156 162 return 0; 157 163 } ··· 158 170 { 159 171 struct slot *slot = hotplug_slot->private; 160 172 161 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 162 - __func__, slot_name(slot)); 163 - 164 173 return pciehp_sysfs_enable_slot(slot); 165 174 } 166 175 ··· 166 181 { 167 182 struct slot *slot = hotplug_slot->private; 168 183 169 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 170 - __func__, slot_name(slot)); 171 - 172 184 return pciehp_sysfs_disable_slot(slot); 173 185 } 174 186 175 187 static int get_power_status(struct hotplug_slot *hotplug_slot, u8 *value) 176 188 { 177 189 struct slot *slot = hotplug_slot->private; 178 - 179 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 180 - __func__, slot_name(slot)); 181 190 182 191 pciehp_get_power_status(slot, value); 183 192 return 0; ··· 181 202 { 182 203 struct slot *slot = hotplug_slot->private; 183 204 184 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 185 - __func__, slot_name(slot)); 186 - 187 205 pciehp_get_attention_status(slot, value); 188 206 return 0; 189 207 } ··· 188 212 static int get_latch_status(struct hotplug_slot *hotplug_slot, u8 *value) 189 213 { 190 214 struct slot *slot = hotplug_slot->private; 191 - 192 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 193 - __func__, slot_name(slot)); 194 215 195 216 pciehp_get_latch_status(slot, value); 196 217 return 0; ··· 197 224 { 198 225 struct slot *slot = hotplug_slot->private; 199 226 200 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 201 - __func__, slot_name(slot)); 202 - 203 227 pciehp_get_adapter_status(slot, value); 204 228 return 0; 205 229 } ··· 204 234 static int reset_slot(struct hotplug_slot *hotplug_slot, int probe) 205 235 { 206 236 struct slot *slot = hotplug_slot->private; 207 - 208 - ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", 209 - __func__, slot_name(slot)); 210 237 211 238 return pciehp_reset_slot(slot, probe); 212 239 } ··· 239 272 if (rc == -EBUSY) 240 273 ctrl_warn(ctrl, "Slot already registered by another hotplug driver\n"); 241 274 else 242 - ctrl_err(ctrl, "Slot initialization failed\n"); 275 + ctrl_err(ctrl, "Slot initialization failed (%d)\n", rc); 243 276 goto err_out_release_ctlr; 244 277 } 245 278 246 279 /* Enable events after we have setup the data structures */ 247 280 rc = pcie_init_notification(ctrl); 248 281 if (rc) { 249 - ctrl_err(ctrl, "Notification initialization failed\n"); 282 + ctrl_err(ctrl, "Notification initialization failed (%d)\n", rc); 250 283 goto err_out_free_ctrl_slot; 251 284 } 252 285
+7 -31
drivers/pci/hotplug/pciehp_ctrl.c
··· 59 59 u32 event_type; 60 60 struct controller *ctrl = p_slot->ctrl; 61 61 62 - /* Attention Button Change */ 63 - ctrl_dbg(ctrl, "Attention button interrupt received\n"); 64 - 65 62 /* 66 63 * Button pressed - See if need to TAKE ACTION!!! 67 64 */ ··· 75 78 u8 getstatus; 76 79 u32 event_type; 77 80 struct controller *ctrl = p_slot->ctrl; 78 - 79 - /* Switch Change */ 80 - ctrl_dbg(ctrl, "Switch interrupt received\n"); 81 81 82 82 pciehp_get_latch_status(p_slot, &getstatus); 83 83 if (getstatus) { ··· 101 107 u32 event_type; 102 108 u8 presence_save; 103 109 struct controller *ctrl = p_slot->ctrl; 104 - 105 - /* Presence Change */ 106 - ctrl_dbg(ctrl, "Presence/Notify input change\n"); 107 110 108 111 /* Switch is open, assume a presence change 109 112 * Save the presence state ··· 131 140 u32 event_type; 132 141 struct controller *ctrl = p_slot->ctrl; 133 142 134 - /* power fault */ 135 - ctrl_dbg(ctrl, "Power fault interrupt received\n"); 136 143 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot)); 137 144 event_type = INT_POWER_FAULT; 138 145 ctrl_info(ctrl, "Power fault bit %x set\n", 0); ··· 143 154 { 144 155 u32 event_type; 145 156 struct controller *ctrl = p_slot->ctrl; 146 - 147 - /* Link Status Change */ 148 - ctrl_dbg(ctrl, "Data Link Layer State change\n"); 149 157 150 158 if (pciehp_check_link_active(ctrl)) { 151 159 ctrl_info(ctrl, "slot(%s): Link Up event\n", ··· 284 298 285 299 switch (info->req) { 286 300 case DISABLE_REQ: 287 - ctrl_dbg(p_slot->ctrl, 288 - "Disabling domain:bus:device=%04x:%02x:00\n", 289 - pci_domain_nr(p_slot->ctrl->pcie->port->subordinate), 290 - p_slot->ctrl->pcie->port->subordinate->number); 291 301 mutex_lock(&p_slot->hotplug_lock); 292 302 pciehp_disable_slot(p_slot); 293 303 mutex_unlock(&p_slot->hotplug_lock); ··· 292 310 mutex_unlock(&p_slot->lock); 293 311 break; 294 312 case ENABLE_REQ: 295 - ctrl_dbg(p_slot->ctrl, 296 - "Enabling domain:bus:device=%04x:%02x:00\n", 297 - pci_domain_nr(p_slot->ctrl->pcie->port->subordinate), 298 - p_slot->ctrl->pcie->port->subordinate->number); 299 313 mutex_lock(&p_slot->hotplug_lock); 300 314 ret = pciehp_enable_slot(p_slot); 301 315 mutex_unlock(&p_slot->hotplug_lock); ··· 394 416 ctrl_info(ctrl, "Button ignore on Slot(%s)\n", slot_name(p_slot)); 395 417 break; 396 418 default: 397 - ctrl_warn(ctrl, "Not a valid state\n"); 419 + ctrl_warn(ctrl, "ignoring invalid state %#x\n", p_slot->state); 398 420 break; 399 421 } 400 422 } ··· 485 507 } 486 508 break; 487 509 default: 488 - ctrl_err(ctrl, "Not a valid state on slot(%s)\n", 489 - slot_name(p_slot)); 510 + ctrl_err(ctrl, "ignoring invalid state %#x on slot(%s)\n", 511 + p_slot->state, slot_name(p_slot)); 490 512 kfree(info); 491 513 break; 492 514 } ··· 510 532 pciehp_green_led_off(p_slot); 511 533 break; 512 534 case INT_PRESENCE_ON: 513 - ctrl_dbg(ctrl, "Surprise Insertion\n"); 514 535 handle_surprise_event(p_slot); 515 536 break; 516 537 case INT_PRESENCE_OFF: ··· 517 540 * Regardless of surprise capability, we need to 518 541 * definitely remove a card that has been pulled out! 519 542 */ 520 - ctrl_dbg(ctrl, "Surprise Removal\n"); 521 543 handle_surprise_event(p_slot); 522 544 break; 523 545 case INT_LINK_UP: ··· 623 647 slot_name(p_slot)); 624 648 break; 625 649 default: 626 - ctrl_err(ctrl, "Not a valid state on slot %s\n", 627 - slot_name(p_slot)); 650 + ctrl_err(ctrl, "invalid state %#x on slot %s\n", 651 + p_slot->state, slot_name(p_slot)); 628 652 break; 629 653 } 630 654 mutex_unlock(&p_slot->lock); ··· 658 682 slot_name(p_slot)); 659 683 break; 660 684 default: 661 - ctrl_err(ctrl, "Not a valid state on slot %s\n", 662 - slot_name(p_slot)); 685 + ctrl_err(ctrl, "invalid state %#x on slot %s\n", 686 + p_slot->state, slot_name(p_slot)); 663 687 break; 664 688 } 665 689 mutex_unlock(&p_slot->lock);
+10 -44
drivers/pci/hotplug/pciehp_hpc.c
··· 312 312 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 313 313 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 314 314 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 315 - ctrl_err(ctrl, "Link Training Error occurs\n"); 315 + ctrl_err(ctrl, "link training error: status %#06x\n", 316 + lnk_status); 316 317 return -1; 317 318 } 318 319 ··· 557 556 intr_loc); 558 557 } while (detected); 559 558 560 - ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 559 + ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc); 561 560 562 561 /* Check Command Complete Interrupt Pending */ 563 562 if (intr_loc & PCI_EXP_SLTSTA_CC) { ··· 749 748 750 749 static inline void dbg_ctrl(struct controller *ctrl) 751 750 { 752 - int i; 753 - u16 reg16; 754 751 struct pci_dev *pdev = ctrl->pcie->port; 752 + u16 reg16; 755 753 756 754 if (!pciehp_debug) 757 755 return; 758 756 759 - ctrl_info(ctrl, "Hotplug Controller:\n"); 760 - ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 761 - pci_name(pdev), pdev->irq); 762 - ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 763 - ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 764 - ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 765 - pdev->subsystem_device); 766 - ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 767 - pdev->subsystem_vendor); 768 - ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", 769 - pci_pcie_cap(pdev)); 770 - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 771 - if (!pci_resource_len(pdev, i)) 772 - continue; 773 - ctrl_info(ctrl, " PCI resource [%d] : %pR\n", 774 - i, &pdev->resource[i]); 775 - } 776 757 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 777 - ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 778 - ctrl_info(ctrl, " Attention Button : %3s\n", 779 - ATTN_BUTTN(ctrl) ? "yes" : "no"); 780 - ctrl_info(ctrl, " Power Controller : %3s\n", 781 - POWER_CTRL(ctrl) ? "yes" : "no"); 782 - ctrl_info(ctrl, " MRL Sensor : %3s\n", 783 - MRL_SENS(ctrl) ? "yes" : "no"); 784 - ctrl_info(ctrl, " Attention Indicator : %3s\n", 785 - ATTN_LED(ctrl) ? "yes" : "no"); 786 - ctrl_info(ctrl, " Power Indicator : %3s\n", 787 - PWR_LED(ctrl) ? "yes" : "no"); 788 - ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 789 - HP_SUPR_RM(ctrl) ? "yes" : "no"); 790 - ctrl_info(ctrl, " EMI Present : %3s\n", 791 - EMI(ctrl) ? "yes" : "no"); 792 - ctrl_info(ctrl, " Command Completed : %3s\n", 793 - NO_CMD_CMPL(ctrl) ? "no" : "yes"); 794 758 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16); 795 759 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 796 760 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16); ··· 784 818 785 819 /* Check if Data Link Layer Link Active Reporting is implemented */ 786 820 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 787 - if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 788 - ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 821 + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) 789 822 ctrl->link_active_reporting = 1; 790 - } 791 823 792 824 /* Clear all remaining event bits in Slot Status register */ 793 825 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, ··· 793 829 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 794 830 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); 795 831 796 - ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", 832 + ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n", 797 833 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 798 834 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 799 - FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 800 - FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 801 835 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 802 836 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 837 + FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 838 + FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 839 + FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), 840 + FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), 803 841 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 804 842 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 805 843 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));