tjh.dev / kernel
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crypto: hisilicon - modify the value of engine type rate

Modify the value of type rate from new QM spec.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Kai Ye and committed by
Herbert Xu 376a5c3c d3b04a43

+4 -4
+1 -1
drivers/crypto/hisilicon/hpre/hpre_main.c
··· 103 103 #define HPRE_QM_PM_FLR BIT(11) 104 104 #define HPRE_QM_SRIOV_FLR BIT(12) 105 105 106 - #define HPRE_SHAPER_TYPE_RATE 128 106 + #define HPRE_SHAPER_TYPE_RATE 640 107 107 #define HPRE_VIA_MSI_DSM 1 108 108 #define HPRE_SQE_MASK_OFFSET 8 109 109 #define HPRE_SQE_MASK_LEN 24
+1 -1
drivers/crypto/hisilicon/sec2/sec_main.c
··· 105 105 106 106 #define SEC_SQE_MASK_OFFSET 64 107 107 #define SEC_SQE_MASK_LEN 48 108 - #define SEC_SHAPER_TYPE_RATE 128 108 + #define SEC_SHAPER_TYPE_RATE 400 109 109 110 110 struct sec_hw_error { 111 111 u32 int_msk;
+2 -2
drivers/crypto/hisilicon/zip/zip_main.c
··· 103 103 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 104 104 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 105 105 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 106 - #define HZIP_SHAPER_RATE_COMPRESS 252 107 - #define HZIP_SHAPER_RATE_DECOMPRESS 229 106 + #define HZIP_SHAPER_RATE_COMPRESS 750 107 + #define HZIP_SHAPER_RATE_DECOMPRESS 140 108 108 #define HZIP_DELAY_1_US 1 109 109 #define HZIP_POLL_TIMEOUT_US 1000 110 110