tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-fixes-2020-07-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.8-rc4:
- GVT fixes
- Include asm sources for render cache clear batches
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87imf7l6ee.fsf@intel.com
+304
-15
+46
drivers/gpu/drm/i915/gt/shaders/README
+46
drivers/gpu/drm/i915/gt/shaders/README
···
1
+
ASM sources for auto generated shaders
2
+
======================================
3
+
4
+
The i915/gt/hsw_clear_kernel.c and i915/gt/ivb_clear_kernel.c files contain
5
+
pre-compiled batch chunks that will clear any residual render cache during
6
+
context switch.
7
+
8
+
They are generated from their respective platform ASM files present on
9
+
i915/gt/shaders/clear_kernel directory.
10
+
11
+
The generated .c files should never be modified directly. Instead, any modification
12
+
needs to be done on the on their respective ASM files and build instructions below
13
+
needes to be followed.
14
+
15
+
Building
16
+
========
17
+
18
+
Environment
19
+
-----------
20
+
21
+
IGT GPU tool scripts and the Mesa's i965 instruction assembler tool are used
22
+
on building.
23
+
24
+
Please make sure your Mesa tool is compiled with "-Dtools=intel" and
25
+
"-Ddri-drivers=i965", and run this script from IGT source root directory"
26
+
27
+
The instructions bellow assume:
28
+
* IGT gpu tools source code is located on your home directory (~) as ~/igt
29
+
* Mesa source code is located on your home directory (~) as ~/mesa
30
+
and built under the ~/mesa/build directory
31
+
* Linux kernel source code is under your home directory (~) as ~/linux
32
+
33
+
Instructions
34
+
------------
35
+
36
+
~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm \
37
+
~/igt/lib/i915/shaders/clear_kernel/ivb.asm
38
+
~ $ cd ~/igt
39
+
igt $ ./scripts/generate_clear_kernel.sh -g ivb \
40
+
-m ~/mesa/build/src/intel/tools/i965_asm
41
+
42
+
~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \
43
+
~/igt/lib/i915/shaders/clear_kernel/hsw.asm
44
+
~ $ cd ~/igt
45
+
igt $ ./scripts/generate_clear_kernel.sh -g hsw \
46
+
-m ~/mesa/build/src/intel/tools/i965_asm
+119
drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
+119
drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2020 Intel Corporation
4
+
*/
5
+
6
+
/*
7
+
* Kernel for PAVP buffer clear.
8
+
*
9
+
* 1. Clear all 64 GRF registers assigned to the kernel with designated value;
10
+
* 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11
+
* 512 bytes of Render Cache.
12
+
*/
13
+
14
+
/* Store designated "clear GRF" value */
15
+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
16
+
17
+
/**
18
+
* Curbe Format
19
+
*
20
+
* DW 1.0 - Block Offset to write Render Cache
21
+
* DW 1.1 [15:0] - Clear Word
22
+
* DW 1.2 - Delay iterations
23
+
* DW 1.3 - Enable Instrumentation (only for debug)
24
+
* DW 1.4 - Rsvd (intended for context ID)
25
+
* DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26
+
* DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
27
+
* DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
28
+
*
29
+
* Binding Table
30
+
*
31
+
* BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
32
+
* BTI 1: Wait/Instrumentation Buffer
33
+
* Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
34
+
* Expected to be initialized to 0 by driver/another kernel
35
+
* Layout:
36
+
* RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
37
+
* Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
38
+
*/
39
+
add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
40
+
cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
41
+
(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
42
+
43
+
/**
44
+
* State Register has info on where this thread is running
45
+
* IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
46
+
* HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
47
+
*/
48
+
mov(8) g3<1>UD 0x00000000UD { align1 1Q };
49
+
shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
50
+
and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
51
+
shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
52
+
and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
53
+
mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
54
+
add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
55
+
shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
56
+
and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
57
+
mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
58
+
add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
59
+
60
+
mov(8) g5<1>UD 0x00000000UD { align1 1Q };
61
+
and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
62
+
mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
63
+
64
+
mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
65
+
mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
66
+
mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
67
+
mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
68
+
and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
69
+
70
+
/* Media block read to fetch current value at specified location in instrumentation buffer */
71
+
sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
72
+
73
+
render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
74
+
add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
75
+
76
+
/* Media block write for updated value at specified location in instrumentation buffer */
77
+
sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
78
+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
79
+
80
+
/* Delay thread for specified parameter */
81
+
add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
82
+
(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
83
+
84
+
/* Store designated "clear GRF" value */
85
+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
86
+
87
+
/* Initialize looping parameters */
88
+
mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
89
+
mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
90
+
91
+
/* Write 32x16 all "0" block */
92
+
mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
93
+
mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
94
+
mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
95
+
mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
96
+
and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
97
+
mov(16) g3<1>UD 0x00000000UD { align1 1H };
98
+
mov(16) g4<1>UD 0x00000000UD { align1 1H };
99
+
mov(16) g5<1>UD 0x00000000UD { align1 1H };
100
+
mov(16) g6<1>UD 0x00000000UD { align1 1H };
101
+
mov(16) g7<1>UD 0x00000000UD { align1 1H };
102
+
mov(16) g8<1>UD 0x00000000UD { align1 1H };
103
+
mov(16) g9<1>UD 0x00000000UD { align1 1H };
104
+
mov(16) g10<1>UD 0x00000000UD { align1 1H };
105
+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
106
+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
107
+
add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
108
+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
109
+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
110
+
111
+
/* Now, clear all GRF registers */
112
+
add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
113
+
mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
114
+
add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
115
+
(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
116
+
117
+
/* Terminante the thread */
118
+
sendc(8) null<1>UD g127<8,8,1>F 0x82000010
119
+
thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
+117
drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
+117
drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2020 Intel Corporation
4
+
*/
5
+
6
+
/*
7
+
* Kernel for PAVP buffer clear.
8
+
*
9
+
* 1. Clear all 64 GRF registers assigned to the kernel with designated value;
10
+
* 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11
+
* 512 bytes of Render Cache.
12
+
*/
13
+
14
+
/* Store designated "clear GRF" value */
15
+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
16
+
17
+
/**
18
+
* Curbe Format
19
+
*
20
+
* DW 1.0 - Block Offset to write Render Cache
21
+
* DW 1.1 [15:0] - Clear Word
22
+
* DW 1.2 - Delay iterations
23
+
* DW 1.3 - Enable Instrumentation (only for debug)
24
+
* DW 1.4 - Rsvd (intended for context ID)
25
+
* DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26
+
* DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
27
+
* DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
28
+
*
29
+
* Binding Table
30
+
*
31
+
* BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
32
+
* BTI 1: Wait/Instrumentation Buffer
33
+
* Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
34
+
* Expected to be initialized to 0 by driver/another kernel
35
+
* Layout :
36
+
* RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
37
+
* Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
38
+
*/
39
+
add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
40
+
cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
41
+
(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
42
+
43
+
/**
44
+
* State Register has info on where this thread is running
45
+
* IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
46
+
* HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
47
+
*/
48
+
mov(8) g3<1>UD 0x00000000UD { align1 1Q };
49
+
shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
50
+
and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
51
+
shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
52
+
and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
53
+
mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
54
+
add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
55
+
shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
56
+
and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
57
+
mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
58
+
add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
59
+
60
+
mov(8) g5<1>UD 0x00000000UD { align1 1Q };
61
+
and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
62
+
mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
63
+
64
+
mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
65
+
mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
66
+
mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
67
+
mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
68
+
and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
69
+
70
+
/* Media block read to fetch current value at specified location in instrumentation buffer */
71
+
sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
72
+
render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
73
+
add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
74
+
75
+
/* Media block write for updated value at specified location in instrumentation buffer */
76
+
sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
77
+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
78
+
/* Delay thread for specified parameter */
79
+
add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
80
+
(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
81
+
82
+
/* Store designated "clear GRF" value */
83
+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
84
+
85
+
/* Initialize looping parameters */
86
+
mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
87
+
mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
88
+
89
+
/* Write 32x16 all "0" block */
90
+
mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
91
+
mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
92
+
mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
93
+
mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
94
+
and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
95
+
mov(16) g3<1>UD 0x00000000UD { align1 1H };
96
+
mov(16) g4<1>UD 0x00000000UD { align1 1H };
97
+
mov(16) g5<1>UD 0x00000000UD { align1 1H };
98
+
mov(16) g6<1>UD 0x00000000UD { align1 1H };
99
+
mov(16) g7<1>UD 0x00000000UD { align1 1H };
100
+
mov(16) g8<1>UD 0x00000000UD { align1 1H };
101
+
mov(16) g9<1>UD 0x00000000UD { align1 1H };
102
+
mov(16) g10<1>UD 0x00000000UD { align1 1H };
103
+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
104
+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
105
+
add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
106
+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
107
+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
108
+
109
+
/* Now, clear all GRF registers */
110
+
add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
111
+
mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
112
+
add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
113
+
(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
114
+
115
+
/* Terminante the thread */
116
+
sendc(8) null<1>UD g127<8,8,1>F 0x82000010
117
+
thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
+1
-1
drivers/gpu/drm/i915/gvt/debugfs.c
+1
-1
drivers/gpu/drm/i915/gvt/debugfs.c
+13
-11
drivers/gpu/drm/i915/gvt/handlers.c
+13
-11
drivers/gpu/drm/i915/gvt/handlers.c
···
1726
1726
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
1727
1727
write_vreg(vgpu, offset, p_data, bytes);
1728
1728
1729
-
if (data & _MASKED_BIT_ENABLE(1)) {
1729
+
if (IS_MASKED_BITS_ENABLED(data, 1)) {
1730
1730
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1731
1731
return 0;
1732
1732
}
1733
1733
1734
1734
if (IS_COFFEELAKE(vgpu->gvt->gt->i915) &&
1735
-
data & _MASKED_BIT_ENABLE(2)) {
1735
+
IS_MASKED_BITS_ENABLED(data, 2)) {
1736
1736
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1737
1737
return 0;
1738
1738
}
···
1741
1741
* pvinfo, if not, we will treat this guest as non-gvtg-aware
1742
1742
* guest, and stop emulating its cfg space, mmio, gtt, etc.
1743
1743
*/
1744
-
if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1745
-
(data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1746
-
&& !vgpu->pv_notified) {
1744
+
if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
1745
+
IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
1746
+
!vgpu->pv_notified) {
1747
1747
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1748
1748
return 0;
1749
1749
}
1750
-
if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1751
-
|| (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1750
+
if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
1751
+
IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
1752
1752
enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1753
1753
1754
1754
gvt_dbg_core("EXECLIST %s on ring %s\n",
···
1809
1809
write_vreg(vgpu, offset, p_data, bytes);
1810
1810
data = vgpu_vreg(vgpu, offset);
1811
1811
1812
-
if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1812
+
if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
1813
1813
data |= RESET_CTL_READY_TO_RESET;
1814
1814
else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1815
1815
data &= ~RESET_CTL_READY_TO_RESET;
···
1827
1827
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1828
1828
write_vreg(vgpu, offset, p_data, bytes);
1829
1829
1830
-
if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
1830
+
if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
1831
+
IS_MASKED_BITS_ENABLED(data, 0x8))
1831
1832
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1832
1833
1833
1834
return 0;
···
3056
3055
MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
3057
3056
MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
3058
3057
MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
3058
+
MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
3059
3059
3060
3060
MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3061
3061
MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
···
3133
3131
MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3134
3132
NULL, NULL);
3135
3133
3136
-
MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
3137
-
MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
3134
+
MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
3135
+
MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
3138
3136
3139
3137
return 0;
3140
3138
}
+3
-3
drivers/gpu/drm/i915/gvt/mmio_context.h
+3
-3
drivers/gpu/drm/i915/gvt/mmio_context.h
···
54
54
55
55
int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
56
56
struct i915_request *req);
57
-
#define IS_RESTORE_INHIBIT(a) \
58
-
(_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
59
-
((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
57
+
58
+
#define IS_RESTORE_INHIBIT(a) \
59
+
IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)
60
60
61
61
#endif
+5
drivers/gpu/drm/i915/gvt/reg.h
+5
drivers/gpu/drm/i915/gvt/reg.h
···
94
94
#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
95
95
((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
96
96
97
+
#define IS_MASKED_BITS_ENABLED(_val, _b) \
98
+
(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
99
+
#define IS_MASKED_BITS_DISABLED(_val, _b) \
100
+
((_val) & _MASKED_BIT_DISABLE(_b))
101
+
97
102
#define FORCEWAKE_RENDER_GEN9_REG 0xa278
98
103
#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
99
104
#define FORCEWAKE_BLITTER_GEN9_REG 0xa188