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Merge tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt

From Stephen Warren:
ARM: tegra: device tree updates

This branch contains all device tree updates for Tegra boards.

The changes are:

* Converted all DT files to use the C pre-processor, to support the use
of named constants. This included use of defines for GPIO, IRQ, and
clock constants.
* Enabling new features such as:
- SPI on Dalmore.
- Audio on Dalmore and Beaver.
- gpio-leds on Beaver.
- Power-supply/batter linkage on Dalmore.
* A minor fix to the RAM size node on Beaver.

It is based on previous pull request tegra-for-3.11-deps-for-usb
followed by a merge of tegra-for-3.11-deps-for-clk.

* tag 'tegra-for-3.11-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (21 commits)
ARM: tegra: enable audio on Beaver
ARM: tegra: enable audio on Dalmore
ARM: tegra: add power-supplies link between battery and charger
ARM: tegra: add audio-related nodes to Tegra114 DT
ARM: tegra114: convert device tree files to use CLK defines
ARM: tegra30: convert device tree files to use CLK defines
ARM: tegra20: convert device tree files to use CLK defines
ARM: tegra: Add charger subnode to tps65090 node
ARM: tegra: convert device tree files to use IRQ defines
ARM: tegra: convert device tree files to use GPIO defines
ARM: tegra: create a DT header defining GPIO IDs
ARM: tegra: use #include for all device trees
ARM: tegra: Add gpio-leds to Tegra30 Beaver
ARM: tegra: fix memory size on Beaver
ARM: tegra: enable spi4 on Dalmore
ARM: tegra114: create a DT header defining CLK IDs
ARM: tegra30: create a DT header defining CLK IDs
ARM: tegra20: create a DT header defining CLK IDs
ARM: tegra: update device trees for USB binding rework
ARM: tegra: modify ULPI reset GPIO properties
...

Signed-off-by: Olof Johansson <olof@lixom.net>

Olof Johansson 36d29fb5 3b2e6296

+1818 -1181
+4 -248
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
··· 12 12 - clocks : Should contain phandle and clock specifiers for two clocks: 13 13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 14 14 - #clock-cells : Should be 1. 15 - In clock consumers, this cell represents the clock ID exposed by the CAR. 16 - 17 - The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 18 - registers. These IDs often match those in the CAR's RST_DEVICES registers, 19 - but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 20 - this case, those clocks are assigned IDs above 160 in order to highlight 21 - this issue. Implementations that interpret these clock IDs as bit values 22 - within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 23 - explicitly handle these special cases. 24 - 25 - The balance of the clocks controlled by the CAR are assigned IDs of 160 and 26 - above. 27 - 28 - 0 unassigned 29 - 1 unassigned 30 - 2 unassigned 31 - 3 unassigned 32 - 4 rtc 33 - 5 timer 34 - 6 uarta 35 - 7 unassigned (register bit affects uartb and vfir) 36 - 8 unassigned 37 - 9 sdmmc2 38 - 10 unassigned (register bit affects spdif_in and spdif_out) 39 - 11 i2s1 40 - 12 i2c1 41 - 13 ndflash 42 - 14 sdmmc1 43 - 15 sdmmc4 44 - 16 unassigned 45 - 17 pwm 46 - 18 i2s2 47 - 19 epp 48 - 20 unassigned (register bit affects vi and vi_sensor) 49 - 21 2d 50 - 22 usbd 51 - 23 isp 52 - 24 3d 53 - 25 unassigned 54 - 26 disp2 55 - 27 disp1 56 - 28 host1x 57 - 29 vcp 58 - 30 i2s0 59 - 31 unassigned 60 - 61 - 32 unassigned 62 - 33 unassigned 63 - 34 apbdma 64 - 35 unassigned 65 - 36 kbc 66 - 37 unassigned 67 - 38 unassigned 68 - 39 unassigned (register bit affects fuse and fuse_burn) 69 - 40 kfuse 70 - 41 sbc1 71 - 42 nor 72 - 43 unassigned 73 - 44 sbc2 74 - 45 unassigned 75 - 46 sbc3 76 - 47 i2c5 77 - 48 dsia 78 - 49 unassigned 79 - 50 mipi 80 - 51 hdmi 81 - 52 csi 82 - 53 unassigned 83 - 54 i2c2 84 - 55 uartc 85 - 56 mipi-cal 86 - 57 emc 87 - 58 usb2 88 - 59 usb3 89 - 60 msenc 90 - 61 vde 91 - 62 bsea 92 - 63 bsev 93 - 94 - 64 unassigned 95 - 65 uartd 96 - 66 unassigned 97 - 67 i2c3 98 - 68 sbc4 99 - 69 sdmmc3 100 - 70 unassigned 101 - 71 owr 102 - 72 afi 103 - 73 csite 104 - 74 unassigned 105 - 75 unassigned 106 - 76 la 107 - 77 trace 108 - 78 soc_therm 109 - 79 dtv 110 - 80 ndspeed 111 - 81 i2cslow 112 - 82 dsib 113 - 83 tsec 114 - 84 unassigned 115 - 85 unassigned 116 - 86 unassigned 117 - 87 unassigned 118 - 88 unassigned 119 - 89 xusb_host 120 - 90 unassigned 121 - 91 msenc 122 - 92 csus 123 - 93 unassigned 124 - 94 unassigned 125 - 95 unassigned (bit affects xusb_dev and xusb_dev_src) 126 - 127 - 96 unassigned 128 - 97 unassigned 129 - 98 unassigned 130 - 99 mselect 131 - 100 tsensor 132 - 101 i2s3 133 - 102 i2s4 134 - 103 i2c4 135 - 104 sbc5 136 - 105 sbc6 137 - 106 d_audio 138 - 107 apbif 139 - 108 dam0 140 - 109 dam1 141 - 110 dam2 142 - 111 hda2codec_2x 143 - 112 unassigned 144 - 113 audio0_2x 145 - 114 audio1_2x 146 - 115 audio2_2x 147 - 116 audio3_2x 148 - 117 audio4_2x 149 - 118 spdif_2x 150 - 119 actmon 151 - 120 extern1 152 - 121 extern2 153 - 122 extern3 154 - 123 unassigned 155 - 124 unassigned 156 - 125 hda 157 - 126 unassigned 158 - 127 se 159 - 160 - 128 hda2hdmi 161 - 129 unassigned 162 - 130 unassigned 163 - 131 unassigned 164 - 132 unassigned 165 - 133 unassigned 166 - 134 unassigned 167 - 135 unassigned 168 - 136 unassigned 169 - 137 unassigned 170 - 138 unassigned 171 - 139 unassigned 172 - 140 unassigned 173 - 141 unassigned 174 - 142 unassigned 175 - 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src, 176 - xusb_host_src and xusb_ss_src) 177 - 144 cilab 178 - 145 cilcd 179 - 146 cile 180 - 147 dsialp 181 - 148 dsiblp 182 - 149 unassigned 183 - 150 dds 184 - 151 unassigned 185 - 152 dp2 186 - 153 amx 187 - 154 adx 188 - 155 unassigned (bit affects dfll_ref and dfll_soc) 189 - 156 xusb_ss 190 - 191 - 192 uartb 192 - 193 vfir 193 - 194 spdif_in 194 - 195 spdif_out 195 - 196 vi 196 - 197 vi_sensor 197 - 198 fuse 198 - 199 fuse_burn 199 - 200 clk_32k 200 - 201 clk_m 201 - 202 clk_m_div2 202 - 203 clk_m_div4 203 - 204 pll_ref 204 - 205 pll_c 205 - 206 pll_c_out1 206 - 207 pll_c2 207 - 208 pll_c3 208 - 209 pll_m 209 - 210 pll_m_out1 210 - 211 pll_p 211 - 212 pll_p_out1 212 - 213 pll_p_out2 213 - 214 pll_p_out3 214 - 215 pll_p_out4 215 - 216 pll_a 216 - 217 pll_a_out0 217 - 218 pll_d 218 - 219 pll_d_out0 219 - 220 pll_d2 220 - 221 pll_d2_out0 221 - 222 pll_u 222 - 223 pll_u_480M 223 - 224 pll_u_60M 224 - 225 pll_u_48M 225 - 226 pll_u_12M 226 - 227 pll_x 227 - 228 pll_x_out0 228 - 229 pll_re_vco 229 - 230 pll_re_out 230 - 231 pll_e_out0 231 - 232 spdif_in_sync 232 - 233 i2s0_sync 233 - 234 i2s1_sync 234 - 235 i2s2_sync 235 - 236 i2s3_sync 236 - 237 i2s4_sync 237 - 238 vimclk_sync 238 - 239 audio0 239 - 240 audio1 240 - 241 audio2 241 - 242 audio3 242 - 243 audio4 243 - 244 spdif 244 - 245 clk_out_1 245 - 246 clk_out_2 246 - 247 clk_out_3 247 - 248 blink 248 - 252 xusb_host_src 249 - 253 xusb_falcon_src 250 - 254 xusb_fs_src 251 - 255 xusb_ss_src 252 - 256 xusb_dev_src 253 - 257 xusb_dev 254 - 258 xusb_hs_src 255 - 259 sclk 256 - 260 hclk 257 - 261 pclk 258 - 262 cclk_g 259 - 263 cclk_lp 260 - 264 dfll_ref 261 - 265 dfll_soc 15 + In clock consumers, this cell represents the clock ID exposed by the 16 + CAR. The assignments may be found in header file 17 + <dt-bindings/clock/tegra114-car.h>. 262 18 263 19 Example SoC include file: 264 20 ··· 26 270 }; 27 271 28 272 usb@c5004000 { 29 - clocks = <&tegra_car 58>; /* usb2 */ 273 + clocks = <&tegra_car TEGRA114_CLK_USB2>; 30 274 }; 31 275 }; 32 276
+4 -150
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
··· 12 12 - clocks : Should contain phandle and clock specifiers for two clocks: 13 13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 14 14 - #clock-cells : Should be 1. 15 - In clock consumers, this cell represents the clock ID exposed by the CAR. 16 - 17 - The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 18 - registers. These IDs often match those in the CAR's RST_DEVICES registers, 19 - but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 20 - this case, those clocks are assigned IDs above 95 in order to highlight 21 - this issue. Implementations that interpret these clock IDs as bit values 22 - within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 23 - explicitly handle these special cases. 24 - 25 - The balance of the clocks controlled by the CAR are assigned IDs of 96 and 26 - above. 27 - 28 - 0 cpu 29 - 1 unassigned 30 - 2 unassigned 31 - 3 ac97 32 - 4 rtc 33 - 5 tmr 34 - 6 uart1 35 - 7 unassigned (register bit affects uart2 and vfir) 36 - 8 gpio 37 - 9 sdmmc2 38 - 10 unassigned (register bit affects spdif_in and spdif_out) 39 - 11 i2s1 40 - 12 i2c1 41 - 13 ndflash 42 - 14 sdmmc1 43 - 15 sdmmc4 44 - 16 twc 45 - 17 pwm 46 - 18 i2s2 47 - 19 epp 48 - 20 unassigned (register bit affects vi and vi_sensor) 49 - 21 2d 50 - 22 usbd 51 - 23 isp 52 - 24 3d 53 - 25 ide 54 - 26 disp2 55 - 27 disp1 56 - 28 host1x 57 - 29 vcp 58 - 30 unassigned 59 - 31 cache2 60 - 61 - 32 mem 62 - 33 ahbdma 63 - 34 apbdma 64 - 35 unassigned 65 - 36 kbc 66 - 37 stat_mon 67 - 38 pmc 68 - 39 fuse 69 - 40 kfuse 70 - 41 sbc1 71 - 42 snor 72 - 43 spi1 73 - 44 sbc2 74 - 45 xio 75 - 46 sbc3 76 - 47 dvc 77 - 48 dsi 78 - 49 unassigned (register bit affects tvo and cve) 79 - 50 mipi 80 - 51 hdmi 81 - 52 csi 82 - 53 tvdac 83 - 54 i2c2 84 - 55 uart3 85 - 56 unassigned 86 - 57 emc 87 - 58 usb2 88 - 59 usb3 89 - 60 mpe 90 - 61 vde 91 - 62 bsea 92 - 63 bsev 93 - 94 - 64 speedo 95 - 65 uart4 96 - 66 uart5 97 - 67 i2c3 98 - 68 sbc4 99 - 69 sdmmc3 100 - 70 pcie 101 - 71 owr 102 - 72 afi 103 - 73 csite 104 - 74 unassigned 105 - 75 avpucq 106 - 76 la 107 - 77 unassigned 108 - 78 unassigned 109 - 79 unassigned 110 - 80 unassigned 111 - 81 unassigned 112 - 82 unassigned 113 - 83 unassigned 114 - 84 irama 115 - 85 iramb 116 - 86 iramc 117 - 87 iramd 118 - 88 cram2 119 - 89 audio_2x a/k/a audio_2x_sync_clk 120 - 90 clk_d 121 - 91 unassigned 122 - 92 sus 123 - 93 cdev2 124 - 94 cdev1 125 - 95 unassigned 126 - 127 - 96 uart2 128 - 97 vfir 129 - 98 spdif_in 130 - 99 spdif_out 131 - 100 vi 132 - 101 vi_sensor 133 - 102 tvo 134 - 103 cve 135 - 104 osc 136 - 105 clk_32k a/k/a clk_s 137 - 106 clk_m 138 - 107 sclk 139 - 108 cclk 140 - 109 hclk 141 - 110 pclk 142 - 111 blink 143 - 112 pll_a 144 - 113 pll_a_out0 145 - 114 pll_c 146 - 115 pll_c_out1 147 - 116 pll_d 148 - 117 pll_d_out0 149 - 118 pll_e 150 - 119 pll_m 151 - 120 pll_m_out1 152 - 121 pll_p 153 - 122 pll_p_out1 154 - 123 pll_p_out2 155 - 124 pll_p_out3 156 - 125 pll_p_out4 157 - 126 pll_s 158 - 127 pll_u 159 - 128 pll_x 160 - 129 cop a/k/a avp 161 - 130 audio a/k/a audio_sync_clk 162 - 131 pll_ref 163 - 132 twd 15 + In clock consumers, this cell represents the clock ID exposed by the 16 + CAR. The assignments may be found in header file 17 + <dt-bindings/clock/tegra20-car.h>. 164 18 165 19 Example SoC include file: 166 20 ··· 26 172 }; 27 173 28 174 usb@c5004000 { 29 - clocks = <&tegra_car 58>; /* usb2 */ 175 + clocks = <&tegra_car TEGRA20_CLK_USB2>; 30 176 }; 31 177 }; 32 178
+4 -207
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
··· 12 12 - clocks : Should contain phandle and clock specifiers for two clocks: 13 13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 14 14 - #clock-cells : Should be 1. 15 - In clock consumers, this cell represents the clock ID exposed by the CAR. 16 - 17 - The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 18 - registers. These IDs often match those in the CAR's RST_DEVICES registers, 19 - but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 20 - this case, those clocks are assigned IDs above 160 in order to highlight 21 - this issue. Implementations that interpret these clock IDs as bit values 22 - within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 23 - explicitly handle these special cases. 24 - 25 - The balance of the clocks controlled by the CAR are assigned IDs of 160 and 26 - above. 27 - 28 - 0 cpu 29 - 1 unassigned 30 - 2 unassigned 31 - 3 unassigned 32 - 4 rtc 33 - 5 timer 34 - 6 uarta 35 - 7 unassigned (register bit affects uartb and vfir) 36 - 8 gpio 37 - 9 sdmmc2 38 - 10 unassigned (register bit affects spdif_in and spdif_out) 39 - 11 i2s1 40 - 12 i2c1 41 - 13 ndflash 42 - 14 sdmmc1 43 - 15 sdmmc4 44 - 16 unassigned 45 - 17 pwm 46 - 18 i2s2 47 - 19 epp 48 - 20 unassigned (register bit affects vi and vi_sensor) 49 - 21 2d 50 - 22 usbd 51 - 23 isp 52 - 24 3d 53 - 25 unassigned 54 - 26 disp2 55 - 27 disp1 56 - 28 host1x 57 - 29 vcp 58 - 30 i2s0 59 - 31 cop_cache 60 - 61 - 32 mc 62 - 33 ahbdma 63 - 34 apbdma 64 - 35 unassigned 65 - 36 kbc 66 - 37 statmon 67 - 38 pmc 68 - 39 unassigned (register bit affects fuse and fuse_burn) 69 - 40 kfuse 70 - 41 sbc1 71 - 42 nor 72 - 43 unassigned 73 - 44 sbc2 74 - 45 unassigned 75 - 46 sbc3 76 - 47 i2c5 77 - 48 dsia 78 - 49 unassigned (register bit affects cve and tvo) 79 - 50 mipi 80 - 51 hdmi 81 - 52 csi 82 - 53 tvdac 83 - 54 i2c2 84 - 55 uartc 85 - 56 unassigned 86 - 57 emc 87 - 58 usb2 88 - 59 usb3 89 - 60 mpe 90 - 61 vde 91 - 62 bsea 92 - 63 bsev 93 - 94 - 64 speedo 95 - 65 uartd 96 - 66 uarte 97 - 67 i2c3 98 - 68 sbc4 99 - 69 sdmmc3 100 - 70 pcie 101 - 71 owr 102 - 72 afi 103 - 73 csite 104 - 74 pciex 105 - 75 avpucq 106 - 76 la 107 - 77 unassigned 108 - 78 unassigned 109 - 79 dtv 110 - 80 ndspeed 111 - 81 i2cslow 112 - 82 dsib 113 - 83 unassigned 114 - 84 irama 115 - 85 iramb 116 - 86 iramc 117 - 87 iramd 118 - 88 cram2 119 - 89 unassigned 120 - 90 audio_2x a/k/a audio_2x_sync_clk 121 - 91 unassigned 122 - 92 csus 123 - 93 cdev2 124 - 94 cdev1 125 - 95 unassigned 126 - 127 - 96 cpu_g 128 - 97 cpu_lp 129 - 98 3d2 130 - 99 mselect 131 - 100 tsensor 132 - 101 i2s3 133 - 102 i2s4 134 - 103 i2c4 135 - 104 sbc5 136 - 105 sbc6 137 - 106 d_audio 138 - 107 apbif 139 - 108 dam0 140 - 109 dam1 141 - 110 dam2 142 - 111 hda2codec_2x 143 - 112 atomics 144 - 113 audio0_2x 145 - 114 audio1_2x 146 - 115 audio2_2x 147 - 116 audio3_2x 148 - 117 audio4_2x 149 - 118 audio5_2x 150 - 119 actmon 151 - 120 extern1 152 - 121 extern2 153 - 122 extern3 154 - 123 sata_oob 155 - 124 sata 156 - 125 hda 157 - 127 se 158 - 128 hda2hdmi 159 - 129 sata_cold 160 - 161 - 160 uartb 162 - 161 vfir 163 - 162 spdif_in 164 - 163 spdif_out 165 - 164 vi 166 - 165 vi_sensor 167 - 166 fuse 168 - 167 fuse_burn 169 - 168 cve 170 - 169 tvo 171 - 172 - 170 clk_32k 173 - 171 clk_m 174 - 172 clk_m_div2 175 - 173 clk_m_div4 176 - 174 pll_ref 177 - 175 pll_c 178 - 176 pll_c_out1 179 - 177 pll_m 180 - 178 pll_m_out1 181 - 179 pll_p 182 - 180 pll_p_out1 183 - 181 pll_p_out2 184 - 182 pll_p_out3 185 - 183 pll_p_out4 186 - 184 pll_a 187 - 185 pll_a_out0 188 - 186 pll_d 189 - 187 pll_d_out0 190 - 188 pll_d2 191 - 189 pll_d2_out0 192 - 190 pll_u 193 - 191 pll_x 194 - 192 pll_x_out0 195 - 193 pll_e 196 - 194 spdif_in_sync 197 - 195 i2s0_sync 198 - 196 i2s1_sync 199 - 197 i2s2_sync 200 - 198 i2s3_sync 201 - 199 i2s4_sync 202 - 200 vimclk 203 - 201 audio0 204 - 202 audio1 205 - 203 audio2 206 - 204 audio3 207 - 205 audio4 208 - 206 audio5 209 - 207 clk_out_1 (extern1) 210 - 208 clk_out_2 (extern2) 211 - 209 clk_out_3 (extern3) 212 - 210 sclk 213 - 211 blink 214 - 212 cclk_g 215 - 213 cclk_lp 216 - 214 twd 217 - 215 cml0 218 - 216 cml1 219 - 217 hclk 220 - 218 pclk 15 + In clock consumers, this cell represents the clock ID exposed by the 16 + CAR. The assignments may be found in header file 17 + <dt-bindings/clock/tegra30-car.h>. 221 18 222 19 Example SoC include file: 223 20 ··· 26 229 }; 27 230 28 231 usb@c5004000 { 29 - clocks = <&tegra_car 58>; /* usb2 */ 232 + clocks = <&tegra_car TEGRA30_CLK_USB2>; 30 233 }; 31 234 }; 32 235
+5 -22
Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
··· 6 6 and additions : 7 7 8 8 Required properties : 9 - - compatible : Should be "nvidia,tegra20-ehci" for USB controllers 10 - used in host mode. 11 - - phy_type : Should be one of "ulpi" or "utmi". 12 - - nvidia,vbus-gpio : If present, specifies a gpio that needs to be 13 - activated for the bus to be powered. 14 - - nvidia,phy : phandle of the PHY instance, the controller is connected to. 15 - 16 - Required properties for phy_type == ulpi: 17 - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 9 + - compatible : Should be "nvidia,tegra20-ehci". 10 + - nvidia,phy : phandle of the PHY that the controller is connected to. 11 + - clocks : Contains a single entry which defines the USB controller's clock. 18 12 19 13 Optional properties: 20 - - dr_mode : dual role mode. Indicates the working mode for 21 - nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", 22 - or "otg". Default to "host" if not defined for backward compatibility. 23 - host means this is a host controller 24 - peripheral means it is device controller 25 - otg means it can operate as either ("on the go") 26 - - nvidia,has-legacy-mode : boolean indicates whether this controller can 27 - operate in legacy mode (as APX 2500 / 2600). In legacy mode some 28 - registers are accessed through the APB_MISC base address instead of 29 - the USB controller. Since this is a legacy issue it probably does not 30 - warrant a compatible string of its own. 31 - - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2 32 - USB ports, which need reset twice due to hardware issues. 14 + - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 15 + USB ports, which need reset twice due to hardware issues.
+37 -2
Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
··· 4 4 5 5 Required properties : 6 6 - compatible : Should be "nvidia,tegra20-usb-phy". 7 - - reg : Address and length of the register set for the USB PHY interface. 8 - - phy_type : Should be one of "ulpi" or "utmi". 7 + - reg : Defines the following set of registers, in the order listed: 8 + - The PHY's own register set. 9 + Always present. 10 + - The register set of the PHY containing the UTMI pad control registers. 11 + Present if-and-only-if phy_type == utmi. 12 + - phy_type : Should be one of "utmi", "ulpi" or "hsic". 13 + - clocks : Defines the clocks listed in the clock-names property. 14 + - clock-names : The following clock names must be present: 15 + - reg: The clock needed to access the PHY's own registers. This is the 16 + associated EHCI controller's clock. Always present. 17 + - pll_u: PLL_U. Always present. 18 + - timer: The timeout clock (clk_m). Present if phy_type == utmi. 19 + - utmi-pads: The clock needed to access the UTMI pad control registers. 20 + Present if phy_type == utmi. 21 + - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). 22 + Present if phy_type == ulpi, and ULPI link mode is in use. 9 23 10 24 Required properties for phy_type == ulpi: 11 25 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 26 + 27 + Required PHY timing params for utmi phy: 28 + - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before 29 + start of sync launches RxActive 30 + - nvidia,elastic-limit : Variable FIFO Depth of elastic input store 31 + - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait 32 + before declare IDLE. 33 + - nvidia,term-range-adj : Range adjusment on terminations 34 + - nvidia,xcvr-setup : HS driver output control 35 + - nvidia,xcvr-lsfslew : LS falling slew rate control. 36 + - nvidia,xcvr-lsrslew : LS rising slew rate control. 12 37 13 38 Optional properties: 14 39 - nvidia,has-legacy-mode : boolean indicates whether this controller can 15 40 operate in legacy mode (as APX 2500 / 2600). In legacy mode some 16 41 registers are accessed through the APB_MISC base address instead of 17 42 the USB controller. 43 + - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power 44 + optimizations for the devices that are always connected. e.g. modem. 45 + - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be 46 + "host", "peripheral", or "otg". Defaults to "host" if not defined. 47 + host means this is a host controller 48 + peripheral means it is device controller 49 + otg means it can operate as either ("on the go") 50 + 51 + Required properties for dr_mode == otg: 52 + - vbus-supply: regulator for VBUS
+63 -8
arch/arm/boot/dts/tegra114-dalmore.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra114.dtsi" 3 + #include "tegra114.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Tegra114 Dalmore evaluation board"; ··· 727 727 battery-name = "battery"; 728 728 sbs,i2c-retry-count = <2>; 729 729 sbs,poll-retry-count = <100>; 730 + power-supplies = <&charger>; 731 + }; 732 + 733 + rt5640: rt5640 { 734 + compatible = "realtek,rt5640"; 735 + reg = <0x1c>; 736 + interrupt-parent = <&gpio>; 737 + interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; 738 + realtek,ldo1-en-gpios = 739 + <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 730 740 }; 731 741 }; 732 742 ··· 758 748 compatible = "ti,tps65090"; 759 749 reg = <0x48>; 760 750 interrupt-parent = <&gpio>; 761 - interrupts = <72 0x04>; /* gpio PJ0 */ 751 + interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; 762 752 763 753 vsys1-supply = <&vdd_ac_bat_reg>; 764 754 vsys2-supply = <&vdd_ac_bat_reg>; ··· 772 762 infet7-supply = <&tps65090_dcdc2_reg>; 773 763 vsys-l1-supply = <&vdd_ac_bat_reg>; 774 764 vsys-l2-supply = <&vdd_ac_bat_reg>; 765 + 766 + charger: charger { 767 + compatible = "ti,tps65090-charger"; 768 + ti,enable-low-current-chrg; 769 + }; 775 770 776 771 regulators { 777 772 tps65090_dcdc1_reg: dcdc1 { ··· 838 823 }; 839 824 }; 840 825 826 + spi@7000da00 { 827 + status = "okay"; 828 + spi-max-frequency = <25000000>; 829 + spi-flash@0 { 830 + compatible = "winbond,w25q32dw"; 831 + reg = <0>; 832 + spi-max-frequency = <20000000>; 833 + }; 834 + }; 835 + 841 836 pmc { 842 837 nvidia,invert-interrupt; 843 838 }; 844 839 840 + ahub { 841 + i2s@70080400 { 842 + status = "okay"; 843 + }; 844 + }; 845 + 845 846 sdhci@78000400 { 846 - cd-gpios = <&gpio 170 1>; /* gpio PV2 */ 847 + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 847 848 bus-width = <4>; 848 849 status = "okay"; 849 850 }; ··· 904 873 regulator-min-microvolt = <1800000>; 905 874 regulator-max-microvolt = <1800000>; 906 875 enable-active-high; 907 - gpio = <&gpio 61 0>; /* GPIO PH5 */ 876 + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; 908 877 }; 909 878 910 879 lcd_bl_en_reg: regulator@2 { ··· 914 883 regulator-min-microvolt = <5000000>; 915 884 regulator-max-microvolt = <5000000>; 916 885 enable-active-high; 917 - gpio = <&gpio 58 0>; /* GPIO PH2 */ 886 + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 918 887 }; 919 888 920 889 usb1_vbus_reg: regulator@3 { ··· 924 893 regulator-min-microvolt = <5000000>; 925 894 regulator-max-microvolt = <5000000>; 926 895 enable-active-high; 927 - gpio = <&gpio 108 0>; /* GPIO PN4 */ 896 + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 928 897 gpio-open-drain; 929 898 vin-supply = <&tps65090_dcdc1_reg>; 930 899 }; ··· 936 905 regulator-min-microvolt = <5000000>; 937 906 regulator-max-microvolt = <5000000>; 938 907 enable-active-high; 939 - gpio = <&gpio 86 0>; /* GPIO PK6 */ 908 + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 940 909 gpio-open-drain; 941 910 vin-supply = <&tps65090_dcdc1_reg>; 942 911 }; ··· 948 917 regulator-min-microvolt = <5000000>; 949 918 regulator-max-microvolt = <5000000>; 950 919 enable-active-high; 951 - gpio = <&gpio 81 0>; /* GPIO PK1 */ 920 + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 952 921 vin-supply = <&tps65090_dcdc1_reg>; 953 922 }; 923 + }; 924 + 925 + sound { 926 + compatible = "nvidia,tegra-audio-rt5640-dalmore", 927 + "nvidia,tegra-audio-rt5640"; 928 + nvidia,model = "NVIDIA Tegra Dalmore"; 929 + 930 + nvidia,audio-routing = 931 + "Headphones", "HPOR", 932 + "Headphones", "HPOL", 933 + "Speakers", "SPORP", 934 + "Speakers", "SPORN", 935 + "Speakers", "SPOLP", 936 + "Speakers", "SPOLN"; 937 + 938 + nvidia,i2s-controller = <&tegra_i2s1>; 939 + nvidia,audio-codec = <&rt5640>; 940 + 941 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; 942 + 943 + clocks = <&tegra_car TEGRA114_CLK_PLL_A>, 944 + <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 945 + <&tegra_car TEGRA114_CLK_EXTERN1>; 946 + clock-names = "pll_a", "pll_a_out0", "mclk"; 954 947 }; 955 948 };
+1 -1
arch/arm/boot/dts/tegra114-pluto.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra114.dtsi" 3 + #include "tegra114.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Tegra114 Pluto evaluation board";
+179 -98
arch/arm/boot/dts/tegra114.dtsi
··· 1 - /include/ "skeleton.dtsi" 1 + #include <dt-bindings/clock/tegra114-car.h> 2 + #include <dt-bindings/gpio/tegra-gpio.h> 3 + #include <dt-bindings/interrupt-controller/arm-gic.h> 4 + 5 + #include "skeleton.dtsi" 2 6 3 7 / { 4 8 compatible = "nvidia,tegra114"; ··· 23 19 <0x50042000 0x1000>, 24 20 <0x50044000 0x2000>, 25 21 <0x50046000 0x2000>; 26 - interrupts = <1 9 0xf04>; 22 + interrupts = <GIC_PPI 9 23 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 27 24 }; 28 25 29 26 timer@60005000 { 30 27 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; 31 28 reg = <0x60005000 0x400>; 32 - interrupts = <0 0 0x04 33 - 0 1 0x04 34 - 0 41 0x04 35 - 0 42 0x04 36 - 0 121 0x04 37 - 0 122 0x04>; 38 - clocks = <&tegra_car 5>; 29 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 30 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 31 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 32 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 33 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 34 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 35 + clocks = <&tegra_car TEGRA114_CLK_TIMER>; 39 36 }; 40 37 41 38 tegra_car: clock { ··· 48 43 apbdma: dma { 49 44 compatible = "nvidia,tegra114-apbdma"; 50 45 reg = <0x6000a000 0x1400>; 51 - interrupts = <0 104 0x04 52 - 0 105 0x04 53 - 0 106 0x04 54 - 0 107 0x04 55 - 0 108 0x04 56 - 0 109 0x04 57 - 0 110 0x04 58 - 0 111 0x04 59 - 0 112 0x04 60 - 0 113 0x04 61 - 0 114 0x04 62 - 0 115 0x04 63 - 0 116 0x04 64 - 0 117 0x04 65 - 0 118 0x04 66 - 0 119 0x04 67 - 0 128 0x04 68 - 0 129 0x04 69 - 0 130 0x04 70 - 0 131 0x04 71 - 0 132 0x04 72 - 0 133 0x04 73 - 0 134 0x04 74 - 0 135 0x04 75 - 0 136 0x04 76 - 0 137 0x04 77 - 0 138 0x04 78 - 0 139 0x04 79 - 0 140 0x04 80 - 0 141 0x04 81 - 0 142 0x04 82 - 0 143 0x04>; 83 - clocks = <&tegra_car 34>; 46 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 47 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 48 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 49 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 50 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 51 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 52 + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 53 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 54 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 55 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 56 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 57 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 58 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 59 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 60 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 61 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 62 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 63 + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 64 + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 65 + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 66 + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 67 + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 68 + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 69 + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 70 + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 71 + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 72 + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 73 + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 74 + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 75 + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 76 + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 77 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 78 + clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 84 79 }; 85 80 86 81 ahb: ahb { ··· 91 86 gpio: gpio { 92 87 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 93 88 reg = <0x6000d000 0x1000>; 94 - interrupts = <0 32 0x04 95 - 0 33 0x04 96 - 0 34 0x04 97 - 0 35 0x04 98 - 0 55 0x04 99 - 0 87 0x04 100 - 0 89 0x04 101 - 0 125 0x04>; 89 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 90 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 91 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 92 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 93 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 94 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 95 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 102 97 #gpio-cells = <2>; 103 98 gpio-controller; 104 99 #interrupt-cells = <2>; ··· 123 118 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 124 119 reg = <0x70006000 0x40>; 125 120 reg-shift = <2>; 126 - interrupts = <0 36 0x04>; 121 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 127 122 nvidia,dma-request-selector = <&apbdma 8>; 128 123 status = "disabled"; 129 - clocks = <&tegra_car 6>; 124 + clocks = <&tegra_car TEGRA114_CLK_UARTA>; 130 125 }; 131 126 132 127 uartb: serial@70006040 { 133 128 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 134 129 reg = <0x70006040 0x40>; 135 130 reg-shift = <2>; 136 - interrupts = <0 37 0x04>; 131 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 137 132 nvidia,dma-request-selector = <&apbdma 9>; 138 133 status = "disabled"; 139 - clocks = <&tegra_car 192>; 134 + clocks = <&tegra_car TEGRA114_CLK_UARTB>; 140 135 }; 141 136 142 137 uartc: serial@70006200 { 143 138 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 144 139 reg = <0x70006200 0x100>; 145 140 reg-shift = <2>; 146 - interrupts = <0 46 0x04>; 141 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 147 142 nvidia,dma-request-selector = <&apbdma 10>; 148 143 status = "disabled"; 149 - clocks = <&tegra_car 55>; 144 + clocks = <&tegra_car TEGRA114_CLK_UARTC>; 150 145 }; 151 146 152 147 uartd: serial@70006300 { 153 148 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 154 149 reg = <0x70006300 0x100>; 155 150 reg-shift = <2>; 156 - interrupts = <0 90 0x04>; 151 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 157 152 nvidia,dma-request-selector = <&apbdma 19>; 158 153 status = "disabled"; 159 - clocks = <&tegra_car 65>; 154 + clocks = <&tegra_car TEGRA114_CLK_UARTD>; 160 155 }; 161 156 162 157 pwm: pwm { 163 158 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 164 159 reg = <0x7000a000 0x100>; 165 160 #pwm-cells = <2>; 166 - clocks = <&tegra_car 17>; 161 + clocks = <&tegra_car TEGRA114_CLK_PWM>; 167 162 status = "disabled"; 168 163 }; 169 164 170 165 i2c@7000c000 { 171 166 compatible = "nvidia,tegra114-i2c"; 172 167 reg = <0x7000c000 0x100>; 173 - interrupts = <0 38 0x04>; 168 + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 174 169 #address-cells = <1>; 175 170 #size-cells = <0>; 176 - clocks = <&tegra_car 12>; 171 + clocks = <&tegra_car TEGRA114_CLK_I2C1>; 177 172 clock-names = "div-clk"; 178 173 status = "disabled"; 179 174 }; ··· 181 176 i2c@7000c400 { 182 177 compatible = "nvidia,tegra114-i2c"; 183 178 reg = <0x7000c400 0x100>; 184 - interrupts = <0 84 0x04>; 179 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 185 180 #address-cells = <1>; 186 181 #size-cells = <0>; 187 - clocks = <&tegra_car 54>; 182 + clocks = <&tegra_car TEGRA114_CLK_I2C2>; 188 183 clock-names = "div-clk"; 189 184 status = "disabled"; 190 185 }; ··· 192 187 i2c@7000c500 { 193 188 compatible = "nvidia,tegra114-i2c"; 194 189 reg = <0x7000c500 0x100>; 195 - interrupts = <0 92 0x04>; 190 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 196 191 #address-cells = <1>; 197 192 #size-cells = <0>; 198 - clocks = <&tegra_car 67>; 193 + clocks = <&tegra_car TEGRA114_CLK_I2C3>; 199 194 clock-names = "div-clk"; 200 195 status = "disabled"; 201 196 }; ··· 203 198 i2c@7000c700 { 204 199 compatible = "nvidia,tegra114-i2c"; 205 200 reg = <0x7000c700 0x100>; 206 - interrupts = <0 120 0x04>; 201 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 207 202 #address-cells = <1>; 208 203 #size-cells = <0>; 209 - clocks = <&tegra_car 103>; 204 + clocks = <&tegra_car TEGRA114_CLK_I2C4>; 210 205 clock-names = "div-clk"; 211 206 status = "disabled"; 212 207 }; ··· 214 209 i2c@7000d000 { 215 210 compatible = "nvidia,tegra114-i2c"; 216 211 reg = <0x7000d000 0x100>; 217 - interrupts = <0 53 0x04>; 212 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 218 213 #address-cells = <1>; 219 214 #size-cells = <0>; 220 - clocks = <&tegra_car 47>; 215 + clocks = <&tegra_car TEGRA114_CLK_I2C5>; 221 216 clock-names = "div-clk"; 222 217 status = "disabled"; 223 218 }; ··· 225 220 spi@7000d400 { 226 221 compatible = "nvidia,tegra114-spi"; 227 222 reg = <0x7000d400 0x200>; 228 - interrupts = <0 59 0x04>; 223 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 229 224 nvidia,dma-request-selector = <&apbdma 15>; 230 225 #address-cells = <1>; 231 226 #size-cells = <0>; 232 - clocks = <&tegra_car 41>; 227 + clocks = <&tegra_car TEGRA114_CLK_SBC1>; 233 228 clock-names = "spi"; 234 229 status = "disabled"; 235 230 }; ··· 237 232 spi@7000d600 { 238 233 compatible = "nvidia,tegra114-spi"; 239 234 reg = <0x7000d600 0x200>; 240 - interrupts = <0 82 0x04>; 235 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 241 236 nvidia,dma-request-selector = <&apbdma 16>; 242 237 #address-cells = <1>; 243 238 #size-cells = <0>; 244 - clocks = <&tegra_car 44>; 239 + clocks = <&tegra_car TEGRA114_CLK_SBC2>; 245 240 clock-names = "spi"; 246 241 status = "disabled"; 247 242 }; ··· 249 244 spi@7000d800 { 250 245 compatible = "nvidia,tegra114-spi"; 251 246 reg = <0x7000d800 0x200>; 252 - interrupts = <0 83 0x04>; 247 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 253 248 nvidia,dma-request-selector = <&apbdma 17>; 254 249 #address-cells = <1>; 255 250 #size-cells = <0>; 256 - clocks = <&tegra_car 46>; 251 + clocks = <&tegra_car TEGRA114_CLK_SBC3>; 257 252 clock-names = "spi"; 258 253 status = "disabled"; 259 254 }; ··· 261 256 spi@7000da00 { 262 257 compatible = "nvidia,tegra114-spi"; 263 258 reg = <0x7000da00 0x200>; 264 - interrupts = <0 93 0x04>; 259 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 265 260 nvidia,dma-request-selector = <&apbdma 18>; 266 261 #address-cells = <1>; 267 262 #size-cells = <0>; 268 - clocks = <&tegra_car 68>; 263 + clocks = <&tegra_car TEGRA114_CLK_SBC4>; 269 264 clock-names = "spi"; 270 265 status = "disabled"; 271 266 }; ··· 273 268 spi@7000dc00 { 274 269 compatible = "nvidia,tegra114-spi"; 275 270 reg = <0x7000dc00 0x200>; 276 - interrupts = <0 94 0x04>; 271 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 277 272 nvidia,dma-request-selector = <&apbdma 27>; 278 273 #address-cells = <1>; 279 274 #size-cells = <0>; 280 - clocks = <&tegra_car 104>; 275 + clocks = <&tegra_car TEGRA114_CLK_SBC5>; 281 276 clock-names = "spi"; 282 277 status = "disabled"; 283 278 }; ··· 285 280 spi@7000de00 { 286 281 compatible = "nvidia,tegra114-spi"; 287 282 reg = <0x7000de00 0x200>; 288 - interrupts = <0 79 0x04>; 283 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 289 284 nvidia,dma-request-selector = <&apbdma 28>; 290 285 #address-cells = <1>; 291 286 #size-cells = <0>; 292 - clocks = <&tegra_car 105>; 287 + clocks = <&tegra_car TEGRA114_CLK_SBC6>; 293 288 clock-names = "spi"; 294 289 status = "disabled"; 295 290 }; ··· 297 292 rtc { 298 293 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 299 294 reg = <0x7000e000 0x100>; 300 - interrupts = <0 2 0x04>; 301 - clocks = <&tegra_car 4>; 295 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 296 + clocks = <&tegra_car TEGRA114_CLK_RTC>; 302 297 }; 303 298 304 299 kbc { 305 300 compatible = "nvidia,tegra114-kbc"; 306 301 reg = <0x7000e200 0x100>; 307 - interrupts = <0 85 0x04>; 308 - clocks = <&tegra_car 36>; 302 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 303 + clocks = <&tegra_car TEGRA114_CLK_KBC>; 309 304 status = "disabled"; 310 305 }; 311 306 312 307 pmc { 313 308 compatible = "nvidia,tegra114-pmc"; 314 309 reg = <0x7000e400 0x400>; 315 - clocks = <&tegra_car 261>, <&clk32k_in>; 310 + clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 316 311 clock-names = "pclk", "clk32k_in"; 317 312 }; 318 313 ··· 327 322 nvidia,ahb = <&ahb>; 328 323 }; 329 324 325 + ahub { 326 + compatible = "nvidia,tegra114-ahub"; 327 + reg = <0x70080000 0x200>, 328 + <0x70080200 0x100>, 329 + <0x70081000 0x200>; 330 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 331 + nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, 332 + <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, 333 + <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, 334 + <&apbdma 29>; 335 + clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 336 + <&tegra_car TEGRA114_CLK_APBIF>, 337 + <&tegra_car TEGRA114_CLK_I2S0>, 338 + <&tegra_car TEGRA114_CLK_I2S1>, 339 + <&tegra_car TEGRA114_CLK_I2S2>, 340 + <&tegra_car TEGRA114_CLK_I2S3>, 341 + <&tegra_car TEGRA114_CLK_I2S4>, 342 + <&tegra_car TEGRA114_CLK_DAM0>, 343 + <&tegra_car TEGRA114_CLK_DAM1>, 344 + <&tegra_car TEGRA114_CLK_DAM2>, 345 + <&tegra_car TEGRA114_CLK_SPDIF_IN>, 346 + <&tegra_car TEGRA114_CLK_AMX>, 347 + <&tegra_car TEGRA114_CLK_ADX>; 348 + clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 349 + "i2s3", "i2s4", "dam0", "dam1", "dam2", 350 + "spdif_in", "amx", "adx"; 351 + ranges; 352 + #address-cells = <1>; 353 + #size-cells = <1>; 354 + 355 + tegra_i2s0: i2s@70080300 { 356 + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 357 + reg = <0x70080300 0x100>; 358 + nvidia,ahub-cif-ids = <4 4>; 359 + clocks = <&tegra_car TEGRA114_CLK_I2S0>; 360 + status = "disabled"; 361 + }; 362 + 363 + tegra_i2s1: i2s@70080400 { 364 + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 365 + reg = <0x70080400 0x100>; 366 + nvidia,ahub-cif-ids = <5 5>; 367 + clocks = <&tegra_car TEGRA114_CLK_I2S1>; 368 + status = "disabled"; 369 + }; 370 + 371 + tegra_i2s2: i2s@70080500 { 372 + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 373 + reg = <0x70080500 0x100>; 374 + nvidia,ahub-cif-ids = <6 6>; 375 + clocks = <&tegra_car TEGRA114_CLK_I2S2>; 376 + status = "disabled"; 377 + }; 378 + 379 + tegra_i2s3: i2s@70080600 { 380 + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 381 + reg = <0x70080600 0x100>; 382 + nvidia,ahub-cif-ids = <7 7>; 383 + clocks = <&tegra_car TEGRA114_CLK_I2S3>; 384 + status = "disabled"; 385 + }; 386 + 387 + tegra_i2s4: i2s@70080700 { 388 + compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 389 + reg = <0x70080700 0x100>; 390 + nvidia,ahub-cif-ids = <8 8>; 391 + clocks = <&tegra_car TEGRA114_CLK_I2S4>; 392 + status = "disabled"; 393 + }; 394 + }; 395 + 330 396 sdhci@78000000 { 331 397 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 332 398 reg = <0x78000000 0x200>; 333 - interrupts = <0 14 0x04>; 334 - clocks = <&tegra_car 14>; 399 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 400 + clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 335 401 status = "disable"; 336 402 }; 337 403 338 404 sdhci@78000200 { 339 405 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 340 406 reg = <0x78000200 0x200>; 341 - interrupts = <0 15 0x04>; 342 - clocks = <&tegra_car 9>; 407 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 408 + clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 343 409 status = "disable"; 344 410 }; 345 411 346 412 sdhci@78000400 { 347 413 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 348 414 reg = <0x78000400 0x200>; 349 - interrupts = <0 19 0x04>; 350 - clocks = <&tegra_car 69>; 415 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 416 + clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 351 417 status = "disable"; 352 418 }; 353 419 354 420 sdhci@78000600 { 355 421 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 356 422 reg = <0x78000600 0x200>; 357 - interrupts = <0 31 0x04>; 358 - clocks = <&tegra_car 15>; 423 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 424 + clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 359 425 status = "disable"; 360 426 }; 361 427 ··· 461 385 462 386 timer { 463 387 compatible = "arm,armv7-timer"; 464 - interrupts = <1 13 0xf08>, 465 - <1 14 0xf08>, 466 - <1 11 0xf08>, 467 - <1 10 0xf08>; 388 + interrupts = 389 + <GIC_PPI 13 390 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 391 + <GIC_PPI 14 392 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 393 + <GIC_PPI 11 394 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 395 + <GIC_PPI 10 396 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 468 397 }; 469 398 };
+20 -9
arch/arm/boot/dts/tegra20-colibri-512.dtsi
··· 1 - /include/ "tegra20.dtsi" 1 + #include "tegra20.dtsi" 2 2 3 3 / { 4 4 model = "Toradex Colibri T20 512MB"; ··· 14 14 pll-supply = <&hdmi_pll_reg>; 15 15 16 16 nvidia,ddc-i2c-bus = <&i2c_ddc>; 17 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 17 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 18 + GPIO_ACTIVE_HIGH>; 18 19 }; 19 20 }; 20 21 ··· 218 217 pmic: tps6586x@34 { 219 218 compatible = "ti,tps6586x"; 220 219 reg = <0x34>; 221 - interrupts = <0 86 0x4>; 220 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 222 221 223 222 ti,system-power-controller; 224 223 ··· 444 443 445 444 ac97: ac97 { 446 445 status = "okay"; 447 - nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 448 - nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */ 446 + nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 447 + GPIO_ACTIVE_HIGH>; 448 + nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) 449 + GPIO_ACTIVE_HIGH>; 449 450 }; 450 451 451 452 usb@c5004000 { 452 453 status = "okay"; 453 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 454 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 455 + GPIO_ACTIVE_LOW>; 456 + }; 457 + 458 + usb-phy@c5004000 { 459 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 460 + GPIO_ACTIVE_LOW>; 454 461 }; 455 462 456 463 sdhci@c8000600 { 457 - cd-gpios = <&gpio 23 1>; /* gpio PC7 */ 464 + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; 458 465 }; 459 466 460 467 clocks { ··· 492 483 493 484 nvidia,ac97-controller = <&ac97>; 494 485 495 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 486 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 487 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 488 + <&tegra_car TEGRA20_CLK_CDEV1>; 496 489 clock-names = "pll_a", "pll_a_out0", "mclk"; 497 490 }; 498 491 ··· 521 510 enable-active-high; 522 511 regulator-boot-on; 523 512 regulator-always-on; 524 - gpio = <&gpio 217 0>; 513 + gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; 525 514 }; 526 515 }; 527 516 };
+41 -24
arch/arm/boot/dts/tegra20-harmony.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20.dtsi" 3 + #include "tegra20.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Tegra20 Harmony evaluation board"; ··· 18 18 pll-supply = <&hdmi_pll_reg>; 19 19 20 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 21 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 22 + GPIO_ACTIVE_HIGH>; 22 23 }; 23 24 }; 24 25 ··· 263 262 compatible = "wlf,wm8903"; 264 263 reg = <0x1a>; 265 264 interrupt-parent = <&gpio>; 266 - interrupts = <187 0x04>; 265 + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 267 266 268 267 gpio-controller; 269 268 #gpio-cells = <2>; ··· 291 290 pmic: tps6586x@34 { 292 291 compatible = "ti,tps6586x"; 293 292 reg = <0x34>; 294 - interrupts = <0 86 0x4>; 293 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 295 294 296 295 ti,system-power-controller; 297 296 ··· 429 428 status = "okay"; 430 429 }; 431 430 431 + usb-phy@c5000000 { 432 + status = "okay"; 433 + }; 434 + 432 435 usb@c5004000 { 433 436 status = "okay"; 434 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 437 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 438 + GPIO_ACTIVE_LOW>; 439 + }; 440 + 441 + usb-phy@c5004000 { 442 + status = "okay"; 443 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 444 + GPIO_ACTIVE_LOW>; 435 445 }; 436 446 437 447 usb@c5008000 { 438 448 status = "okay"; 439 449 }; 440 450 441 - usb-phy@c5004400 { 442 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 451 + usb-phy@c5008000 { 452 + status = "okay"; 443 453 }; 444 454 445 455 sdhci@c8000200 { 446 456 status = "okay"; 447 - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 448 - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 449 - power-gpios = <&gpio 155 0>; /* gpio PT3 */ 457 + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 458 + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 459 + power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 450 460 bus-width = <4>; 451 461 }; 452 462 453 463 sdhci@c8000600 { 454 464 status = "okay"; 455 - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ 456 - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 457 - power-gpios = <&gpio 70 0>; /* gpio PI6 */ 465 + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; 466 + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 467 + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 458 468 bus-width = <8>; 459 469 }; 460 470 ··· 487 475 488 476 power { 489 477 label = "Power"; 490 - gpios = <&gpio 170 1>; /* gpio PV2, active low */ 478 + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 491 479 linux,code = <116>; /* KEY_POWER */ 492 480 gpio-key,wakeup; 493 481 }; ··· 630 618 regulator-name = "vdd_1v5"; 631 619 regulator-min-microvolt = <1500000>; 632 620 regulator-max-microvolt = <1500000>; 633 - gpio = <&pmic 0 0>; 621 + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 634 622 }; 635 623 636 624 regulator@2 { ··· 639 627 regulator-name = "vdd_1v2"; 640 628 regulator-min-microvolt = <1200000>; 641 629 regulator-max-microvolt = <1200000>; 642 - gpio = <&pmic 1 0>; 630 + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 643 631 enable-active-high; 644 632 }; 645 633 ··· 649 637 regulator-name = "vdd_1v05"; 650 638 regulator-min-microvolt = <1050000>; 651 639 regulator-max-microvolt = <1050000>; 652 - gpio = <&pmic 2 0>; 640 + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 653 641 enable-active-high; 654 642 /* Hack until board-harmony-pcie.c is removed */ 655 643 status = "disabled"; ··· 661 649 regulator-name = "vdd_pnl"; 662 650 regulator-min-microvolt = <2800000>; 663 651 regulator-max-microvolt = <2800000>; 664 - gpio = <&gpio 22 0>; /* gpio PC6 */ 652 + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 665 653 enable-active-high; 666 654 }; 667 655 ··· 671 659 regulator-name = "vdd_bl"; 672 660 regulator-min-microvolt = <2800000>; 673 661 regulator-max-microvolt = <2800000>; 674 - gpio = <&gpio 176 0>; /* gpio PW0 */ 662 + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 675 663 enable-active-high; 676 664 }; 677 665 }; ··· 694 682 nvidia,i2s-controller = <&tegra_i2s1>; 695 683 nvidia,audio-codec = <&wm8903>; 696 684 697 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 698 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 699 - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 700 - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 685 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 686 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 687 + GPIO_ACTIVE_HIGH>; 688 + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) 689 + GPIO_ACTIVE_HIGH>; 690 + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) 691 + GPIO_ACTIVE_HIGH>; 701 692 702 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 693 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 694 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 695 + <&tegra_car TEGRA20_CLK_CDEV1>; 703 696 clock-names = "pll_a", "pll_a_out0", "mclk"; 704 697 }; 705 698 };
+10 -3
arch/arm/boot/dts/tegra20-iris-512.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20-colibri-512.dtsi" 3 + #include "tegra20-colibri-512.dtsi" 4 4 5 5 / { 6 6 model = "Toradex Colibri T20 512MB on Iris"; ··· 38 38 39 39 usb@c5000000 { 40 40 status = "okay"; 41 - dr_mode = "otg"; 41 + }; 42 + 43 + usb-phy@c5000000 { 44 + status = "okay"; 42 45 }; 43 46 44 47 usb@c5008000 { 48 + status = "okay"; 49 + }; 50 + 51 + usb-phy@c5008000 { 45 52 status = "okay"; 46 53 }; 47 54 ··· 80 73 regulator-max-microvolt = <5000000>; 81 74 regulator-boot-on; 82 75 regulator-always-on; 83 - gpio = <&gpio 178 0>; 76 + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 84 77 }; 85 78 86 79 vcc_sd_reg: regulator@1 {
+7 -5
arch/arm/boot/dts/tegra20-medcom-wide.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20-tamonten.dtsi" 3 + #include "tegra20-tamonten.dtsi" 4 4 5 5 / { 6 6 model = "Avionic Design Medcom-Wide board"; ··· 15 15 compatible = "wlf,wm8903"; 16 16 reg = <0x1a>; 17 17 interrupt-parent = <&gpio>; 18 - interrupts = <187 0x04>; 18 + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 19 19 20 20 gpio-controller; 21 21 #gpio-cells = <2>; ··· 56 56 nvidia,i2s-controller = <&tegra_i2s1>; 57 57 nvidia,audio-codec = <&wm8903>; 58 58 59 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 60 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 59 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 60 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 61 61 62 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 62 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 63 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 64 + <&tegra_car TEGRA20_CLK_CDEV1>; 63 65 clock-names = "pll_a", "pll_a_out0", "mclk"; 64 66 }; 65 67 };
+32 -16
arch/arm/boot/dts/tegra20-paz00.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20.dtsi" 3 + #include "tegra20.dtsi" 4 4 5 5 / { 6 6 model = "Toshiba AC100 / Dynabook AZ"; ··· 18 18 pll-supply = <&hdmi_pll_reg>; 19 19 20 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 21 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 22 + GPIO_ACTIVE_HIGH>; 22 23 }; 23 24 }; 24 25 ··· 271 270 nvec { 272 271 compatible = "nvidia,nvec"; 273 272 reg = <0x7000c500 0x100>; 274 - interrupts = <0 92 0x04>; 273 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 275 274 #address-cells = <1>; 276 275 #size-cells = <0>; 277 276 clock-frequency = <80000>; 278 - request-gpios = <&gpio 170 0>; /* gpio PV2 */ 277 + request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 279 278 slave-addr = <138>; 280 - clocks = <&tegra_car 67>, <&tegra_car 124>; 279 + clocks = <&tegra_car TEGRA20_CLK_I2C3>, 280 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 281 281 clock-names = "div-clk", "fast-clk"; 282 282 }; 283 283 ··· 289 287 pmic: tps6586x@34 { 290 288 compatible = "ti,tps6586x"; 291 289 reg = <0x34>; 292 - interrupts = <0 86 0x4>; 290 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 293 291 294 292 #gpio-cells = <2>; 295 293 gpio-controller; ··· 429 427 status = "okay"; 430 428 }; 431 429 430 + usb-phy@c5000000 { 431 + status = "okay"; 432 + }; 433 + 432 434 usb@c5004000 { 433 435 status = "okay"; 434 - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 436 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 437 + GPIO_ACTIVE_LOW>; 438 + }; 439 + 440 + usb-phy@c5004000 { 441 + status = "okay"; 442 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 443 + GPIO_ACTIVE_LOW>; 435 444 }; 436 445 437 446 usb@c5008000 { 438 447 status = "okay"; 439 448 }; 440 449 441 - usb-phy@c5004400 { 442 - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 450 + usb-phy@c5008000 { 451 + status = "okay"; 443 452 }; 444 453 445 454 sdhci@c8000000 { 446 455 status = "okay"; 447 - cd-gpios = <&gpio 173 1>; /* gpio PV5 */ 448 - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 449 - power-gpios = <&gpio 169 0>; /* gpio PV1 */ 456 + cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; 457 + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 458 + power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 450 459 bus-width = <4>; 451 460 }; 452 461 ··· 485 472 486 473 power { 487 474 label = "Power"; 488 - gpios = <&gpio 79 1>; /* gpio PJ7, active low */ 475 + gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; 489 476 linux,code = <116>; /* KEY_POWER */ 490 477 gpio-key,wakeup; 491 478 }; ··· 496 483 497 484 wifi { 498 485 label = "wifi-led"; 499 - gpios = <&gpio 24 0>; /* gpio PD0 */ 486 + gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 500 487 linux,default-trigger = "rfkill0"; 501 488 }; 502 489 }; ··· 533 520 534 521 nvidia,audio-codec = <&alc5632>; 535 522 nvidia,i2s-controller = <&tegra_i2s1>; 536 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 523 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 524 + GPIO_ACTIVE_HIGH>; 537 525 538 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 526 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 527 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 528 + <&tegra_car TEGRA20_CLK_CDEV1>; 539 529 clock-names = "pll_a", "pll_a_out0", "mclk"; 540 530 }; 541 531 };
+7 -5
arch/arm/boot/dts/tegra20-plutux.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20-tamonten.dtsi" 3 + #include "tegra20-tamonten.dtsi" 4 4 5 5 / { 6 6 model = "Avionic Design Plutux board"; ··· 17 17 compatible = "wlf,wm8903"; 18 18 reg = <0x1a>; 19 19 interrupt-parent = <&gpio>; 20 - interrupts = <187 0x04>; 20 + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 21 21 22 22 gpio-controller; 23 23 #gpio-cells = <2>; ··· 50 50 nvidia,i2s-controller = <&tegra_i2s1>; 51 51 nvidia,audio-codec = <&wm8903>; 52 52 53 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 54 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 53 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 54 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 55 55 56 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 56 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 57 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 58 + <&tegra_car TEGRA20_CLK_CDEV1>; 57 59 clock-names = "pll_a", "pll_a_out0", "mclk"; 58 60 }; 59 61 };
+47 -22
arch/arm/boot/dts/tegra20-seaboard.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20.dtsi" 3 + #include "tegra20.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Seaboard"; ··· 18 18 pll-supply = <&hdmi_pll_reg>; 19 19 20 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 21 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 22 + GPIO_ACTIVE_HIGH>; 22 23 }; 23 24 }; 24 25 ··· 314 313 compatible = "wlf,wm8903"; 315 314 reg = <0x1a>; 316 315 interrupt-parent = <&gpio>; 317 - interrupts = <187 0x04>; 316 + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 318 317 319 318 gpio-controller; 320 319 #gpio-cells = <2>; ··· 329 328 compatible = "isil,isl29018"; 330 329 reg = <0x44>; 331 330 interrupt-parent = <&gpio>; 332 - interrupts = <202 0x04>; /* GPIO PZ2 */ 331 + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 333 332 }; 334 333 335 334 gyrometer@68 { 336 335 compatible = "invn,mpu3050"; 337 336 reg = <0x68>; 338 337 interrupt-parent = <&gpio>; 339 - interrupts = <204 0x04>; /* gpio PZ4 */ 338 + interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; 340 339 }; 341 340 }; 342 341 ··· 389 388 pmic: tps6586x@34 { 390 389 compatible = "ti,tps6586x"; 391 390 reg = <0x34>; 392 - interrupts = <0 86 0x4>; 391 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 393 392 394 393 ti,system-power-controller; 395 394 ··· 512 511 compatible = "ak,ak8975"; 513 512 reg = <0xc>; 514 513 interrupt-parent = <&gpio>; 515 - interrupts = <109 0x04>; /* gpio PN5 */ 514 + interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; 516 515 }; 517 516 }; 518 517 ··· 566 565 567 566 usb@c5000000 { 568 567 status = "okay"; 569 - nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ 568 + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 569 + dr_mode = "otg"; 570 + }; 571 + 572 + usb-phy@c5000000 { 573 + status = "okay"; 574 + vbus-supply = <&vbus_reg>; 570 575 dr_mode = "otg"; 571 576 }; 572 577 573 578 usb@c5004000 { 574 579 status = "okay"; 575 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 580 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 581 + GPIO_ACTIVE_LOW>; 582 + }; 583 + 584 + usb-phy@c5004000 { 585 + status = "okay"; 586 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 587 + GPIO_ACTIVE_LOW>; 576 588 }; 577 589 578 590 usb@c5008000 { 579 591 status = "okay"; 580 592 }; 581 593 582 - usb-phy@c5004400 { 583 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 594 + usb-phy@c5008000 { 595 + status = "okay"; 584 596 }; 585 597 586 598 sdhci@c8000000 { 587 599 status = "okay"; 588 - power-gpios = <&gpio 86 0>; /* gpio PK6 */ 600 + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 589 601 bus-width = <4>; 590 602 keep-power-in-suspend; 591 603 }; 592 604 593 605 sdhci@c8000400 { 594 606 status = "okay"; 595 - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 596 - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 597 - power-gpios = <&gpio 70 0>; /* gpio PI6 */ 607 + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 608 + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 609 + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 598 610 bus-width = <4>; 599 611 }; 600 612 ··· 635 621 636 622 power { 637 623 label = "Power"; 638 - gpios = <&gpio 170 1>; /* gpio PV2, active low */ 624 + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 639 625 linux,code = <116>; /* KEY_POWER */ 640 626 gpio-key,wakeup; 641 627 }; 642 628 643 629 lid { 644 630 label = "Lid"; 645 - gpios = <&gpio 23 0>; /* gpio PC7 */ 631 + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; 646 632 linux,input-type = <5>; /* EV_SW */ 647 633 linux,code = <0>; /* SW_LID */ 648 634 debounce-interval = <1>; ··· 809 795 regulator-name = "vdd_1v5"; 810 796 regulator-min-microvolt = <1500000>; 811 797 regulator-max-microvolt = <1500000>; 812 - gpio = <&pmic 0 0>; 798 + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 813 799 }; 814 800 815 801 regulator@2 { ··· 818 804 regulator-name = "vdd_1v2"; 819 805 regulator-min-microvolt = <1200000>; 820 806 regulator-max-microvolt = <1200000>; 821 - gpio = <&pmic 1 0>; 807 + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 822 808 enable-active-high; 809 + }; 810 + 811 + vbus_reg: regulator@3 { 812 + compatible = "regulator-fixed"; 813 + reg = <3>; 814 + regulator-name = "vdd_vbus_wup1"; 815 + regulator-min-microvolt = <5000000>; 816 + regulator-max-microvolt = <5000000>; 817 + gpio = <&gpio 24 0>; /* PD0 */ 823 818 }; 824 819 }; 825 820 ··· 850 827 nvidia,i2s-controller = <&tegra_i2s1>; 851 828 nvidia,audio-codec = <&wm8903>; 852 829 853 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 854 - nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ 830 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 831 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; 855 832 856 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 833 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 834 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 835 + <&tegra_car TEGRA20_CLK_CDEV1>; 857 836 clock-names = "pll_a", "pll_a_out0", "mclk"; 858 837 }; 859 838 };
+10 -5
arch/arm/boot/dts/tegra20-tamonten.dtsi
··· 1 - /include/ "tegra20.dtsi" 1 + #include "tegra20.dtsi" 2 2 3 3 / { 4 4 model = "Avionic Design Tamonten SOM"; ··· 14 14 pll-supply = <&hdmi_pll_reg>; 15 15 16 16 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 17 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 17 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 18 + GPIO_ACTIVE_HIGH>; 18 19 }; 19 20 }; 20 21 ··· 322 321 pmic: tps6586x@34 { 323 322 compatible = "ti,tps6586x"; 324 323 reg = <0x34>; 325 - interrupts = <0 86 0x4>; 324 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 326 325 327 326 ti,system-power-controller; 328 327 ··· 471 470 status = "okay"; 472 471 }; 473 472 473 + usb-phy@c5008000 { 474 + status = "okay"; 475 + }; 476 + 474 477 sdhci@c8000600 { 475 - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ 476 - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 478 + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; 479 + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 477 480 bus-width = <4>; 478 481 status = "okay"; 479 482 };
+8 -5
arch/arm/boot/dts/tegra20-tec.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20-tamonten.dtsi" 3 + #include "tegra20-tamonten.dtsi" 4 4 5 5 / { 6 6 model = "Avionic Design Tamonten Evaluation Carrier"; ··· 17 17 compatible = "wlf,wm8903"; 18 18 reg = <0x1a>; 19 19 interrupt-parent = <&gpio>; 20 - interrupts = <187 0x04>; 20 + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 21 21 22 22 gpio-controller; 23 23 #gpio-cells = <2>; ··· 50 50 nvidia,i2s-controller = <&tegra_i2s1>; 51 51 nvidia,audio-codec = <&wm8903>; 52 52 53 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 54 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 53 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 54 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 55 + GPIO_ACTIVE_HIGH>; 55 56 56 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 57 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 58 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 59 + <&tegra_car TEGRA20_CLK_CDEV1>; 57 60 clock-names = "pll_a", "pll_a_out0", "mclk"; 58 61 }; 59 62 };
+35 -11
arch/arm/boot/dts/tegra20-trimslice.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20.dtsi" 3 + #include "tegra20.dtsi" 4 4 5 5 / { 6 6 model = "Compulab TrimSlice board"; ··· 18 18 pll-supply = <&hdmi_pll_reg>; 19 19 20 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 21 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 22 + GPIO_ACTIVE_HIGH>; 22 23 }; 23 24 }; 24 25 ··· 312 311 313 312 usb@c5000000 { 314 313 status = "okay"; 315 - nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ 314 + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 315 + }; 316 + 317 + usb-phy@c5000000 { 318 + status = "okay"; 319 + vbus-supply = <&vbus_reg>; 316 320 }; 317 321 318 322 usb@c5004000 { 319 323 status = "okay"; 320 - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 324 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 325 + GPIO_ACTIVE_LOW>; 326 + }; 327 + 328 + usb-phy@c5004000 { 329 + status = "okay"; 330 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 331 + GPIO_ACTIVE_LOW>; 321 332 }; 322 333 323 334 usb@c5008000 { 324 335 status = "okay"; 325 336 }; 326 337 327 - usb-phy@c5004400 { 328 - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 338 + usb-phy@c5008000 { 339 + status = "okay"; 329 340 }; 330 341 331 342 sdhci@c8000000 { ··· 347 334 348 335 sdhci@c8000600 { 349 336 status = "okay"; 350 - cd-gpios = <&gpio 121 1>; /* gpio PP1 */ 351 - wp-gpios = <&gpio 122 0>; /* gpio PP2 */ 337 + cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; 338 + wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 352 339 bus-width = <4>; 353 340 }; 354 341 ··· 370 357 371 358 power { 372 359 label = "Power"; 373 - gpios = <&gpio 190 1>; /* gpio PX6, active low */ 360 + gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 374 361 linux,code = <116>; /* KEY_POWER */ 375 362 gpio-key,wakeup; 376 363 }; ··· 378 365 379 366 poweroff { 380 367 compatible = "gpio-poweroff"; 381 - gpios = <&gpio 191 1>; /* gpio PX7, active low */ 368 + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 382 369 }; 383 370 384 371 regulators { ··· 403 390 regulator-max-microvolt = <1800000>; 404 391 regulator-always-on; 405 392 }; 393 + 394 + vbus_reg: regulator@2 { 395 + compatible = "regulator-fixed"; 396 + reg = <2>; 397 + regulator-name = "usb1_vbus"; 398 + regulator-min-microvolt = <5000000>; 399 + regulator-max-microvolt = <5000000>; 400 + gpio = <&gpio 170 0>; /* PV2 */ 401 + }; 406 402 }; 407 403 408 404 sound { ··· 419 397 nvidia,i2s-controller = <&tegra_i2s1>; 420 398 nvidia,audio-codec = <&codec>; 421 399 422 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 400 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 401 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 402 + <&tegra_car TEGRA20_CLK_CDEV1>; 423 403 clock-names = "pll_a", "pll_a_out0", "mclk"; 424 404 }; 425 405 };
+38 -22
arch/arm/boot/dts/tegra20-ventana.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20.dtsi" 3 + #include "tegra20.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Tegra20 Ventana evaluation board"; ··· 18 18 pll-supply = <&hdmi_pll_reg>; 19 19 20 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 21 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 22 + GPIO_ACTIVE_HIGH>; 22 23 }; 23 24 }; 24 25 ··· 311 310 compatible = "wlf,wm8903"; 312 311 reg = <0x1a>; 313 312 interrupt-parent = <&gpio>; 314 - interrupts = <187 0x04>; 313 + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 315 314 316 315 gpio-controller; 317 316 #gpio-cells = <2>; ··· 326 325 compatible = "isil,isl29018"; 327 326 reg = <0x44>; 328 327 interrupt-parent = <&gpio>; 329 - interrupts = <202 0x04>; /*gpio PZ2 */ 328 + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 330 329 }; 331 330 }; 332 331 ··· 372 371 pmic: tps6586x@34 { 373 372 compatible = "ti,tps6586x"; 374 373 reg = <0x34>; 375 - interrupts = <0 86 0x4>; 374 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 376 375 377 376 ti,system-power-controller; 378 377 ··· 506 505 status = "okay"; 507 506 }; 508 507 508 + usb-phy@c5000000 { 509 + status = "okay"; 510 + }; 511 + 509 512 usb@c5004000 { 510 513 status = "okay"; 511 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 514 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 515 + GPIO_ACTIVE_LOW>; 516 + }; 517 + 518 + usb-phy@c5004000 { 519 + status = "okay"; 520 + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 521 + GPIO_ACTIVE_LOW>; 512 522 }; 513 523 514 524 usb@c5008000 { 515 525 status = "okay"; 516 526 }; 517 527 518 - usb-phy@c5004400 { 519 - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 528 + usb-phy@c5008000 { 529 + status = "okay"; 520 530 }; 521 531 522 532 sdhci@c8000000 { 523 533 status = "okay"; 524 - power-gpios = <&gpio 86 0>; /* gpio PK6 */ 534 + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 525 535 bus-width = <4>; 526 536 keep-power-in-suspend; 527 537 }; 528 538 529 539 sdhci@c8000400 { 530 540 status = "okay"; 531 - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 532 - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 533 - power-gpios = <&gpio 70 0>; /* gpio PI6 */ 541 + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 542 + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 543 + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 534 544 bus-width = <4>; 535 545 }; 536 546 ··· 569 557 570 558 power { 571 559 label = "Power"; 572 - gpios = <&gpio 170 1>; /* gpio PV2, active low */ 560 + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 573 561 linux,code = <116>; /* KEY_POWER */ 574 562 gpio-key,wakeup; 575 563 }; ··· 595 583 regulator-name = "vdd_1v5"; 596 584 regulator-min-microvolt = <1500000>; 597 585 regulator-max-microvolt = <1500000>; 598 - gpio = <&pmic 0 0>; 586 + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 599 587 }; 600 588 601 589 regulator@2 { ··· 604 592 regulator-name = "vdd_1v2"; 605 593 regulator-min-microvolt = <1200000>; 606 594 regulator-max-microvolt = <1200000>; 607 - gpio = <&pmic 1 0>; 595 + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 608 596 enable-active-high; 609 597 }; 610 598 ··· 614 602 regulator-name = "vdd_pnl"; 615 603 regulator-min-microvolt = <2800000>; 616 604 regulator-max-microvolt = <2800000>; 617 - gpio = <&gpio 22 0>; /* gpio PC6 */ 605 + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 618 606 enable-active-high; 619 607 }; 620 608 ··· 624 612 regulator-name = "vdd_bl"; 625 613 regulator-min-microvolt = <2800000>; 626 614 regulator-max-microvolt = <2800000>; 627 - gpio = <&gpio 176 0>; /* gpio PW0 */ 615 + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 628 616 enable-active-high; 629 617 }; 630 618 }; ··· 647 635 nvidia,i2s-controller = <&tegra_i2s1>; 648 636 nvidia,audio-codec = <&wm8903>; 649 637 650 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 651 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 652 - nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ 653 - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 638 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 639 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 640 + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) 641 + GPIO_ACTIVE_HIGH>; 642 + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) 643 + GPIO_ACTIVE_HIGH>; 654 644 655 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 645 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 646 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 647 + <&tegra_car TEGRA20_CLK_CDEV1>; 656 648 clock-names = "pll_a", "pll_a_out0", "mclk"; 657 649 }; 658 650 };
+39 -8
arch/arm/boot/dts/tegra20-whistler.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra20.dtsi" 3 + #include "tegra20.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Tegra20 Whistler evaluation board"; ··· 18 18 pll-supply = <&hdmi_pll_reg>; 19 19 20 20 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 21 - nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ 21 + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 22 + GPIO_ACTIVE_HIGH>; 22 23 }; 23 24 }; 24 25 ··· 282 281 max8907@3c { 283 282 compatible = "maxim,max8907"; 284 283 reg = <0x3c>; 285 - interrupts = <0 86 0x4>; 284 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 286 285 287 286 maxim,system-power-controller; 288 287 ··· 509 508 510 509 usb@c5000000 { 511 510 status = "okay"; 512 - nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ 511 + nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>; 512 + }; 513 + 514 + usb-phy@c5000000 { 515 + status = "okay"; 516 + vbus-supply = <&vbus1_reg>; 513 517 }; 514 518 515 519 usb@c5008000 { 516 520 status = "okay"; 517 - nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ 521 + nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>; 522 + }; 523 + 524 + usb-phy@c5008000 { 525 + status = "okay"; 526 + vbus-supply = <&vbus3_reg>; 518 527 }; 519 528 520 529 sdhci@c8000400 { 521 530 status = "okay"; 522 - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 523 - wp-gpios = <&gpio 173 0>; /* gpio PV5 */ 531 + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 532 + wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; 524 533 bus-width = <8>; 525 534 }; 526 535 ··· 579 568 regulator-max-microvolt = <5000000>; 580 569 regulator-always-on; 581 570 }; 571 + 572 + vbus1_reg: regulator@2 { 573 + compatible = "regulator-fixed"; 574 + reg = <2>; 575 + regulator-name = "vbus1"; 576 + regulator-min-microvolt = <5000000>; 577 + regulator-max-microvolt = <5000000>; 578 + gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ 579 + }; 580 + 581 + vbus3_reg: regulator@3 { 582 + compatible = "regulator-fixed"; 583 + reg = <3>; 584 + regulator-name = "vbus3"; 585 + regulator-min-microvolt = <5000000>; 586 + regulator-max-microvolt = <5000000>; 587 + gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ 588 + }; 582 589 }; 583 590 584 591 sound { ··· 613 584 nvidia,i2s-controller = <&tegra_i2s1>; 614 585 nvidia,audio-codec = <&codec>; 615 586 616 - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; 587 + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 588 + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 589 + <&tegra_car TEGRA20_CLK_CDEV1>; 617 590 clock-names = "pll_a", "pll_a_out0", "mclk"; 618 591 }; 619 592 };
+161 -124
arch/arm/boot/dts/tegra20.dtsi
··· 1 - /include/ "skeleton.dtsi" 1 + #include <dt-bindings/clock/tegra20-car.h> 2 + #include <dt-bindings/gpio/tegra-gpio.h> 3 + #include <dt-bindings/interrupt-controller/arm-gic.h> 4 + 5 + #include "skeleton.dtsi" 2 6 3 7 / { 4 8 compatible = "nvidia,tegra20"; ··· 19 15 host1x { 20 16 compatible = "nvidia,tegra20-host1x", "simple-bus"; 21 17 reg = <0x50000000 0x00024000>; 22 - interrupts = <0 65 0x04 /* mpcore syncpt */ 23 - 0 67 0x04>; /* mpcore general */ 24 - clocks = <&tegra_car 28>; 18 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 19 + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 20 + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 25 21 26 22 #address-cells = <1>; 27 23 #size-cells = <1>; ··· 31 27 mpe { 32 28 compatible = "nvidia,tegra20-mpe"; 33 29 reg = <0x54040000 0x00040000>; 34 - interrupts = <0 68 0x04>; 35 - clocks = <&tegra_car 60>; 30 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 31 + clocks = <&tegra_car TEGRA20_CLK_MPE>; 36 32 }; 37 33 38 34 vi { 39 35 compatible = "nvidia,tegra20-vi"; 40 36 reg = <0x54080000 0x00040000>; 41 - interrupts = <0 69 0x04>; 42 - clocks = <&tegra_car 100>; 37 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 38 + clocks = <&tegra_car TEGRA20_CLK_VI>; 43 39 }; 44 40 45 41 epp { 46 42 compatible = "nvidia,tegra20-epp"; 47 43 reg = <0x540c0000 0x00040000>; 48 - interrupts = <0 70 0x04>; 49 - clocks = <&tegra_car 19>; 44 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 45 + clocks = <&tegra_car TEGRA20_CLK_EPP>; 50 46 }; 51 47 52 48 isp { 53 49 compatible = "nvidia,tegra20-isp"; 54 50 reg = <0x54100000 0x00040000>; 55 - interrupts = <0 71 0x04>; 56 - clocks = <&tegra_car 23>; 51 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 52 + clocks = <&tegra_car TEGRA20_CLK_ISP>; 57 53 }; 58 54 59 55 gr2d { 60 56 compatible = "nvidia,tegra20-gr2d"; 61 57 reg = <0x54140000 0x00040000>; 62 - interrupts = <0 72 0x04>; 63 - clocks = <&tegra_car 21>; 58 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 59 + clocks = <&tegra_car TEGRA20_CLK_GR2D>; 64 60 }; 65 61 66 62 gr3d { 67 63 compatible = "nvidia,tegra20-gr3d"; 68 64 reg = <0x54180000 0x00040000>; 69 - clocks = <&tegra_car 24>; 65 + clocks = <&tegra_car TEGRA20_CLK_GR3D>; 70 66 }; 71 67 72 68 dc@54200000 { 73 69 compatible = "nvidia,tegra20-dc"; 74 70 reg = <0x54200000 0x00040000>; 75 - interrupts = <0 73 0x04>; 76 - clocks = <&tegra_car 27>, <&tegra_car 121>; 71 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 72 + clocks = <&tegra_car TEGRA20_CLK_DISP1>, 73 + <&tegra_car TEGRA20_CLK_PLL_P>; 77 74 clock-names = "disp1", "parent"; 78 75 79 76 rgb { ··· 85 80 dc@54240000 { 86 81 compatible = "nvidia,tegra20-dc"; 87 82 reg = <0x54240000 0x00040000>; 88 - interrupts = <0 74 0x04>; 89 - clocks = <&tegra_car 26>, <&tegra_car 121>; 83 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 84 + clocks = <&tegra_car TEGRA20_CLK_DISP2>, 85 + <&tegra_car TEGRA20_CLK_PLL_P>; 90 86 clock-names = "disp2", "parent"; 91 87 92 88 rgb { ··· 98 92 hdmi { 99 93 compatible = "nvidia,tegra20-hdmi"; 100 94 reg = <0x54280000 0x00040000>; 101 - interrupts = <0 75 0x04>; 102 - clocks = <&tegra_car 51>, <&tegra_car 117>; 95 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 96 + clocks = <&tegra_car TEGRA20_CLK_HDMI>, 97 + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 103 98 clock-names = "hdmi", "parent"; 104 99 status = "disabled"; 105 100 }; ··· 108 101 tvo { 109 102 compatible = "nvidia,tegra20-tvo"; 110 103 reg = <0x542c0000 0x00040000>; 111 - interrupts = <0 76 0x04>; 112 - clocks = <&tegra_car 102>; 104 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 105 + clocks = <&tegra_car TEGRA20_CLK_TVO>; 113 106 status = "disabled"; 114 107 }; 115 108 116 109 dsi { 117 110 compatible = "nvidia,tegra20-dsi"; 118 111 reg = <0x54300000 0x00040000>; 119 - clocks = <&tegra_car 48>; 112 + clocks = <&tegra_car TEGRA20_CLK_DSI>; 120 113 status = "disabled"; 121 114 }; 122 115 }; ··· 124 117 timer@50004600 { 125 118 compatible = "arm,cortex-a9-twd-timer"; 126 119 reg = <0x50040600 0x20>; 127 - interrupts = <1 13 0x304>; 128 - clocks = <&tegra_car 132>; 120 + interrupts = <GIC_PPI 13 121 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 122 + clocks = <&tegra_car TEGRA20_CLK_TWD>; 129 123 }; 130 124 131 125 intc: interrupt-controller { ··· 149 141 timer@60005000 { 150 142 compatible = "nvidia,tegra20-timer"; 151 143 reg = <0x60005000 0x60>; 152 - interrupts = <0 0 0x04 153 - 0 1 0x04 154 - 0 41 0x04 155 - 0 42 0x04>; 156 - clocks = <&tegra_car 5>; 144 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 145 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 146 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 147 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 148 + clocks = <&tegra_car TEGRA20_CLK_TIMER>; 157 149 }; 158 150 159 151 tegra_car: clock { ··· 165 157 apbdma: dma { 166 158 compatible = "nvidia,tegra20-apbdma"; 167 159 reg = <0x6000a000 0x1200>; 168 - interrupts = <0 104 0x04 169 - 0 105 0x04 170 - 0 106 0x04 171 - 0 107 0x04 172 - 0 108 0x04 173 - 0 109 0x04 174 - 0 110 0x04 175 - 0 111 0x04 176 - 0 112 0x04 177 - 0 113 0x04 178 - 0 114 0x04 179 - 0 115 0x04 180 - 0 116 0x04 181 - 0 117 0x04 182 - 0 118 0x04 183 - 0 119 0x04>; 184 - clocks = <&tegra_car 34>; 160 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 161 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 162 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 163 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 164 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 165 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 166 + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 168 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 169 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 170 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 171 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 172 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 173 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 174 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 175 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 176 + clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 185 177 }; 186 178 187 179 ahb { ··· 192 184 gpio: gpio { 193 185 compatible = "nvidia,tegra20-gpio"; 194 186 reg = <0x6000d000 0x1000>; 195 - interrupts = <0 32 0x04 196 - 0 33 0x04 197 - 0 34 0x04 198 - 0 35 0x04 199 - 0 55 0x04 200 - 0 87 0x04 201 - 0 89 0x04>; 187 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 188 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 189 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 190 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 191 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 192 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 193 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 202 194 #gpio-cells = <2>; 203 195 gpio-controller; 204 196 #interrupt-cells = <2>; ··· 221 213 tegra_ac97: ac97 { 222 214 compatible = "nvidia,tegra20-ac97"; 223 215 reg = <0x70002000 0x200>; 224 - interrupts = <0 81 0x04>; 216 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 225 217 nvidia,dma-request-selector = <&apbdma 12>; 226 - clocks = <&tegra_car 3>; 218 + clocks = <&tegra_car TEGRA20_CLK_AC97>; 227 219 status = "disabled"; 228 220 }; 229 221 230 222 tegra_i2s1: i2s@70002800 { 231 223 compatible = "nvidia,tegra20-i2s"; 232 224 reg = <0x70002800 0x200>; 233 - interrupts = <0 13 0x04>; 225 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 234 226 nvidia,dma-request-selector = <&apbdma 2>; 235 - clocks = <&tegra_car 11>; 227 + clocks = <&tegra_car TEGRA20_CLK_I2S1>; 236 228 status = "disabled"; 237 229 }; 238 230 239 231 tegra_i2s2: i2s@70002a00 { 240 232 compatible = "nvidia,tegra20-i2s"; 241 233 reg = <0x70002a00 0x200>; 242 - interrupts = <0 3 0x04>; 234 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 243 235 nvidia,dma-request-selector = <&apbdma 1>; 244 - clocks = <&tegra_car 18>; 236 + clocks = <&tegra_car TEGRA20_CLK_I2S2>; 245 237 status = "disabled"; 246 238 }; 247 239 ··· 256 248 compatible = "nvidia,tegra20-uart"; 257 249 reg = <0x70006000 0x40>; 258 250 reg-shift = <2>; 259 - interrupts = <0 36 0x04>; 251 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 260 252 nvidia,dma-request-selector = <&apbdma 8>; 261 - clocks = <&tegra_car 6>; 253 + clocks = <&tegra_car TEGRA20_CLK_UARTA>; 262 254 status = "disabled"; 263 255 }; 264 256 ··· 266 258 compatible = "nvidia,tegra20-uart"; 267 259 reg = <0x70006040 0x40>; 268 260 reg-shift = <2>; 269 - interrupts = <0 37 0x04>; 261 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 270 262 nvidia,dma-request-selector = <&apbdma 9>; 271 - clocks = <&tegra_car 96>; 263 + clocks = <&tegra_car TEGRA20_CLK_UARTB>; 272 264 status = "disabled"; 273 265 }; 274 266 ··· 276 268 compatible = "nvidia,tegra20-uart"; 277 269 reg = <0x70006200 0x100>; 278 270 reg-shift = <2>; 279 - interrupts = <0 46 0x04>; 271 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 280 272 nvidia,dma-request-selector = <&apbdma 10>; 281 - clocks = <&tegra_car 55>; 273 + clocks = <&tegra_car TEGRA20_CLK_UARTC>; 282 274 status = "disabled"; 283 275 }; 284 276 ··· 286 278 compatible = "nvidia,tegra20-uart"; 287 279 reg = <0x70006300 0x100>; 288 280 reg-shift = <2>; 289 - interrupts = <0 90 0x04>; 281 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 290 282 nvidia,dma-request-selector = <&apbdma 19>; 291 - clocks = <&tegra_car 65>; 283 + clocks = <&tegra_car TEGRA20_CLK_UARTD>; 292 284 status = "disabled"; 293 285 }; 294 286 ··· 296 288 compatible = "nvidia,tegra20-uart"; 297 289 reg = <0x70006400 0x100>; 298 290 reg-shift = <2>; 299 - interrupts = <0 91 0x04>; 291 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 300 292 nvidia,dma-request-selector = <&apbdma 20>; 301 - clocks = <&tegra_car 66>; 293 + clocks = <&tegra_car TEGRA20_CLK_UARTE>; 302 294 status = "disabled"; 303 295 }; 304 296 ··· 306 298 compatible = "nvidia,tegra20-pwm"; 307 299 reg = <0x7000a000 0x100>; 308 300 #pwm-cells = <2>; 309 - clocks = <&tegra_car 17>; 301 + clocks = <&tegra_car TEGRA20_CLK_PWM>; 310 302 status = "disabled"; 311 303 }; 312 304 313 305 rtc { 314 306 compatible = "nvidia,tegra20-rtc"; 315 307 reg = <0x7000e000 0x100>; 316 - interrupts = <0 2 0x04>; 317 - clocks = <&tegra_car 4>; 308 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 309 + clocks = <&tegra_car TEGRA20_CLK_RTC>; 318 310 }; 319 311 320 312 i2c@7000c000 { 321 313 compatible = "nvidia,tegra20-i2c"; 322 314 reg = <0x7000c000 0x100>; 323 - interrupts = <0 38 0x04>; 315 + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 324 316 #address-cells = <1>; 325 317 #size-cells = <0>; 326 - clocks = <&tegra_car 12>, <&tegra_car 124>; 318 + clocks = <&tegra_car TEGRA20_CLK_I2C1>, 319 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 327 320 clock-names = "div-clk", "fast-clk"; 328 321 status = "disabled"; 329 322 }; ··· 332 323 spi@7000c380 { 333 324 compatible = "nvidia,tegra20-sflash"; 334 325 reg = <0x7000c380 0x80>; 335 - interrupts = <0 39 0x04>; 326 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 336 327 nvidia,dma-request-selector = <&apbdma 11>; 337 328 #address-cells = <1>; 338 329 #size-cells = <0>; 339 - clocks = <&tegra_car 43>; 330 + clocks = <&tegra_car TEGRA20_CLK_SPI>; 340 331 status = "disabled"; 341 332 }; 342 333 343 334 i2c@7000c400 { 344 335 compatible = "nvidia,tegra20-i2c"; 345 336 reg = <0x7000c400 0x100>; 346 - interrupts = <0 84 0x04>; 337 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 347 338 #address-cells = <1>; 348 339 #size-cells = <0>; 349 - clocks = <&tegra_car 54>, <&tegra_car 124>; 340 + clocks = <&tegra_car TEGRA20_CLK_I2C2>, 341 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 350 342 clock-names = "div-clk", "fast-clk"; 351 343 status = "disabled"; 352 344 }; ··· 355 345 i2c@7000c500 { 356 346 compatible = "nvidia,tegra20-i2c"; 357 347 reg = <0x7000c500 0x100>; 358 - interrupts = <0 92 0x04>; 348 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 359 349 #address-cells = <1>; 360 350 #size-cells = <0>; 361 - clocks = <&tegra_car 67>, <&tegra_car 124>; 351 + clocks = <&tegra_car TEGRA20_CLK_I2C3>, 352 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 362 353 clock-names = "div-clk", "fast-clk"; 363 354 status = "disabled"; 364 355 }; ··· 367 356 i2c@7000d000 { 368 357 compatible = "nvidia,tegra20-i2c-dvc"; 369 358 reg = <0x7000d000 0x200>; 370 - interrupts = <0 53 0x04>; 359 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 371 360 #address-cells = <1>; 372 361 #size-cells = <0>; 373 - clocks = <&tegra_car 47>, <&tegra_car 124>; 362 + clocks = <&tegra_car TEGRA20_CLK_DVC>, 363 + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 374 364 clock-names = "div-clk", "fast-clk"; 375 365 status = "disabled"; 376 366 }; ··· 379 367 spi@7000d400 { 380 368 compatible = "nvidia,tegra20-slink"; 381 369 reg = <0x7000d400 0x200>; 382 - interrupts = <0 59 0x04>; 370 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 383 371 nvidia,dma-request-selector = <&apbdma 15>; 384 372 #address-cells = <1>; 385 373 #size-cells = <0>; 386 - clocks = <&tegra_car 41>; 374 + clocks = <&tegra_car TEGRA20_CLK_SBC1>; 387 375 status = "disabled"; 388 376 }; 389 377 390 378 spi@7000d600 { 391 379 compatible = "nvidia,tegra20-slink"; 392 380 reg = <0x7000d600 0x200>; 393 - interrupts = <0 82 0x04>; 381 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 394 382 nvidia,dma-request-selector = <&apbdma 16>; 395 383 #address-cells = <1>; 396 384 #size-cells = <0>; 397 - clocks = <&tegra_car 44>; 385 + clocks = <&tegra_car TEGRA20_CLK_SBC2>; 398 386 status = "disabled"; 399 387 }; 400 388 401 389 spi@7000d800 { 402 390 compatible = "nvidia,tegra20-slink"; 403 391 reg = <0x7000d800 0x200>; 404 - interrupts = <0 83 0x04>; 392 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 405 393 nvidia,dma-request-selector = <&apbdma 17>; 406 394 #address-cells = <1>; 407 395 #size-cells = <0>; 408 - clocks = <&tegra_car 46>; 396 + clocks = <&tegra_car TEGRA20_CLK_SBC3>; 409 397 status = "disabled"; 410 398 }; 411 399 412 400 spi@7000da00 { 413 401 compatible = "nvidia,tegra20-slink"; 414 402 reg = <0x7000da00 0x200>; 415 - interrupts = <0 93 0x04>; 403 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 416 404 nvidia,dma-request-selector = <&apbdma 18>; 417 405 #address-cells = <1>; 418 406 #size-cells = <0>; 419 - clocks = <&tegra_car 68>; 407 + clocks = <&tegra_car TEGRA20_CLK_SBC4>; 420 408 status = "disabled"; 421 409 }; 422 410 423 411 kbc { 424 412 compatible = "nvidia,tegra20-kbc"; 425 413 reg = <0x7000e200 0x100>; 426 - interrupts = <0 85 0x04>; 427 - clocks = <&tegra_car 36>; 414 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 415 + clocks = <&tegra_car TEGRA20_CLK_KBC>; 428 416 status = "disabled"; 429 417 }; 430 418 431 419 pmc { 432 420 compatible = "nvidia,tegra20-pmc"; 433 421 reg = <0x7000e400 0x400>; 434 - clocks = <&tegra_car 110>, <&clk32k_in>; 422 + clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 435 423 clock-names = "pclk", "clk32k_in"; 436 424 }; 437 425 ··· 439 427 compatible = "nvidia,tegra20-mc"; 440 428 reg = <0x7000f000 0x024 441 429 0x7000f03c 0x3c4>; 442 - interrupts = <0 77 0x04>; 430 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 443 431 }; 444 432 445 433 iommu { ··· 458 446 usb@c5000000 { 459 447 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 460 448 reg = <0xc5000000 0x4000>; 461 - interrupts = <0 20 0x04>; 449 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 462 450 phy_type = "utmi"; 463 451 nvidia,has-legacy-mode; 464 - clocks = <&tegra_car 22>; 452 + clocks = <&tegra_car TEGRA20_CLK_USBD>; 465 453 nvidia,needs-double-reset; 466 454 nvidia,phy = <&phy1>; 467 455 status = "disabled"; 468 456 }; 469 457 470 - phy1: usb-phy@c5000400 { 458 + phy1: usb-phy@c5000000 { 471 459 compatible = "nvidia,tegra20-usb-phy"; 472 - reg = <0xc5000400 0x3c00>; 460 + reg = <0xc5000000 0x4000 0xc5000000 0x4000>; 473 461 phy_type = "utmi"; 462 + clocks = <&tegra_car TEGRA20_CLK_USBD>, 463 + <&tegra_car TEGRA20_CLK_PLL_U>, 464 + <&tegra_car TEGRA20_CLK_CLK_M>, 465 + <&tegra_car TEGRA20_CLK_USBD>; 466 + clock-names = "reg", "pll_u", "timer", "utmi-pads"; 474 467 nvidia,has-legacy-mode; 475 - clocks = <&tegra_car 22>, <&tegra_car 127>; 476 - clock-names = "phy", "pll_u"; 468 + hssync_start_delay = <9>; 469 + idle_wait_delay = <17>; 470 + elastic_limit = <16>; 471 + term_range_adj = <6>; 472 + xcvr_setup = <9>; 473 + xcvr_lsfslew = <1>; 474 + xcvr_lsrslew = <1>; 475 + status = "disabled"; 477 476 }; 478 477 479 478 usb@c5004000 { 480 479 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 481 480 reg = <0xc5004000 0x4000>; 482 - interrupts = <0 21 0x04>; 481 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 483 482 phy_type = "ulpi"; 484 - clocks = <&tegra_car 58>; 483 + clocks = <&tegra_car TEGRA20_CLK_USB2>; 485 484 nvidia,phy = <&phy2>; 486 485 status = "disabled"; 487 486 }; 488 487 489 - phy2: usb-phy@c5004400 { 488 + phy2: usb-phy@c5004000 { 490 489 compatible = "nvidia,tegra20-usb-phy"; 491 - reg = <0xc5004400 0x3c00>; 490 + reg = <0xc5004000 0x4000>; 492 491 phy_type = "ulpi"; 493 - clocks = <&tegra_car 93>, <&tegra_car 127>; 494 - clock-names = "phy", "pll_u"; 492 + clocks = <&tegra_car TEGRA20_CLK_USB2>, 493 + <&tegra_car TEGRA20_CLK_PLL_U>, 494 + <&tegra_car TEGRA20_CLK_CDEV2>; 495 + clock-names = "reg", "pll_u", "ulpi-link"; 496 + status = "disabled"; 495 497 }; 496 498 497 499 usb@c5008000 { 498 500 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 499 501 reg = <0xc5008000 0x4000>; 500 - interrupts = <0 97 0x04>; 502 + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 501 503 phy_type = "utmi"; 502 - clocks = <&tegra_car 59>; 504 + clocks = <&tegra_car TEGRA20_CLK_USB3>; 503 505 nvidia,phy = <&phy3>; 504 506 status = "disabled"; 505 507 }; 506 508 507 - phy3: usb-phy@c5008400 { 509 + phy3: usb-phy@c5008000 { 508 510 compatible = "nvidia,tegra20-usb-phy"; 509 - reg = <0xc5008400 0x3c00>; 511 + reg = <0xc5008000 0x4000 0xc5000000 0x4000>; 510 512 phy_type = "utmi"; 511 - clocks = <&tegra_car 22>, <&tegra_car 127>; 512 - clock-names = "phy", "pll_u"; 513 + clocks = <&tegra_car TEGRA20_CLK_USB3>, 514 + <&tegra_car TEGRA20_CLK_PLL_U>, 515 + <&tegra_car TEGRA20_CLK_CLK_M>, 516 + <&tegra_car TEGRA20_CLK_USBD>; 517 + clock-names = "reg", "pll_u", "timer", "utmi-pads"; 518 + hssync_start_delay = <9>; 519 + idle_wait_delay = <17>; 520 + elastic_limit = <16>; 521 + term_range_adj = <6>; 522 + xcvr_setup = <9>; 523 + xcvr_lsfslew = <2>; 524 + xcvr_lsrslew = <2>; 525 + status = "disabled"; 513 526 }; 514 527 515 528 sdhci@c8000000 { 516 529 compatible = "nvidia,tegra20-sdhci"; 517 530 reg = <0xc8000000 0x200>; 518 - interrupts = <0 14 0x04>; 519 - clocks = <&tegra_car 14>; 531 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 532 + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 520 533 status = "disabled"; 521 534 }; 522 535 523 536 sdhci@c8000200 { 524 537 compatible = "nvidia,tegra20-sdhci"; 525 538 reg = <0xc8000200 0x200>; 526 - interrupts = <0 15 0x04>; 527 - clocks = <&tegra_car 9>; 539 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 540 + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 528 541 status = "disabled"; 529 542 }; 530 543 531 544 sdhci@c8000400 { 532 545 compatible = "nvidia,tegra20-sdhci"; 533 546 reg = <0xc8000400 0x200>; 534 - interrupts = <0 19 0x04>; 535 - clocks = <&tegra_car 69>; 547 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 548 + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 536 549 status = "disabled"; 537 550 }; 538 551 539 552 sdhci@c8000600 { 540 553 compatible = "nvidia,tegra20-sdhci"; 541 554 reg = <0xc8000600 0x200>; 542 - interrupts = <0 31 0x04>; 543 - clocks = <&tegra_car 15>; 555 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 556 + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 544 557 status = "disabled"; 545 558 }; 546 559 ··· 588 551 589 552 pmu { 590 553 compatible = "arm,cortex-a9-pmu"; 591 - interrupts = <0 56 0x04 592 - 0 57 0x04>; 554 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 555 + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 593 556 }; 594 557 };
+55 -13
arch/arm/boot/dts/tegra30-beaver.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra30.dtsi" 3 + #include "tegra30.dtsi" 4 4 5 5 / { 6 6 model = "NVIDIA Tegra30 Beaver evaluation board"; 7 7 compatible = "nvidia,beaver", "nvidia,tegra30"; 8 8 9 9 memory { 10 - reg = <0x80000000 0x80000000>; 10 + reg = <0x80000000 0x7ff00000>; 11 11 }; 12 12 13 13 pinmux { ··· 116 116 status = "okay"; 117 117 clock-frequency = <100000>; 118 118 119 + rt5640: rt5640 { 120 + compatible = "realtek,rt5640"; 121 + reg = <0x1c>; 122 + interrupt-parent = <&gpio>; 123 + interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; 124 + realtek,ldo1-en-gpios = 125 + <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; 126 + }; 127 + 119 128 tps62361 { 120 129 compatible = "ti,tps62361"; 121 130 reg = <0x60>; ··· 142 133 compatible = "ti,tps65911"; 143 134 reg = <0x2d>; 144 135 145 - interrupts = <0 86 0x4>; 136 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 146 137 #interrupt-cells = <2>; 147 138 interrupt-controller; 148 139 ··· 273 264 274 265 sdhci@78000000 { 275 266 status = "okay"; 276 - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 277 - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 278 - power-gpios = <&gpio 31 0>; /* gpio PD7 */ 267 + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 268 + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 269 + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; 279 270 bus-width = <4>; 280 271 }; 281 272 ··· 321 312 regulator-boot-on; 322 313 regulator-always-on; 323 314 enable-active-high; 324 - gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ 315 + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 325 316 }; 326 317 327 318 ddr_reg: regulator@2 { ··· 333 324 regulator-always-on; 334 325 regulator-boot-on; 335 326 enable-active-high; 336 - gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */ 327 + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 337 328 vin-supply = <&vdd_5v_in_reg>; 338 329 }; 339 330 ··· 346 337 regulator-always-on; 347 338 regulator-boot-on; 348 339 enable-active-high; 349 - gpio = <&gpio 30 0>; /* gpio PD6 */ 340 + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; 350 341 vin-supply = <&vdd_5v_in_reg>; 351 342 }; 352 343 ··· 357 348 regulator-min-microvolt = <5000000>; 358 349 regulator-max-microvolt = <5000000>; 359 350 enable-active-high; 360 - gpio = <&gpio 68 0>; /* GPIO PI4 */ 351 + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; 361 352 gpio-open-drain; 362 353 vin-supply = <&vdd_5v_in_reg>; 363 354 }; ··· 369 360 regulator-min-microvolt = <5000000>; 370 361 regulator-max-microvolt = <5000000>; 371 362 enable-active-high; 372 - gpio = <&gpio 63 0>; /* GPIO PH7 */ 363 + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; 373 364 gpio-open-drain; 374 365 vin-supply = <&vdd_5v_in_reg>; 375 366 }; ··· 383 374 regulator-always-on; 384 375 regulator-boot-on; 385 376 enable-active-high; 386 - gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */ 377 + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 387 378 vin-supply = <&vdd_5v_in_reg>; 388 379 }; 389 380 ··· 396 387 regulator-always-on; 397 388 regulator-boot-on; 398 389 enable-active-high; 399 - gpio = <&gpio 95 0>; /* gpio PL7 */ 390 + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; 400 391 vin-supply = <&sys_3v3_reg>; 401 392 }; 393 + }; 394 + 395 + gpio-leds { 396 + compatible = "gpio-leds"; 397 + 398 + gpled1 { 399 + label = "LED1"; /* CR5A1 (blue) */ 400 + gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; 401 + }; 402 + gpled2 { 403 + label = "LED2"; /* CR4A2 (green) */ 404 + gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; 405 + }; 406 + }; 407 + 408 + sound { 409 + compatible = "nvidia,tegra-audio-rt5640-beaver", 410 + "nvidia,tegra-audio-rt5640"; 411 + nvidia,model = "NVIDIA Tegra Beaver"; 412 + 413 + nvidia,audio-routing = 414 + "Headphones", "HPOR", 415 + "Headphones", "HPOL"; 416 + 417 + nvidia,i2s-controller = <&tegra_i2s1>; 418 + nvidia,audio-codec = <&rt5640>; 419 + 420 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 421 + 422 + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 423 + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 424 + <&tegra_car TEGRA30_CLK_EXTERN1>; 425 + clock-names = "pll_a", "pll_a_out0", "mclk"; 402 426 }; 403 427 };
+8 -8
arch/arm/boot/dts/tegra30-cardhu-a02.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra30-cardhu.dtsi" 3 + #include "tegra30-cardhu.dtsi" 4 4 5 5 /* This dts file support the cardhu A02 version of board */ 6 6 ··· 22 22 regulator-always-on; 23 23 regulator-boot-on; 24 24 enable-active-high; 25 - gpio = <&pmic 6 0>; 25 + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 26 26 }; 27 27 28 28 sys_3v3_reg: regulator@101 { ··· 34 34 regulator-always-on; 35 35 regulator-boot-on; 36 36 enable-active-high; 37 - gpio = <&pmic 7 0>; 37 + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 38 38 }; 39 39 40 40 usb1_vbus_reg: regulator@102 { ··· 44 44 regulator-min-microvolt = <5000000>; 45 45 regulator-max-microvolt = <5000000>; 46 46 enable-active-high; 47 - gpio = <&gpio 68 0>; /* GPIO PI4 */ 47 + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; 48 48 gpio-open-drain; 49 49 vin-supply = <&vdd_5v0_reg>; 50 50 }; ··· 56 56 regulator-min-microvolt = <5000000>; 57 57 regulator-max-microvolt = <5000000>; 58 58 enable-active-high; 59 - gpio = <&gpio 63 0>; /* GPIO PH7 */ 59 + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; 60 60 gpio-open-drain; 61 61 vin-supply = <&vdd_5v0_reg>; 62 62 }; ··· 68 68 regulator-min-microvolt = <5000000>; 69 69 regulator-max-microvolt = <5000000>; 70 70 enable-active-high; 71 - gpio = <&pmic 2 0>; 71 + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 72 72 }; 73 73 74 74 vdd_bl_reg: regulator@105 { ··· 80 80 regulator-always-on; 81 81 regulator-boot-on; 82 82 enable-active-high; 83 - gpio = <&gpio 83 0>; /* GPIO PK3 */ 83 + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; 84 84 }; 85 85 }; 86 86 87 87 sdhci@78000400 { 88 88 status = "okay"; 89 - power-gpios = <&gpio 28 0>; /* gpio PD4 */ 89 + power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 90 90 bus-width = <4>; 91 91 keep-power-in-suspend; 92 92 };
+9 -9
arch/arm/boot/dts/tegra30-cardhu-a04.dts
··· 1 1 /dts-v1/; 2 2 3 - /include/ "tegra30-cardhu.dtsi" 3 + #include "tegra30-cardhu.dtsi" 4 4 5 5 /* This dts file support the cardhu A04 and later versions of board */ 6 6 ··· 22 22 regulator-always-on; 23 23 regulator-boot-on; 24 24 enable-active-high; 25 - gpio = <&pmic 7 0>; 25 + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 26 26 }; 27 27 28 28 sys_3v3_reg: regulator@101 { ··· 34 34 regulator-always-on; 35 35 regulator-boot-on; 36 36 enable-active-high; 37 - gpio = <&pmic 6 0>; 37 + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 38 38 }; 39 39 40 40 usb1_vbus_reg: regulator@102 { ··· 44 44 regulator-min-microvolt = <5000000>; 45 45 regulator-max-microvolt = <5000000>; 46 46 enable-active-high; 47 - gpio = <&gpio 238 0>; /* GPIO PDD6 */ 47 + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; 48 48 gpio-open-drain; 49 49 vin-supply = <&vdd_5v0_reg>; 50 50 }; ··· 56 56 regulator-min-microvolt = <5000000>; 57 57 regulator-max-microvolt = <5000000>; 58 58 enable-active-high; 59 - gpio = <&gpio 236 0>; /* GPIO PDD4 */ 59 + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; 60 60 gpio-open-drain; 61 61 vin-supply = <&vdd_5v0_reg>; 62 62 }; ··· 68 68 regulator-min-microvolt = <5000000>; 69 69 regulator-max-microvolt = <5000000>; 70 70 enable-active-high; 71 - gpio = <&pmic 8 0>; 71 + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; 72 72 }; 73 73 74 74 vdd_bl_reg: regulator@105 { ··· 80 80 regulator-always-on; 81 81 regulator-boot-on; 82 82 enable-active-high; 83 - gpio = <&gpio 234 0>; /* GPIO PDD2 */ 83 + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; 84 84 }; 85 85 86 86 vdd_bl2_reg: regulator@106 { ··· 92 92 regulator-always-on; 93 93 regulator-boot-on; 94 94 enable-active-high; 95 - gpio = <&gpio 232 0>; /* GPIO PDD0 */ 95 + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; 96 96 }; 97 97 }; 98 98 99 99 sdhci@78000400 { 100 100 status = "okay"; 101 - power-gpios = <&gpio 27 0>; /* gpio PD3 */ 101 + power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; 102 102 bus-width = <4>; 103 103 keep-power-in-suspend; 104 104 };
+25 -22
arch/arm/boot/dts/tegra30-cardhu.dtsi
··· 1 - /include/ "tegra30.dtsi" 1 + #include "tegra30.dtsi" 2 2 3 3 /** 4 4 * This file contains common DT entry for all fab version of Cardhu. ··· 146 146 compatible = "isil,isl29028"; 147 147 reg = <0x44>; 148 148 interrupt-parent = <&gpio>; 149 - interrupts = <88 0x04>; /*gpio PL0 */ 149 + interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; 150 150 }; 151 151 }; 152 152 ··· 163 163 compatible = "wlf,wm8903"; 164 164 reg = <0x1a>; 165 165 interrupt-parent = <&gpio>; 166 - interrupts = <179 0x04>; /* gpio PW3 */ 166 + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>; 167 167 168 168 gpio-controller; 169 169 #gpio-cells = <2>; ··· 190 190 compatible = "ti,tps65911"; 191 191 reg = <0x2d>; 192 192 193 - interrupts = <0 86 0x4>; 193 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 194 194 #interrupt-cells = <2>; 195 195 interrupt-controller; 196 196 ··· 318 318 319 319 sdhci@78000000 { 320 320 status = "okay"; 321 - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ 322 - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 323 - power-gpios = <&gpio 31 0>; /* gpio PD7 */ 321 + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 322 + wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 323 + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; 324 324 bus-width = <4>; 325 325 }; 326 326 ··· 364 364 regulator-min-microvolt = <1800000>; 365 365 regulator-max-microvolt = <1800000>; 366 366 enable-active-high; 367 - gpio = <&gpio 220 0>; /* gpio PBB4 */ 367 + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; 368 368 vin-supply = <&vio_reg>; 369 369 }; 370 370 ··· 377 377 regulator-boot-on; 378 378 regulator-always-on; 379 379 enable-active-high; 380 - gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ 380 + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 381 381 }; 382 382 383 383 emmc_3v3_reg: regulator@3 { ··· 389 389 regulator-always-on; 390 390 regulator-boot-on; 391 391 enable-active-high; 392 - gpio = <&gpio 25 0>; /* gpio PD1 */ 392 + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; 393 393 vin-supply = <&sys_3v3_reg>; 394 394 }; 395 395 ··· 400 400 regulator-min-microvolt = <3300000>; 401 401 regulator-max-microvolt = <3300000>; 402 402 enable-active-high; 403 - gpio = <&gpio 30 0>; /* gpio PD6 */ 403 + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; 404 404 }; 405 405 406 406 pex_hvdd_3v3_reg: regulator@5 { ··· 410 410 regulator-min-microvolt = <3300000>; 411 411 regulator-max-microvolt = <3300000>; 412 412 enable-active-high; 413 - gpio = <&gpio 95 0>; /* gpio PL7 */ 413 + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; 414 414 vin-supply = <&sys_3v3_reg>; 415 415 }; 416 416 ··· 421 421 regulator-min-microvolt = <2800000>; 422 422 regulator-max-microvolt = <2800000>; 423 423 enable-active-high; 424 - gpio = <&gpio 142 0>; /* gpio PR6 */ 424 + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; 425 425 vin-supply = <&sys_3v3_reg>; 426 426 }; 427 427 ··· 432 432 regulator-min-microvolt = <2800000>; 433 433 regulator-max-microvolt = <2800000>; 434 434 enable-active-high; 435 - gpio = <&gpio 143 0>; /* gpio PR7 */ 435 + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; 436 436 vin-supply = <&sys_3v3_reg>; 437 437 }; 438 438 ··· 443 443 regulator-min-microvolt = <3300000>; 444 444 regulator-max-microvolt = <3300000>; 445 445 enable-active-high; 446 - gpio = <&gpio 144 0>; /* gpio PS0 */ 446 + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; 447 447 vin-supply = <&sys_3v3_reg>; 448 448 }; 449 449 ··· 456 456 regulator-always-on; 457 457 regulator-boot-on; 458 458 enable-active-high; 459 - gpio = <&gpio 24 0>; /* gpio PD0 */ 459 + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 460 460 vin-supply = <&sys_3v3_reg>; 461 461 }; 462 462 ··· 467 467 regulator-min-microvolt = <3300000>; 468 468 regulator-max-microvolt = <3300000>; 469 469 enable-active-high; 470 - gpio = <&gpio 94 0>; /* gpio PL6 */ 470 + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; 471 471 vin-supply = <&sys_3v3_reg>; 472 472 }; 473 473 ··· 480 480 regulator-always-on; 481 481 regulator-boot-on; 482 482 enable-active-high; 483 - gpio = <&gpio 92 0>; /* gpio PL4 */ 483 + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; 484 484 vin-supply = <&sys_3v3_reg>; 485 485 }; 486 486 ··· 491 491 regulator-min-microvolt = <5000000>; 492 492 regulator-max-microvolt = <5000000>; 493 493 enable-active-high; 494 - gpio = <&gpio 152 0>; /* GPIO PT0 */ 494 + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; 495 495 gpio-open-drain; 496 496 vin-supply = <&vdd_5v0_reg>; 497 497 }; ··· 515 515 nvidia,i2s-controller = <&tegra_i2s1>; 516 516 nvidia,audio-codec = <&wm8903>; 517 517 518 - nvidia,spkr-en-gpios = <&wm8903 2 0>; 519 - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 518 + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 519 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 520 + GPIO_ACTIVE_HIGH>; 520 521 521 - clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>; 522 + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 523 + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 524 + <&tegra_car TEGRA30_CLK_EXTERN1>; 522 525 clock-names = "pll_a", "pll_a_out0", "mclk"; 523 526 }; 524 527 };
+154 -134
arch/arm/boot/dts/tegra30.dtsi
··· 1 - /include/ "skeleton.dtsi" 1 + #include <dt-bindings/clock/tegra30-car.h> 2 + #include <dt-bindings/gpio/tegra-gpio.h> 3 + #include <dt-bindings/interrupt-controller/arm-gic.h> 4 + 5 + #include "skeleton.dtsi" 2 6 3 7 / { 4 8 compatible = "nvidia,tegra30"; ··· 19 15 host1x { 20 16 compatible = "nvidia,tegra30-host1x", "simple-bus"; 21 17 reg = <0x50000000 0x00024000>; 22 - interrupts = <0 65 0x04 /* mpcore syncpt */ 23 - 0 67 0x04>; /* mpcore general */ 24 - clocks = <&tegra_car 28>; 18 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 19 + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 20 + clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 25 21 26 22 #address-cells = <1>; 27 23 #size-cells = <1>; ··· 31 27 mpe { 32 28 compatible = "nvidia,tegra30-mpe"; 33 29 reg = <0x54040000 0x00040000>; 34 - interrupts = <0 68 0x04>; 35 - clocks = <&tegra_car 60>; 30 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 31 + clocks = <&tegra_car TEGRA30_CLK_MPE>; 36 32 }; 37 33 38 34 vi { 39 35 compatible = "nvidia,tegra30-vi"; 40 36 reg = <0x54080000 0x00040000>; 41 - interrupts = <0 69 0x04>; 42 - clocks = <&tegra_car 164>; 37 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 38 + clocks = <&tegra_car TEGRA30_CLK_VI>; 43 39 }; 44 40 45 41 epp { 46 42 compatible = "nvidia,tegra30-epp"; 47 43 reg = <0x540c0000 0x00040000>; 48 - interrupts = <0 70 0x04>; 49 - clocks = <&tegra_car 19>; 44 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 45 + clocks = <&tegra_car TEGRA30_CLK_EPP>; 50 46 }; 51 47 52 48 isp { 53 49 compatible = "nvidia,tegra30-isp"; 54 50 reg = <0x54100000 0x00040000>; 55 - interrupts = <0 71 0x04>; 56 - clocks = <&tegra_car 23>; 51 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 52 + clocks = <&tegra_car TEGRA30_CLK_ISP>; 57 53 }; 58 54 59 55 gr2d { 60 56 compatible = "nvidia,tegra30-gr2d"; 61 57 reg = <0x54140000 0x00040000>; 62 - interrupts = <0 72 0x04>; 63 - clocks = <&tegra_car 21>; 58 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 59 + clocks = <&tegra_car TEGRA30_CLK_GR2D>; 64 60 }; 65 61 66 62 gr3d { ··· 73 69 dc@54200000 { 74 70 compatible = "nvidia,tegra30-dc"; 75 71 reg = <0x54200000 0x00040000>; 76 - interrupts = <0 73 0x04>; 77 - clocks = <&tegra_car 27>, <&tegra_car 179>; 72 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 73 + clocks = <&tegra_car TEGRA30_CLK_DISP1>, 74 + <&tegra_car TEGRA30_CLK_PLL_P>; 78 75 clock-names = "disp1", "parent"; 79 76 80 77 rgb { ··· 86 81 dc@54240000 { 87 82 compatible = "nvidia,tegra30-dc"; 88 83 reg = <0x54240000 0x00040000>; 89 - interrupts = <0 74 0x04>; 90 - clocks = <&tegra_car 26>, <&tegra_car 179>; 84 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 85 + clocks = <&tegra_car TEGRA30_CLK_DISP2>, 86 + <&tegra_car TEGRA30_CLK_PLL_P>; 91 87 clock-names = "disp2", "parent"; 92 88 93 89 rgb { ··· 99 93 hdmi { 100 94 compatible = "nvidia,tegra30-hdmi"; 101 95 reg = <0x54280000 0x00040000>; 102 - interrupts = <0 75 0x04>; 103 - clocks = <&tegra_car 51>, <&tegra_car 189>; 96 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 97 + clocks = <&tegra_car TEGRA30_CLK_HDMI>, 98 + <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 104 99 clock-names = "hdmi", "parent"; 105 100 status = "disabled"; 106 101 }; ··· 109 102 tvo { 110 103 compatible = "nvidia,tegra30-tvo"; 111 104 reg = <0x542c0000 0x00040000>; 112 - interrupts = <0 76 0x04>; 113 - clocks = <&tegra_car 169>; 105 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 106 + clocks = <&tegra_car TEGRA30_CLK_TVO>; 114 107 status = "disabled"; 115 108 }; 116 109 117 110 dsi { 118 111 compatible = "nvidia,tegra30-dsi"; 119 112 reg = <0x54300000 0x00040000>; 120 - clocks = <&tegra_car 48>; 113 + clocks = <&tegra_car TEGRA30_CLK_DSIA>; 121 114 status = "disabled"; 122 115 }; 123 116 }; ··· 125 118 timer@50004600 { 126 119 compatible = "arm,cortex-a9-twd-timer"; 127 120 reg = <0x50040600 0x20>; 128 - interrupts = <1 13 0xf04>; 129 - clocks = <&tegra_car 214>; 121 + interrupts = <GIC_PPI 13 122 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 123 + clocks = <&tegra_car TEGRA30_CLK_TWD>; 130 124 }; 131 125 132 126 intc: interrupt-controller { ··· 150 142 timer@60005000 { 151 143 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 152 144 reg = <0x60005000 0x400>; 153 - interrupts = <0 0 0x04 154 - 0 1 0x04 155 - 0 41 0x04 156 - 0 42 0x04 157 - 0 121 0x04 158 - 0 122 0x04>; 159 - clocks = <&tegra_car 5>; 145 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 146 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 147 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 148 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 149 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 150 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 151 + clocks = <&tegra_car TEGRA30_CLK_TIMER>; 160 152 }; 161 153 162 154 tegra_car: clock { ··· 168 160 apbdma: dma { 169 161 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 170 162 reg = <0x6000a000 0x1400>; 171 - interrupts = <0 104 0x04 172 - 0 105 0x04 173 - 0 106 0x04 174 - 0 107 0x04 175 - 0 108 0x04 176 - 0 109 0x04 177 - 0 110 0x04 178 - 0 111 0x04 179 - 0 112 0x04 180 - 0 113 0x04 181 - 0 114 0x04 182 - 0 115 0x04 183 - 0 116 0x04 184 - 0 117 0x04 185 - 0 118 0x04 186 - 0 119 0x04 187 - 0 128 0x04 188 - 0 129 0x04 189 - 0 130 0x04 190 - 0 131 0x04 191 - 0 132 0x04 192 - 0 133 0x04 193 - 0 134 0x04 194 - 0 135 0x04 195 - 0 136 0x04 196 - 0 137 0x04 197 - 0 138 0x04 198 - 0 139 0x04 199 - 0 140 0x04 200 - 0 141 0x04 201 - 0 142 0x04 202 - 0 143 0x04>; 203 - clocks = <&tegra_car 34>; 163 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 164 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 165 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 166 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 168 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 169 + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 170 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 171 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 172 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 173 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 174 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 175 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 176 + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 177 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 178 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 179 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 180 + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 181 + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 182 + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 183 + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 184 + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 185 + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 186 + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 187 + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 188 + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 189 + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 190 + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 191 + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 192 + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 193 + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 194 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 195 + clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 204 196 }; 205 197 206 198 ahb: ahb { ··· 211 203 gpio: gpio { 212 204 compatible = "nvidia,tegra30-gpio"; 213 205 reg = <0x6000d000 0x1000>; 214 - interrupts = <0 32 0x04 215 - 0 33 0x04 216 - 0 34 0x04 217 - 0 35 0x04 218 - 0 55 0x04 219 - 0 87 0x04 220 - 0 89 0x04 221 - 0 125 0x04>; 206 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 207 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 208 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 209 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 210 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 211 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 212 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 213 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 222 214 #gpio-cells = <2>; 223 215 gpio-controller; 224 216 #interrupt-cells = <2>; ··· 243 235 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 244 236 reg = <0x70006000 0x40>; 245 237 reg-shift = <2>; 246 - interrupts = <0 36 0x04>; 238 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 247 239 nvidia,dma-request-selector = <&apbdma 8>; 248 - clocks = <&tegra_car 6>; 240 + clocks = <&tegra_car TEGRA30_CLK_UARTA>; 249 241 status = "disabled"; 250 242 }; 251 243 ··· 253 245 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 254 246 reg = <0x70006040 0x40>; 255 247 reg-shift = <2>; 256 - interrupts = <0 37 0x04>; 248 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 257 249 nvidia,dma-request-selector = <&apbdma 9>; 258 - clocks = <&tegra_car 160>; 250 + clocks = <&tegra_car TEGRA30_CLK_UARTB>; 259 251 status = "disabled"; 260 252 }; 261 253 ··· 263 255 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 264 256 reg = <0x70006200 0x100>; 265 257 reg-shift = <2>; 266 - interrupts = <0 46 0x04>; 258 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 267 259 nvidia,dma-request-selector = <&apbdma 10>; 268 - clocks = <&tegra_car 55>; 260 + clocks = <&tegra_car TEGRA30_CLK_UARTC>; 269 261 status = "disabled"; 270 262 }; 271 263 ··· 273 265 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 274 266 reg = <0x70006300 0x100>; 275 267 reg-shift = <2>; 276 - interrupts = <0 90 0x04>; 268 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 277 269 nvidia,dma-request-selector = <&apbdma 19>; 278 - clocks = <&tegra_car 65>; 270 + clocks = <&tegra_car TEGRA30_CLK_UARTD>; 279 271 status = "disabled"; 280 272 }; 281 273 ··· 283 275 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 284 276 reg = <0x70006400 0x100>; 285 277 reg-shift = <2>; 286 - interrupts = <0 91 0x04>; 278 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 287 279 nvidia,dma-request-selector = <&apbdma 20>; 288 - clocks = <&tegra_car 66>; 280 + clocks = <&tegra_car TEGRA30_CLK_UARTE>; 289 281 status = "disabled"; 290 282 }; 291 283 ··· 293 285 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 294 286 reg = <0x7000a000 0x100>; 295 287 #pwm-cells = <2>; 296 - clocks = <&tegra_car 17>; 288 + clocks = <&tegra_car TEGRA30_CLK_PWM>; 297 289 status = "disabled"; 298 290 }; 299 291 300 292 rtc { 301 293 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 302 294 reg = <0x7000e000 0x100>; 303 - interrupts = <0 2 0x04>; 304 - clocks = <&tegra_car 4>; 295 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 296 + clocks = <&tegra_car TEGRA30_CLK_RTC>; 305 297 }; 306 298 307 299 i2c@7000c000 { 308 300 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 309 301 reg = <0x7000c000 0x100>; 310 - interrupts = <0 38 0x04>; 302 + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 311 303 #address-cells = <1>; 312 304 #size-cells = <0>; 313 - clocks = <&tegra_car 12>, <&tegra_car 182>; 305 + clocks = <&tegra_car TEGRA30_CLK_I2C1>, 306 + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 314 307 clock-names = "div-clk", "fast-clk"; 315 308 status = "disabled"; 316 309 }; ··· 319 310 i2c@7000c400 { 320 311 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 321 312 reg = <0x7000c400 0x100>; 322 - interrupts = <0 84 0x04>; 313 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 323 314 #address-cells = <1>; 324 315 #size-cells = <0>; 325 - clocks = <&tegra_car 54>, <&tegra_car 182>; 316 + clocks = <&tegra_car TEGRA30_CLK_I2C2>, 317 + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 326 318 clock-names = "div-clk", "fast-clk"; 327 319 status = "disabled"; 328 320 }; ··· 331 321 i2c@7000c500 { 332 322 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 333 323 reg = <0x7000c500 0x100>; 334 - interrupts = <0 92 0x04>; 324 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 335 325 #address-cells = <1>; 336 326 #size-cells = <0>; 337 - clocks = <&tegra_car 67>, <&tegra_car 182>; 327 + clocks = <&tegra_car TEGRA30_CLK_I2C3>, 328 + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 338 329 clock-names = "div-clk", "fast-clk"; 339 330 status = "disabled"; 340 331 }; ··· 343 332 i2c@7000c700 { 344 333 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 345 334 reg = <0x7000c700 0x100>; 346 - interrupts = <0 120 0x04>; 335 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 347 336 #address-cells = <1>; 348 337 #size-cells = <0>; 349 - clocks = <&tegra_car 103>, <&tegra_car 182>; 338 + clocks = <&tegra_car TEGRA30_CLK_I2C4>, 339 + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 350 340 clock-names = "div-clk", "fast-clk"; 351 341 status = "disabled"; 352 342 }; ··· 355 343 i2c@7000d000 { 356 344 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 357 345 reg = <0x7000d000 0x100>; 358 - interrupts = <0 53 0x04>; 346 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 359 347 #address-cells = <1>; 360 348 #size-cells = <0>; 361 - clocks = <&tegra_car 47>, <&tegra_car 182>; 349 + clocks = <&tegra_car TEGRA30_CLK_I2C5>, 350 + <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 362 351 clock-names = "div-clk", "fast-clk"; 363 352 status = "disabled"; 364 353 }; ··· 367 354 spi@7000d400 { 368 355 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 369 356 reg = <0x7000d400 0x200>; 370 - interrupts = <0 59 0x04>; 357 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 371 358 nvidia,dma-request-selector = <&apbdma 15>; 372 359 #address-cells = <1>; 373 360 #size-cells = <0>; 374 - clocks = <&tegra_car 41>; 361 + clocks = <&tegra_car TEGRA30_CLK_SBC1>; 375 362 status = "disabled"; 376 363 }; 377 364 378 365 spi@7000d600 { 379 366 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 380 367 reg = <0x7000d600 0x200>; 381 - interrupts = <0 82 0x04>; 368 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 382 369 nvidia,dma-request-selector = <&apbdma 16>; 383 370 #address-cells = <1>; 384 371 #size-cells = <0>; 385 - clocks = <&tegra_car 44>; 372 + clocks = <&tegra_car TEGRA30_CLK_SBC2>; 386 373 status = "disabled"; 387 374 }; 388 375 389 376 spi@7000d800 { 390 377 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 391 378 reg = <0x7000d800 0x200>; 392 - interrupts = <0 83 0x04>; 379 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 393 380 nvidia,dma-request-selector = <&apbdma 17>; 394 381 #address-cells = <1>; 395 382 #size-cells = <0>; 396 - clocks = <&tegra_car 46>; 383 + clocks = <&tegra_car TEGRA30_CLK_SBC3>; 397 384 status = "disabled"; 398 385 }; 399 386 400 387 spi@7000da00 { 401 388 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 402 389 reg = <0x7000da00 0x200>; 403 - interrupts = <0 93 0x04>; 390 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 404 391 nvidia,dma-request-selector = <&apbdma 18>; 405 392 #address-cells = <1>; 406 393 #size-cells = <0>; 407 - clocks = <&tegra_car 68>; 394 + clocks = <&tegra_car TEGRA30_CLK_SBC4>; 408 395 status = "disabled"; 409 396 }; 410 397 411 398 spi@7000dc00 { 412 399 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 413 400 reg = <0x7000dc00 0x200>; 414 - interrupts = <0 94 0x04>; 401 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 415 402 nvidia,dma-request-selector = <&apbdma 27>; 416 403 #address-cells = <1>; 417 404 #size-cells = <0>; 418 - clocks = <&tegra_car 104>; 405 + clocks = <&tegra_car TEGRA30_CLK_SBC5>; 419 406 status = "disabled"; 420 407 }; 421 408 422 409 spi@7000de00 { 423 410 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 424 411 reg = <0x7000de00 0x200>; 425 - interrupts = <0 79 0x04>; 412 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 426 413 nvidia,dma-request-selector = <&apbdma 28>; 427 414 #address-cells = <1>; 428 415 #size-cells = <0>; 429 - clocks = <&tegra_car 105>; 416 + clocks = <&tegra_car TEGRA30_CLK_SBC6>; 430 417 status = "disabled"; 431 418 }; 432 419 433 420 kbc { 434 421 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 435 422 reg = <0x7000e200 0x100>; 436 - interrupts = <0 85 0x04>; 437 - clocks = <&tegra_car 36>; 423 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 424 + clocks = <&tegra_car TEGRA30_CLK_KBC>; 438 425 status = "disabled"; 439 426 }; 440 427 441 428 pmc { 442 429 compatible = "nvidia,tegra30-pmc"; 443 430 reg = <0x7000e400 0x400>; 444 - clocks = <&tegra_car 218>, <&clk32k_in>; 431 + clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 445 432 clock-names = "pclk", "clk32k_in"; 446 433 }; 447 434 ··· 451 438 0x7000f03c 0x1b4 452 439 0x7000f200 0x028 453 440 0x7000f284 0x17c>; 454 - interrupts = <0 77 0x04>; 441 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 455 442 }; 456 443 457 444 iommu { ··· 468 455 compatible = "nvidia,tegra30-ahub"; 469 456 reg = <0x70080000 0x200 470 457 0x70080200 0x100>; 471 - interrupts = <0 103 0x04>; 458 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 472 459 nvidia,dma-request-selector = <&apbdma 1>; 473 - clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, 474 - <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, 475 - <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, 476 - <&tegra_car 110>, <&tegra_car 162>; 460 + clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 461 + <&tegra_car TEGRA30_CLK_APBIF>, 462 + <&tegra_car TEGRA30_CLK_I2S0>, 463 + <&tegra_car TEGRA30_CLK_I2S1>, 464 + <&tegra_car TEGRA30_CLK_I2S2>, 465 + <&tegra_car TEGRA30_CLK_I2S3>, 466 + <&tegra_car TEGRA30_CLK_I2S4>, 467 + <&tegra_car TEGRA30_CLK_DAM0>, 468 + <&tegra_car TEGRA30_CLK_DAM1>, 469 + <&tegra_car TEGRA30_CLK_DAM2>, 470 + <&tegra_car TEGRA30_CLK_SPDIF_IN>; 477 471 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 478 472 "i2s3", "i2s4", "dam0", "dam1", "dam2", 479 473 "spdif_in"; ··· 492 472 compatible = "nvidia,tegra30-i2s"; 493 473 reg = <0x70080300 0x100>; 494 474 nvidia,ahub-cif-ids = <4 4>; 495 - clocks = <&tegra_car 30>; 475 + clocks = <&tegra_car TEGRA30_CLK_I2S0>; 496 476 status = "disabled"; 497 477 }; 498 478 ··· 500 480 compatible = "nvidia,tegra30-i2s"; 501 481 reg = <0x70080400 0x100>; 502 482 nvidia,ahub-cif-ids = <5 5>; 503 - clocks = <&tegra_car 11>; 483 + clocks = <&tegra_car TEGRA30_CLK_I2S1>; 504 484 status = "disabled"; 505 485 }; 506 486 ··· 508 488 compatible = "nvidia,tegra30-i2s"; 509 489 reg = <0x70080500 0x100>; 510 490 nvidia,ahub-cif-ids = <6 6>; 511 - clocks = <&tegra_car 18>; 491 + clocks = <&tegra_car TEGRA30_CLK_I2S2>; 512 492 status = "disabled"; 513 493 }; 514 494 ··· 516 496 compatible = "nvidia,tegra30-i2s"; 517 497 reg = <0x70080600 0x100>; 518 498 nvidia,ahub-cif-ids = <7 7>; 519 - clocks = <&tegra_car 101>; 499 + clocks = <&tegra_car TEGRA30_CLK_I2S3>; 520 500 status = "disabled"; 521 501 }; 522 502 ··· 524 504 compatible = "nvidia,tegra30-i2s"; 525 505 reg = <0x70080700 0x100>; 526 506 nvidia,ahub-cif-ids = <8 8>; 527 - clocks = <&tegra_car 102>; 507 + clocks = <&tegra_car TEGRA30_CLK_I2S4>; 528 508 status = "disabled"; 529 509 }; 530 510 }; ··· 532 512 sdhci@78000000 { 533 513 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 534 514 reg = <0x78000000 0x200>; 535 - interrupts = <0 14 0x04>; 536 - clocks = <&tegra_car 14>; 515 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 516 + clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 537 517 status = "disabled"; 538 518 }; 539 519 540 520 sdhci@78000200 { 541 521 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 542 522 reg = <0x78000200 0x200>; 543 - interrupts = <0 15 0x04>; 544 - clocks = <&tegra_car 9>; 523 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 524 + clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 545 525 status = "disabled"; 546 526 }; 547 527 548 528 sdhci@78000400 { 549 529 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 550 530 reg = <0x78000400 0x200>; 551 - interrupts = <0 19 0x04>; 552 - clocks = <&tegra_car 69>; 531 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 532 + clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 553 533 status = "disabled"; 554 534 }; 555 535 556 536 sdhci@78000600 { 557 537 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 558 538 reg = <0x78000600 0x200>; 559 - interrupts = <0 31 0x04>; 560 - clocks = <&tegra_car 15>; 539 + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 540 + clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 561 541 status = "disabled"; 562 542 }; 563 543 ··· 592 572 593 573 pmu { 594 574 compatible = "arm,cortex-a9-pmu"; 595 - interrupts = <0 144 0x04 596 - 0 145 0x04 597 - 0 146 0x04 598 - 0 147 0x04>; 575 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 576 + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 577 + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 578 + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 599 579 }; 600 580 };
+342
include/dt-bindings/clock/tegra114-car.h
··· 1 + /* 2 + * This header provides constants for binding nvidia,tegra114-car. 3 + * 4 + * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5 + * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6 + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7 + * this case, those clocks are assigned IDs above 160 in order to highlight 8 + * this issue. Implementations that interpret these clock IDs as bit values 9 + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10 + * explicitly handle these special cases. 11 + * 12 + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13 + * above. 14 + */ 15 + 16 + #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 17 + #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 18 + 19 + /* 0 */ 20 + /* 1 */ 21 + /* 2 */ 22 + /* 3 */ 23 + #define TEGRA114_CLK_RTC 4 24 + #define TEGRA114_CLK_TIMER 5 25 + #define TEGRA114_CLK_UARTA 6 26 + /* 7 (register bit affects uartb and vfir) */ 27 + /* 8 */ 28 + #define TEGRA114_CLK_SDMMC2 9 29 + /* 10 (register bit affects spdif_in and spdif_out) */ 30 + #define TEGRA114_CLK_I2S1 11 31 + #define TEGRA114_CLK_I2C1 12 32 + #define TEGRA114_CLK_NDFLASH 13 33 + #define TEGRA114_CLK_SDMMC1 14 34 + #define TEGRA114_CLK_SDMMC4 15 35 + /* 16 */ 36 + #define TEGRA114_CLK_PWM 17 37 + #define TEGRA114_CLK_I2S2 18 38 + #define TEGRA114_CLK_EPP 19 39 + /* 20 (register bit affects vi and vi_sensor) */ 40 + #define TEGRA114_CLK_GR_2D 21 41 + #define TEGRA114_CLK_USBD 22 42 + #define TEGRA114_CLK_ISP 23 43 + #define TEGRA114_CLK_GR_3D 24 44 + /* 25 */ 45 + #define TEGRA114_CLK_DISP2 26 46 + #define TEGRA114_CLK_DISP1 27 47 + #define TEGRA114_CLK_HOST1X 28 48 + #define TEGRA114_CLK_VCP 29 49 + #define TEGRA114_CLK_I2S0 30 50 + /* 31 */ 51 + 52 + /* 32 */ 53 + /* 33 */ 54 + #define TEGRA114_CLK_APBDMA 34 55 + /* 35 */ 56 + #define TEGRA114_CLK_KBC 36 57 + /* 37 */ 58 + /* 38 */ 59 + /* 39 (register bit affects fuse and fuse_burn) */ 60 + #define TEGRA114_CLK_KFUSE 40 61 + #define TEGRA114_CLK_SBC1 41 62 + #define TEGRA114_CLK_NOR 42 63 + /* 43 */ 64 + #define TEGRA114_CLK_SBC2 44 65 + /* 45 */ 66 + #define TEGRA114_CLK_SBC3 46 67 + #define TEGRA114_CLK_I2C5 47 68 + #define TEGRA114_CLK_DSIA 48 69 + /* 49 */ 70 + #define TEGRA114_CLK_MIPI 50 71 + #define TEGRA114_CLK_HDMI 51 72 + #define TEGRA114_CLK_CSI 52 73 + /* 53 */ 74 + #define TEGRA114_CLK_I2C2 54 75 + #define TEGRA114_CLK_UARTC 55 76 + #define TEGRA114_CLK_MIPI_CAL 56 77 + #define TEGRA114_CLK_EMC 57 78 + #define TEGRA114_CLK_USB2 58 79 + #define TEGRA114_CLK_USB3 59 80 + /* 60 */ 81 + #define TEGRA114_CLK_VDE 61 82 + #define TEGRA114_CLK_BSEA 62 83 + #define TEGRA114_CLK_BSEV 63 84 + 85 + /* 64 */ 86 + #define TEGRA114_CLK_UARTD 65 87 + /* 66 */ 88 + #define TEGRA114_CLK_I2C3 67 89 + #define TEGRA114_CLK_SBC4 68 90 + #define TEGRA114_CLK_SDMMC3 69 91 + /* 70 */ 92 + #define TEGRA114_CLK_OWR 71 93 + /* 72 */ 94 + #define TEGRA114_CLK_CSITE 73 95 + /* 74 */ 96 + /* 75 */ 97 + #define TEGRA114_CLK_LA 76 98 + #define TEGRA114_CLK_TRACE 77 99 + #define TEGRA114_CLK_SOC_THERM 78 100 + #define TEGRA114_CLK_DTV 79 101 + #define TEGRA114_CLK_NDSPEED 80 102 + #define TEGRA114_CLK_I2CSLOW 81 103 + #define TEGRA114_CLK_DSIB 82 104 + #define TEGRA114_CLK_TSEC 83 105 + /* 84 */ 106 + /* 85 */ 107 + /* 86 */ 108 + /* 87 */ 109 + /* 88 */ 110 + #define TEGRA114_CLK_XUSB_HOST 89 111 + /* 90 */ 112 + #define TEGRA114_CLK_MSENC 91 113 + #define TEGRA114_CLK_CSUS 92 114 + /* 93 */ 115 + /* 94 */ 116 + /* 95 (bit affects xusb_dev and xusb_dev_src) */ 117 + 118 + /* 96 */ 119 + /* 97 */ 120 + /* 98 */ 121 + #define TEGRA114_CLK_MSELECT 99 122 + #define TEGRA114_CLK_TSENSOR 100 123 + #define TEGRA114_CLK_I2S3 101 124 + #define TEGRA114_CLK_I2S4 102 125 + #define TEGRA114_CLK_I2C4 103 126 + #define TEGRA114_CLK_SBC5 104 127 + #define TEGRA114_CLK_SBC6 105 128 + #define TEGRA114_CLK_D_AUDIO 106 129 + #define TEGRA114_CLK_APBIF 107 130 + #define TEGRA114_CLK_DAM0 108 131 + #define TEGRA114_CLK_DAM1 109 132 + #define TEGRA114_CLK_DAM2 110 133 + #define TEGRA114_CLK_HDA2CODEC_2X 111 134 + /* 112 */ 135 + #define TEGRA114_CLK_AUDIO0_2X 113 136 + #define TEGRA114_CLK_AUDIO1_2X 114 137 + #define TEGRA114_CLK_AUDIO2_2X 115 138 + #define TEGRA114_CLK_AUDIO3_2X 116 139 + #define TEGRA114_CLK_AUDIO4_2X 117 140 + #define TEGRA114_CLK_SPDIF_2X 118 141 + #define TEGRA114_CLK_ACTMON 119 142 + #define TEGRA114_CLK_EXTERN1 120 143 + #define TEGRA114_CLK_EXTERN2 121 144 + #define TEGRA114_CLK_EXTERN3 122 145 + /* 123 */ 146 + /* 124 */ 147 + #define TEGRA114_CLK_HDA 125 148 + /* 126 */ 149 + #define TEGRA114_CLK_SE 127 150 + 151 + #define TEGRA114_CLK_HDA2HDMI 128 152 + /* 129 */ 153 + /* 130 */ 154 + /* 131 */ 155 + /* 132 */ 156 + /* 133 */ 157 + /* 134 */ 158 + /* 135 */ 159 + /* 136 */ 160 + /* 137 */ 161 + /* 138 */ 162 + /* 139 */ 163 + /* 140 */ 164 + /* 141 */ 165 + /* 142 */ 166 + /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 167 + /* xusb_host_src and xusb_ss_src) */ 168 + #define TEGRA114_CLK_CILAB 144 169 + #define TEGRA114_CLK_CILCD 145 170 + #define TEGRA114_CLK_CILE 146 171 + #define TEGRA114_CLK_DSIALP 147 172 + #define TEGRA114_CLK_DSIBLP 148 173 + /* 149 */ 174 + #define TEGRA114_CLK_DDS 150 175 + /* 151 */ 176 + #define TEGRA114_CLK_DP2 152 177 + #define TEGRA114_CLK_AMX 153 178 + #define TEGRA114_CLK_ADX 154 179 + /* 155 (bit affects dfll_ref and dfll_soc) */ 180 + #define TEGRA114_CLK_XUSB_SS 156 181 + /* 157 */ 182 + /* 158 */ 183 + /* 159 */ 184 + 185 + /* 160 */ 186 + /* 161 */ 187 + /* 162 */ 188 + /* 163 */ 189 + /* 164 */ 190 + /* 165 */ 191 + /* 166 */ 192 + /* 167 */ 193 + /* 168 */ 194 + /* 169 */ 195 + /* 170 */ 196 + /* 171 */ 197 + /* 172 */ 198 + /* 173 */ 199 + /* 174 */ 200 + /* 175 */ 201 + /* 176 */ 202 + /* 177 */ 203 + /* 178 */ 204 + /* 179 */ 205 + /* 180 */ 206 + /* 181 */ 207 + /* 182 */ 208 + /* 183 */ 209 + /* 184 */ 210 + /* 185 */ 211 + /* 186 */ 212 + /* 187 */ 213 + /* 188 */ 214 + /* 189 */ 215 + /* 190 */ 216 + /* 191 */ 217 + 218 + #define TEGRA114_CLK_UARTB 192 219 + #define TEGRA114_CLK_VFIR 193 220 + #define TEGRA114_CLK_SPDIF_IN 194 221 + #define TEGRA114_CLK_SPDIF_OUT 195 222 + #define TEGRA114_CLK_VI 196 223 + #define TEGRA114_CLK_VI_SENSOR 197 224 + #define TEGRA114_CLK_FUSE 198 225 + #define TEGRA114_CLK_FUSE_BURN 199 226 + #define TEGRA114_CLK_CLK_32K 200 227 + #define TEGRA114_CLK_CLK_M 201 228 + #define TEGRA114_CLK_CLK_M_DIV2 202 229 + #define TEGRA114_CLK_CLK_M_DIV4 203 230 + #define TEGRA114_CLK_PLL_REF 204 231 + #define TEGRA114_CLK_PLL_C 205 232 + #define TEGRA114_CLK_PLL_C_OUT1 206 233 + #define TEGRA114_CLK_PLL_C2 207 234 + #define TEGRA114_CLK_PLL_C3 208 235 + #define TEGRA114_CLK_PLL_M 209 236 + #define TEGRA114_CLK_PLL_M_OUT1 210 237 + #define TEGRA114_CLK_PLL_P 211 238 + #define TEGRA114_CLK_PLL_P_OUT1 212 239 + #define TEGRA114_CLK_PLL_P_OUT2 213 240 + #define TEGRA114_CLK_PLL_P_OUT3 214 241 + #define TEGRA114_CLK_PLL_P_OUT4 215 242 + #define TEGRA114_CLK_PLL_A 216 243 + #define TEGRA114_CLK_PLL_A_OUT0 217 244 + #define TEGRA114_CLK_PLL_D 218 245 + #define TEGRA114_CLK_PLL_D_OUT0 219 246 + #define TEGRA114_CLK_PLL_D2 220 247 + #define TEGRA114_CLK_PLL_D2_OUT0 221 248 + #define TEGRA114_CLK_PLL_U 222 249 + #define TEGRA114_CLK_PLL_U_480M 223 250 + 251 + #define TEGRA114_CLK_PLL_U_60M 224 252 + #define TEGRA114_CLK_PLL_U_48M 225 253 + #define TEGRA114_CLK_PLL_U_12M 226 254 + #define TEGRA114_CLK_PLL_X 227 255 + #define TEGRA114_CLK_PLL_X_OUT0 228 256 + #define TEGRA114_CLK_PLL_RE_VCO 229 257 + #define TEGRA114_CLK_PLL_RE_OUT 230 258 + #define TEGRA114_CLK_PLL_E_OUT0 231 259 + #define TEGRA114_CLK_SPDIF_IN_SYNC 232 260 + #define TEGRA114_CLK_I2S0_SYNC 233 261 + #define TEGRA114_CLK_I2S1_SYNC 234 262 + #define TEGRA114_CLK_I2S2_SYNC 235 263 + #define TEGRA114_CLK_I2S3_SYNC 236 264 + #define TEGRA114_CLK_I2S4_SYNC 237 265 + #define TEGRA114_CLK_VIMCLK_SYNC 238 266 + #define TEGRA114_CLK_AUDIO0 239 267 + #define TEGRA114_CLK_AUDIO1 240 268 + #define TEGRA114_CLK_AUDIO2 241 269 + #define TEGRA114_CLK_AUDIO3 242 270 + #define TEGRA114_CLK_AUDIO4 243 271 + #define TEGRA114_CLK_SPDIF 244 272 + #define TEGRA114_CLK_CLK_OUT_1 245 273 + #define TEGRA114_CLK_CLK_OUT_2 246 274 + #define TEGRA114_CLK_CLK_OUT_3 247 275 + #define TEGRA114_CLK_BLINK 248 276 + /* 249 */ 277 + /* 250 */ 278 + /* 251 */ 279 + #define TEGRA114_CLK_XUSB_HOST_SRC 252 280 + #define TEGRA114_CLK_XUSB_FALCON_SRC 253 281 + #define TEGRA114_CLK_XUSB_FS_SRC 254 282 + #define TEGRA114_CLK_XUSB_SS_SRC 255 283 + 284 + #define TEGRA114_CLK_XUSB_DEV_SRC 256 285 + #define TEGRA114_CLK_XUSB_DEV 257 286 + #define TEGRA114_CLK_XUSB_HS_SRC 258 287 + #define TEGRA114_CLK_SCLK 259 288 + #define TEGRA114_CLK_HCLK 260 289 + #define TEGRA114_CLK_PCLK 261 290 + #define TEGRA114_CLK_CCLK_G 262 291 + #define TEGRA114_CLK_CCLK_LP 263 292 + /* 264 */ 293 + /* 265 */ 294 + /* 266 */ 295 + /* 267 */ 296 + /* 268 */ 297 + /* 269 */ 298 + /* 270 */ 299 + /* 271 */ 300 + /* 272 */ 301 + /* 273 */ 302 + /* 274 */ 303 + /* 275 */ 304 + /* 276 */ 305 + /* 277 */ 306 + /* 278 */ 307 + /* 279 */ 308 + /* 280 */ 309 + /* 281 */ 310 + /* 282 */ 311 + /* 283 */ 312 + /* 284 */ 313 + /* 285 */ 314 + /* 286 */ 315 + /* 287 */ 316 + 317 + /* 288 */ 318 + /* 289 */ 319 + /* 290 */ 320 + /* 291 */ 321 + /* 292 */ 322 + /* 293 */ 323 + /* 294 */ 324 + /* 295 */ 325 + /* 296 */ 326 + /* 297 */ 327 + /* 298 */ 328 + /* 299 */ 329 + #define TEGRA114_CLK_AUDIO0_MUX 300 330 + #define TEGRA114_CLK_AUDIO1_MUX 301 331 + #define TEGRA114_CLK_AUDIO2_MUX 302 332 + #define TEGRA114_CLK_AUDIO3_MUX 303 333 + #define TEGRA114_CLK_AUDIO4_MUX 304 334 + #define TEGRA114_CLK_SPDIF_MUX 305 335 + #define TEGRA114_CLK_CLK_OUT_1_MUX 306 336 + #define TEGRA114_CLK_CLK_OUT_2_MUX 307 337 + #define TEGRA114_CLK_CLK_OUT_3_MUX 308 338 + #define TEGRA114_CLK_DSIA_MUX 309 339 + #define TEGRA114_CLK_DSIB_MUX 310 340 + #define TEGRA114_CLK_CLK_MAX 311 341 + 342 + #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
+158
include/dt-bindings/clock/tegra20-car.h
··· 1 + /* 2 + * This header provides constants for binding nvidia,tegra20-car. 3 + * 4 + * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5 + * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6 + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7 + * this case, those clocks are assigned IDs above 95 in order to highlight 8 + * this issue. Implementations that interpret these clock IDs as bit values 9 + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10 + * explicitly handle these special cases. 11 + * 12 + * The balance of the clocks controlled by the CAR are assigned IDs of 96 and 13 + * above. 14 + */ 15 + 16 + #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H 17 + #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H 18 + 19 + #define TEGRA20_CLK_CPU 0 20 + /* 1 */ 21 + /* 2 */ 22 + #define TEGRA20_CLK_AC97 3 23 + #define TEGRA20_CLK_RTC 4 24 + #define TEGRA20_CLK_TIMER 5 25 + #define TEGRA20_CLK_UARTA 6 26 + /* 7 (register bit affects uart2 and vfir) */ 27 + #define TEGRA20_CLK_GPIO 8 28 + #define TEGRA20_CLK_SDMMC2 9 29 + /* 10 (register bit affects spdif_in and spdif_out) */ 30 + #define TEGRA20_CLK_I2S1 11 31 + #define TEGRA20_CLK_I2C1 12 32 + #define TEGRA20_CLK_NDFLASH 13 33 + #define TEGRA20_CLK_SDMMC1 14 34 + #define TEGRA20_CLK_SDMMC4 15 35 + #define TEGRA20_CLK_TWC 16 36 + #define TEGRA20_CLK_PWM 17 37 + #define TEGRA20_CLK_I2S2 18 38 + #define TEGRA20_CLK_EPP 19 39 + /* 20 (register bit affects vi and vi_sensor) */ 40 + #define TEGRA20_CLK_GR2D 21 41 + #define TEGRA20_CLK_USBD 22 42 + #define TEGRA20_CLK_ISP 23 43 + #define TEGRA20_CLK_GR3D 24 44 + #define TEGRA20_CLK_IDE 25 45 + #define TEGRA20_CLK_DISP2 26 46 + #define TEGRA20_CLK_DISP1 27 47 + #define TEGRA20_CLK_HOST1X 28 48 + #define TEGRA20_CLK_VCP 29 49 + /* 30 */ 50 + #define TEGRA20_CLK_CACHE2 31 51 + 52 + #define TEGRA20_CLK_MEM 32 53 + #define TEGRA20_CLK_AHBDMA 33 54 + #define TEGRA20_CLK_APBDMA 34 55 + /* 35 */ 56 + #define TEGRA20_CLK_KBC 36 57 + #define TEGRA20_CLK_STAT_MON 37 58 + #define TEGRA20_CLK_PMC 38 59 + #define TEGRA20_CLK_FUSE 39 60 + #define TEGRA20_CLK_KFUSE 40 61 + #define TEGRA20_CLK_SBC1 41 62 + #define TEGRA20_CLK_NOR 42 63 + #define TEGRA20_CLK_SPI 43 64 + #define TEGRA20_CLK_SBC2 44 65 + #define TEGRA20_CLK_XIO 45 66 + #define TEGRA20_CLK_SBC3 46 67 + #define TEGRA20_CLK_DVC 47 68 + #define TEGRA20_CLK_DSI 48 69 + /* 49 (register bit affects tvo and cve) */ 70 + #define TEGRA20_CLK_MIPI 50 71 + #define TEGRA20_CLK_HDMI 51 72 + #define TEGRA20_CLK_CSI 52 73 + #define TEGRA20_CLK_TVDAC 53 74 + #define TEGRA20_CLK_I2C2 54 75 + #define TEGRA20_CLK_UARTC 55 76 + /* 56 */ 77 + #define TEGRA20_CLK_EMC 57 78 + #define TEGRA20_CLK_USB2 58 79 + #define TEGRA20_CLK_USB3 59 80 + #define TEGRA20_CLK_MPE 60 81 + #define TEGRA20_CLK_VDE 61 82 + #define TEGRA20_CLK_BSEA 62 83 + #define TEGRA20_CLK_BSEV 63 84 + 85 + #define TEGRA20_CLK_SPEEDO 64 86 + #define TEGRA20_CLK_UARTD 65 87 + #define TEGRA20_CLK_UARTE 66 88 + #define TEGRA20_CLK_I2C3 67 89 + #define TEGRA20_CLK_SBC4 68 90 + #define TEGRA20_CLK_SDMMC3 69 91 + #define TEGRA20_CLK_PEX 70 92 + #define TEGRA20_CLK_OWR 71 93 + #define TEGRA20_CLK_AFI 72 94 + #define TEGRA20_CLK_CSITE 73 95 + #define TEGRA20_CLK_PCIE_XCLK 74 96 + #define TEGRA20_CLK_AVPUCQ 75 97 + #define TEGRA20_CLK_LA 76 98 + /* 77 */ 99 + /* 78 */ 100 + /* 79 */ 101 + /* 80 */ 102 + /* 81 */ 103 + /* 82 */ 104 + /* 83 */ 105 + #define TEGRA20_CLK_IRAMA 84 106 + #define TEGRA20_CLK_IRAMB 85 107 + #define TEGRA20_CLK_IRAMC 86 108 + #define TEGRA20_CLK_IRAMD 87 109 + #define TEGRA20_CLK_CRAM2 88 110 + #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ 111 + #define TEGRA20_CLK_CLK_D 90 112 + /* 91 */ 113 + #define TEGRA20_CLK_CSUS 92 114 + #define TEGRA20_CLK_CDEV2 93 115 + #define TEGRA20_CLK_CDEV1 94 116 + /* 95 */ 117 + 118 + #define TEGRA20_CLK_UARTB 96 119 + #define TEGRA20_CLK_VFIR 97 120 + #define TEGRA20_CLK_SPDIF_IN 98 121 + #define TEGRA20_CLK_SPDIF_OUT 99 122 + #define TEGRA20_CLK_VI 100 123 + #define TEGRA20_CLK_VI_SENSOR 101 124 + #define TEGRA20_CLK_TVO 102 125 + #define TEGRA20_CLK_CVE 103 126 + #define TEGRA20_CLK_OSC 104 127 + #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ 128 + #define TEGRA20_CLK_CLK_M 106 129 + #define TEGRA20_CLK_SCLK 107 130 + #define TEGRA20_CLK_CCLK 108 131 + #define TEGRA20_CLK_HCLK 109 132 + #define TEGRA20_CLK_PCLK 110 133 + #define TEGRA20_CLK_BLINK 111 134 + #define TEGRA20_CLK_PLL_A 112 135 + #define TEGRA20_CLK_PLL_A_OUT0 113 136 + #define TEGRA20_CLK_PLL_C 114 137 + #define TEGRA20_CLK_PLL_C_OUT1 115 138 + #define TEGRA20_CLK_PLL_D 116 139 + #define TEGRA20_CLK_PLL_D_OUT0 117 140 + #define TEGRA20_CLK_PLL_E 118 141 + #define TEGRA20_CLK_PLL_M 119 142 + #define TEGRA20_CLK_PLL_M_OUT1 120 143 + #define TEGRA20_CLK_PLL_P 121 144 + #define TEGRA20_CLK_PLL_P_OUT1 122 145 + #define TEGRA20_CLK_PLL_P_OUT2 123 146 + #define TEGRA20_CLK_PLL_P_OUT3 124 147 + #define TEGRA20_CLK_PLL_P_OUT4 125 148 + #define TEGRA20_CLK_PLL_S 126 149 + #define TEGRA20_CLK_PLL_U 127 150 + 151 + #define TEGRA20_CLK_PLL_X 128 152 + #define TEGRA20_CLK_COP 129 /* a/k/a avp */ 153 + #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ 154 + #define TEGRA20_CLK_PLL_REF 131 155 + #define TEGRA20_CLK_TWD 132 156 + #define TEGRA20_CLK_CLK_MAX 133 157 + 158 + #endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
+265
include/dt-bindings/clock/tegra30-car.h
··· 1 + /* 2 + * This header provides constants for binding nvidia,tegra30-car. 3 + * 4 + * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 5 + * registers. These IDs often match those in the CAR's RST_DEVICES registers, 6 + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 7 + * this case, those clocks are assigned IDs above 160 in order to highlight 8 + * this issue. Implementations that interpret these clock IDs as bit values 9 + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 10 + * explicitly handle these special cases. 11 + * 12 + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 13 + * above. 14 + */ 15 + 16 + #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 17 + #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 18 + 19 + #define TEGRA30_CLK_CPU 0 20 + /* 1 */ 21 + /* 2 */ 22 + /* 3 */ 23 + #define TEGRA30_CLK_RTC 4 24 + #define TEGRA30_CLK_TIMER 5 25 + #define TEGRA30_CLK_UARTA 6 26 + /* 7 (register bit affects uartb and vfir) */ 27 + #define TEGRA30_CLK_GPIO 8 28 + #define TEGRA30_CLK_SDMMC2 9 29 + /* 10 (register bit affects spdif_in and spdif_out) */ 30 + #define TEGRA30_CLK_I2S1 11 31 + #define TEGRA30_CLK_I2C1 12 32 + #define TEGRA30_CLK_NDFLASH 13 33 + #define TEGRA30_CLK_SDMMC1 14 34 + #define TEGRA30_CLK_SDMMC4 15 35 + /* 16 */ 36 + #define TEGRA30_CLK_PWM 17 37 + #define TEGRA30_CLK_I2S2 18 38 + #define TEGRA30_CLK_EPP 19 39 + /* 20 (register bit affects vi and vi_sensor) */ 40 + #define TEGRA30_CLK_GR2D 21 41 + #define TEGRA30_CLK_USBD 22 42 + #define TEGRA30_CLK_ISP 23 43 + #define TEGRA30_CLK_GR3D 24 44 + /* 25 */ 45 + #define TEGRA30_CLK_DISP2 26 46 + #define TEGRA30_CLK_DISP1 27 47 + #define TEGRA30_CLK_HOST1X 28 48 + #define TEGRA30_CLK_VCP 29 49 + #define TEGRA30_CLK_I2S0 30 50 + #define TEGRA30_CLK_COP_CACHE 31 51 + 52 + #define TEGRA30_CLK_MC 32 53 + #define TEGRA30_CLK_AHBDMA 33 54 + #define TEGRA30_CLK_APBDMA 34 55 + /* 35 */ 56 + #define TEGRA30_CLK_KBC 36 57 + #define TEGRA30_CLK_STATMON 37 58 + #define TEGRA30_CLK_PMC 38 59 + /* 39 (register bit affects fuse and fuse_burn) */ 60 + #define TEGRA30_CLK_KFUSE 40 61 + #define TEGRA30_CLK_SBC1 41 62 + #define TEGRA30_CLK_NOR 42 63 + /* 43 */ 64 + #define TEGRA30_CLK_SBC2 44 65 + /* 45 */ 66 + #define TEGRA30_CLK_SBC3 46 67 + #define TEGRA30_CLK_I2C5 47 68 + #define TEGRA30_CLK_DSIA 48 69 + /* 49 (register bit affects cve and tvo) */ 70 + #define TEGRA30_CLK_MIPI 50 71 + #define TEGRA30_CLK_HDMI 51 72 + #define TEGRA30_CLK_CSI 52 73 + #define TEGRA30_CLK_TVDAC 53 74 + #define TEGRA30_CLK_I2C2 54 75 + #define TEGRA30_CLK_UARTC 55 76 + /* 56 */ 77 + #define TEGRA30_CLK_EMC 57 78 + #define TEGRA30_CLK_USB2 58 79 + #define TEGRA30_CLK_USB3 59 80 + #define TEGRA30_CLK_MPE 60 81 + #define TEGRA30_CLK_VDE 61 82 + #define TEGRA30_CLK_BSEA 62 83 + #define TEGRA30_CLK_BSEV 63 84 + 85 + #define TEGRA30_CLK_SPEEDO 64 86 + #define TEGRA30_CLK_UARTD 65 87 + #define TEGRA30_CLK_UARTE 66 88 + #define TEGRA30_CLK_I2C3 67 89 + #define TEGRA30_CLK_SBC4 68 90 + #define TEGRA30_CLK_SDMMC3 69 91 + #define TEGRA30_CLK_PCIE 70 92 + #define TEGRA30_CLK_OWR 71 93 + #define TEGRA30_CLK_AFI 72 94 + #define TEGRA30_CLK_CSITE 73 95 + #define TEGRA30_CLK_PCIEX 74 96 + #define TEGRA30_CLK_AVPUCQ 75 97 + #define TEGRA30_CLK_LA 76 98 + /* 77 */ 99 + /* 78 */ 100 + #define TEGRA30_CLK_DTV 79 101 + #define TEGRA30_CLK_NDSPEED 80 102 + #define TEGRA30_CLK_I2CSLOW 81 103 + #define TEGRA30_CLK_DSIB 82 104 + /* 83 */ 105 + #define TEGRA30_CLK_IRAMA 84 106 + #define TEGRA30_CLK_IRAMB 85 107 + #define TEGRA30_CLK_IRAMC 86 108 + #define TEGRA30_CLK_IRAMD 87 109 + #define TEGRA30_CLK_CRAM2 88 110 + /* 89 */ 111 + #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 112 + /* 91 */ 113 + #define TEGRA30_CLK_CSUS 92 114 + #define TEGRA30_CLK_CDEV2 93 115 + #define TEGRA30_CLK_CDEV1 94 116 + /* 95 */ 117 + 118 + #define TEGRA30_CLK_CPU_G 96 119 + #define TEGRA30_CLK_CPU_LP 97 120 + #define TEGRA30_CLK_GR3D2 98 121 + #define TEGRA30_CLK_MSELECT 99 122 + #define TEGRA30_CLK_TSENSOR 100 123 + #define TEGRA30_CLK_I2S3 101 124 + #define TEGRA30_CLK_I2S4 102 125 + #define TEGRA30_CLK_I2C4 103 126 + #define TEGRA30_CLK_SBC5 104 127 + #define TEGRA30_CLK_SBC6 105 128 + #define TEGRA30_CLK_D_AUDIO 106 129 + #define TEGRA30_CLK_APBIF 107 130 + #define TEGRA30_CLK_DAM0 108 131 + #define TEGRA30_CLK_DAM1 109 132 + #define TEGRA30_CLK_DAM2 110 133 + #define TEGRA30_CLK_HDA2CODEC_2X 111 134 + #define TEGRA30_CLK_ATOMICS 112 135 + #define TEGRA30_CLK_AUDIO0_2X 113 136 + #define TEGRA30_CLK_AUDIO1_2X 114 137 + #define TEGRA30_CLK_AUDIO2_2X 115 138 + #define TEGRA30_CLK_AUDIO3_2X 116 139 + #define TEGRA30_CLK_AUDIO4_2X 117 140 + #define TEGRA30_CLK_SPDIF_2X 118 141 + #define TEGRA30_CLK_ACTMON 119 142 + #define TEGRA30_CLK_EXTERN1 120 143 + #define TEGRA30_CLK_EXTERN2 121 144 + #define TEGRA30_CLK_EXTERN3 122 145 + #define TEGRA30_CLK_SATA_OOB 123 146 + #define TEGRA30_CLK_SATA 124 147 + #define TEGRA30_CLK_HDA 125 148 + /* 126 */ 149 + #define TEGRA30_CLK_SE 127 150 + 151 + #define TEGRA30_CLK_HDA2HDMI 128 152 + #define TEGRA30_CLK_SATA_COLD 129 153 + /* 130 */ 154 + /* 131 */ 155 + /* 132 */ 156 + /* 133 */ 157 + /* 134 */ 158 + /* 135 */ 159 + /* 136 */ 160 + /* 137 */ 161 + /* 138 */ 162 + /* 139 */ 163 + /* 140 */ 164 + /* 141 */ 165 + /* 142 */ 166 + /* 143 */ 167 + /* 144 */ 168 + /* 145 */ 169 + /* 146 */ 170 + /* 147 */ 171 + /* 148 */ 172 + /* 149 */ 173 + /* 150 */ 174 + /* 151 */ 175 + /* 152 */ 176 + /* 153 */ 177 + /* 154 */ 178 + /* 155 */ 179 + /* 156 */ 180 + /* 157 */ 181 + /* 158 */ 182 + /* 159 */ 183 + 184 + #define TEGRA30_CLK_UARTB 160 185 + #define TEGRA30_CLK_VFIR 161 186 + #define TEGRA30_CLK_SPDIF_IN 162 187 + #define TEGRA30_CLK_SPDIF_OUT 163 188 + #define TEGRA30_CLK_VI 164 189 + #define TEGRA30_CLK_VI_SENSOR 165 190 + #define TEGRA30_CLK_FUSE 166 191 + #define TEGRA30_CLK_FUSE_BURN 167 192 + #define TEGRA30_CLK_CVE 168 193 + #define TEGRA30_CLK_TVO 169 194 + #define TEGRA30_CLK_CLK_32K 170 195 + #define TEGRA30_CLK_CLK_M 171 196 + #define TEGRA30_CLK_CLK_M_DIV2 172 197 + #define TEGRA30_CLK_CLK_M_DIV4 173 198 + #define TEGRA30_CLK_PLL_REF 174 199 + #define TEGRA30_CLK_PLL_C 175 200 + #define TEGRA30_CLK_PLL_C_OUT1 176 201 + #define TEGRA30_CLK_PLL_M 177 202 + #define TEGRA30_CLK_PLL_M_OUT1 178 203 + #define TEGRA30_CLK_PLL_P 179 204 + #define TEGRA30_CLK_PLL_P_OUT1 180 205 + #define TEGRA30_CLK_PLL_P_OUT2 181 206 + #define TEGRA30_CLK_PLL_P_OUT3 182 207 + #define TEGRA30_CLK_PLL_P_OUT4 183 208 + #define TEGRA30_CLK_PLL_A 184 209 + #define TEGRA30_CLK_PLL_A_OUT0 185 210 + #define TEGRA30_CLK_PLL_D 186 211 + #define TEGRA30_CLK_PLL_D_OUT0 187 212 + #define TEGRA30_CLK_PLL_D2 188 213 + #define TEGRA30_CLK_PLL_D2_OUT0 189 214 + #define TEGRA30_CLK_PLL_U 190 215 + #define TEGRA30_CLK_PLL_X 191 216 + 217 + #define TEGRA30_CLK_PLL_X_OUT0 192 218 + #define TEGRA30_CLK_PLL_E 193 219 + #define TEGRA30_CLK_SPDIF_IN_SYNC 194 220 + #define TEGRA30_CLK_I2S0_SYNC 195 221 + #define TEGRA30_CLK_I2S1_SYNC 196 222 + #define TEGRA30_CLK_I2S2_SYNC 197 223 + #define TEGRA30_CLK_I2S3_SYNC 198 224 + #define TEGRA30_CLK_I2S4_SYNC 199 225 + #define TEGRA30_CLK_VIMCLK_SYNC 200 226 + #define TEGRA30_CLK_AUDIO0 201 227 + #define TEGRA30_CLK_AUDIO1 202 228 + #define TEGRA30_CLK_AUDIO2 203 229 + #define TEGRA30_CLK_AUDIO3 204 230 + #define TEGRA30_CLK_AUDIO4 205 231 + #define TEGRA30_CLK_SPDIF 206 232 + #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 233 + #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 234 + #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 235 + #define TEGRA30_CLK_SCLK 210 236 + #define TEGRA30_CLK_BLINK 211 237 + #define TEGRA30_CLK_CCLK_G 212 238 + #define TEGRA30_CLK_CCLK_LP 213 239 + #define TEGRA30_CLK_TWD 214 240 + #define TEGRA30_CLK_CML0 215 241 + #define TEGRA30_CLK_CML1 216 242 + #define TEGRA30_CLK_HCLK 217 243 + #define TEGRA30_CLK_PCLK 218 244 + /* 219 */ 245 + /* 220 */ 246 + /* 221 */ 247 + /* 222 */ 248 + /* 223 */ 249 + 250 + /* 288 */ 251 + /* 289 */ 252 + /* 290 */ 253 + /* 291 */ 254 + /* 292 */ 255 + /* 293 */ 256 + /* 294 */ 257 + /* 295 */ 258 + /* 296 */ 259 + /* 297 */ 260 + /* 298 */ 261 + /* 299 */ 262 + #define TEGRA30_CLK_CLK_OUT_1_MUX 300 263 + #define TEGRA30_CLK_CLK_MAX 301 264 + 265 + #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
+50
include/dt-bindings/gpio/tegra-gpio.h
··· 1 + /* 2 + * This header provides constants for binding nvidia,tegra*-gpio. 3 + * 4 + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 5 + * provide names for this. 6 + * 7 + * The second cell contains standard flag values specified in gpio.h. 8 + */ 9 + 10 + #ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H 11 + #define _DT_BINDINGS_GPIO_TEGRA_GPIO_H 12 + 13 + #include <dt-bindings/gpio/gpio.h> 14 + 15 + #define TEGRA_GPIO_BANK_ID_A 0 16 + #define TEGRA_GPIO_BANK_ID_B 1 17 + #define TEGRA_GPIO_BANK_ID_C 2 18 + #define TEGRA_GPIO_BANK_ID_D 3 19 + #define TEGRA_GPIO_BANK_ID_E 4 20 + #define TEGRA_GPIO_BANK_ID_F 5 21 + #define TEGRA_GPIO_BANK_ID_G 6 22 + #define TEGRA_GPIO_BANK_ID_H 7 23 + #define TEGRA_GPIO_BANK_ID_I 8 24 + #define TEGRA_GPIO_BANK_ID_J 9 25 + #define TEGRA_GPIO_BANK_ID_K 10 26 + #define TEGRA_GPIO_BANK_ID_L 11 27 + #define TEGRA_GPIO_BANK_ID_M 12 28 + #define TEGRA_GPIO_BANK_ID_N 13 29 + #define TEGRA_GPIO_BANK_ID_O 14 30 + #define TEGRA_GPIO_BANK_ID_P 15 31 + #define TEGRA_GPIO_BANK_ID_Q 16 32 + #define TEGRA_GPIO_BANK_ID_R 17 33 + #define TEGRA_GPIO_BANK_ID_S 18 34 + #define TEGRA_GPIO_BANK_ID_T 19 35 + #define TEGRA_GPIO_BANK_ID_U 20 36 + #define TEGRA_GPIO_BANK_ID_V 21 37 + #define TEGRA_GPIO_BANK_ID_W 22 38 + #define TEGRA_GPIO_BANK_ID_X 23 39 + #define TEGRA_GPIO_BANK_ID_Y 24 40 + #define TEGRA_GPIO_BANK_ID_Z 25 41 + #define TEGRA_GPIO_BANK_ID_AA 26 42 + #define TEGRA_GPIO_BANK_ID_BB 27 43 + #define TEGRA_GPIO_BANK_ID_CC 28 44 + #define TEGRA_GPIO_BANK_ID_DD 29 45 + #define TEGRA_GPIO_BANK_ID_EE 30 46 + 47 + #define TEGRA_GPIO(bank, offset) \ 48 + ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) 49 + 50 + #endif