Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

soc: mediatek: add MT6797 scpsys support

This adds scpsys support for MT6797

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

authored by

Mars Cheng and committed by
Matthias Brugger
36c310f5 a3acbbf4

+144
+114
drivers/soc/mediatek/mtk-scpsys.c
··· 21 21 #include <linux/soc/mediatek/infracfg.h> 22 22 23 23 #include <dt-bindings/power/mt2701-power.h> 24 + #include <dt-bindings/power/mt6797-power.h> 24 25 #include <dt-bindings/power/mt8173-power.h> 25 26 26 27 #define SPM_VDE_PWR_CON 0x0210 ··· 586 585 } 587 586 588 587 /* 588 + * MT6797 power domain support 589 + */ 590 + 591 + static const struct scp_domain_data scp_domain_data_mt6797[] = { 592 + [MT6797_POWER_DOMAIN_VDEC] = { 593 + .name = "vdec", 594 + .sta_mask = BIT(7), 595 + .ctl_offs = 0x300, 596 + .sram_pdn_bits = GENMASK(8, 8), 597 + .sram_pdn_ack_bits = GENMASK(12, 12), 598 + .clk_id = {CLK_VDEC}, 599 + }, 600 + [MT6797_POWER_DOMAIN_VENC] = { 601 + .name = "venc", 602 + .sta_mask = BIT(21), 603 + .ctl_offs = 0x304, 604 + .sram_pdn_bits = GENMASK(11, 8), 605 + .sram_pdn_ack_bits = GENMASK(15, 12), 606 + .clk_id = {CLK_NONE}, 607 + }, 608 + [MT6797_POWER_DOMAIN_ISP] = { 609 + .name = "isp", 610 + .sta_mask = BIT(5), 611 + .ctl_offs = 0x308, 612 + .sram_pdn_bits = GENMASK(9, 8), 613 + .sram_pdn_ack_bits = GENMASK(13, 12), 614 + .clk_id = {CLK_NONE}, 615 + }, 616 + [MT6797_POWER_DOMAIN_MM] = { 617 + .name = "mm", 618 + .sta_mask = BIT(3), 619 + .ctl_offs = 0x30C, 620 + .sram_pdn_bits = GENMASK(8, 8), 621 + .sram_pdn_ack_bits = GENMASK(12, 12), 622 + .clk_id = {CLK_MM}, 623 + .bus_prot_mask = (BIT(1) | BIT(2)), 624 + }, 625 + [MT6797_POWER_DOMAIN_AUDIO] = { 626 + .name = "audio", 627 + .sta_mask = BIT(24), 628 + .ctl_offs = 0x314, 629 + .sram_pdn_bits = GENMASK(11, 8), 630 + .sram_pdn_ack_bits = GENMASK(15, 12), 631 + .clk_id = {CLK_NONE}, 632 + }, 633 + [MT6797_POWER_DOMAIN_MFG_ASYNC] = { 634 + .name = "mfg_async", 635 + .sta_mask = BIT(13), 636 + .ctl_offs = 0x334, 637 + .sram_pdn_bits = 0, 638 + .sram_pdn_ack_bits = 0, 639 + .clk_id = {CLK_MFG}, 640 + }, 641 + [MT6797_POWER_DOMAIN_MJC] = { 642 + .name = "mjc", 643 + .sta_mask = BIT(20), 644 + .ctl_offs = 0x310, 645 + .sram_pdn_bits = GENMASK(8, 8), 646 + .sram_pdn_ack_bits = GENMASK(12, 12), 647 + .clk_id = {CLK_NONE}, 648 + }, 649 + }; 650 + 651 + #define NUM_DOMAINS_MT6797 ARRAY_SIZE(scp_domain_data_mt6797) 652 + #define SPM_PWR_STATUS_MT6797 0x0180 653 + #define SPM_PWR_STATUS_2ND_MT6797 0x0184 654 + 655 + static int __init scpsys_probe_mt6797(struct platform_device *pdev) 656 + { 657 + struct scp *scp; 658 + struct genpd_onecell_data *pd_data; 659 + int ret; 660 + struct scp_ctrl_reg scp_reg; 661 + 662 + scp_reg.pwr_sta_offs = SPM_PWR_STATUS_MT6797; 663 + scp_reg.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797; 664 + 665 + scp = init_scp(pdev, scp_domain_data_mt6797, NUM_DOMAINS_MT6797, 666 + &scp_reg); 667 + if (IS_ERR(scp)) 668 + return PTR_ERR(scp); 669 + 670 + mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT6797); 671 + 672 + pd_data = &scp->pd_data; 673 + 674 + ret = pm_genpd_add_subdomain(pd_data->domains[MT6797_POWER_DOMAIN_MM], 675 + pd_data->domains[MT6797_POWER_DOMAIN_VDEC]); 676 + if (ret && IS_ENABLED(CONFIG_PM)) 677 + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); 678 + 679 + ret = pm_genpd_add_subdomain(pd_data->domains[MT6797_POWER_DOMAIN_MM], 680 + pd_data->domains[MT6797_POWER_DOMAIN_ISP]); 681 + if (ret && IS_ENABLED(CONFIG_PM)) 682 + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); 683 + 684 + ret = pm_genpd_add_subdomain(pd_data->domains[MT6797_POWER_DOMAIN_MM], 685 + pd_data->domains[MT6797_POWER_DOMAIN_VENC]); 686 + if (ret && IS_ENABLED(CONFIG_PM)) 687 + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); 688 + 689 + ret = pm_genpd_add_subdomain(pd_data->domains[MT6797_POWER_DOMAIN_MM], 690 + pd_data->domains[MT6797_POWER_DOMAIN_MJC]); 691 + if (ret && IS_ENABLED(CONFIG_PM)) 692 + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); 693 + 694 + return 0; 695 + } 696 + 697 + /* 589 698 * MT8173 power domain support 590 699 */ 591 700 ··· 831 720 { 832 721 .compatible = "mediatek,mt2701-scpsys", 833 722 .data = scpsys_probe_mt2701, 723 + }, { 724 + .compatible = "mediatek,mt6797-scpsys", 725 + .data = scpsys_probe_mt6797, 834 726 }, { 835 727 .compatible = "mediatek,mt8173-scpsys", 836 728 .data = scpsys_probe_mt8173,
+30
include/dt-bindings/power/mt6797-power.h
··· 1 + /* 2 + * Copyright (c) 2017 MediaTek Inc. 3 + * Author: Mars.C <mars.cheng@mediatek.com> 4 + * 5 + * This program is free software; you can redistribute it and/or modify 6 + * it under the terms of the GNU General Public License version 2 as 7 + * published by the Free Software Foundation. 8 + * 9 + * This program is distributed in the hope that it will be useful, 10 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 + * GNU General Public License for more details. 12 + */ 13 + 14 + #ifndef _DT_BINDINGS_POWER_MT6797_POWER_H 15 + #define _DT_BINDINGS_POWER_MT6797_POWER_H 16 + 17 + #define MT6797_POWER_DOMAIN_VDEC 0 18 + #define MT6797_POWER_DOMAIN_VENC 1 19 + #define MT6797_POWER_DOMAIN_ISP 2 20 + #define MT6797_POWER_DOMAIN_MM 3 21 + #define MT6797_POWER_DOMAIN_AUDIO 4 22 + #define MT6797_POWER_DOMAIN_MFG_ASYNC 5 23 + #define MT6797_POWER_DOMAIN_MFG 6 24 + #define MT6797_POWER_DOMAIN_MFG_CORE0 7 25 + #define MT6797_POWER_DOMAIN_MFG_CORE1 8 26 + #define MT6797_POWER_DOMAIN_MFG_CORE2 9 27 + #define MT6797_POWER_DOMAIN_MFG_CORE3 10 28 + #define MT6797_POWER_DOMAIN_MJC 11 29 + 30 + #endif /* _DT_BINDINGS_POWER_MT6797_POWER_H */