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MIPS: Remove unreachable break statements from cp1emu.c

There were many cases of:

return something;
break;

All those break statements are unreachable and thus redundant.

Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5727/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

David Daney and committed by
Ralf Baechle 36b0f79b 43d30939

-27
-27
arch/mips/math-emu/cp1emu.c
··· 436 436 break; 437 437 default: 438 438 return SIGILL; 439 - break; 440 439 } 441 440 break; 442 441 case mm_32f_74_op: /* c.cond.fmt */ ··· 450 451 break; 451 452 default: 452 453 return SIGILL; 453 - break; 454 454 } 455 455 break; 456 456 default: 457 457 return SIGILL; 458 - break; 459 458 } 460 459 461 460 *insn_ptr = mips32_insn; ··· 488 491 dec_insn.next_pc_inc; 489 492 *contpc = regs->regs[insn.mm_i_format.rs]; 490 493 return 1; 491 - break; 492 494 } 493 495 } 494 496 break; ··· 509 513 dec_insn.pc_inc + 510 514 dec_insn.next_pc_inc; 511 515 return 1; 512 - break; 513 516 case mm_bgezals_op: 514 517 case mm_bgezal_op: 515 518 regs->regs[31] = regs->cp0_epc + ··· 525 530 dec_insn.pc_inc + 526 531 dec_insn.next_pc_inc; 527 532 return 1; 528 - break; 529 533 case mm_blez_op: 530 534 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 531 535 *contpc = regs->cp0_epc + ··· 535 541 dec_insn.pc_inc + 536 542 dec_insn.next_pc_inc; 537 543 return 1; 538 - break; 539 544 case mm_bgtz_op: 540 545 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 541 546 *contpc = regs->cp0_epc + ··· 545 552 dec_insn.pc_inc + 546 553 dec_insn.next_pc_inc; 547 554 return 1; 548 - break; 549 555 case mm_bc2f_op: 550 556 case mm_bc1f_op: 551 557 bc_false = 1; ··· 572 580 *contpc = regs->cp0_epc + 573 581 dec_insn.pc_inc + dec_insn.next_pc_inc; 574 582 return 1; 575 - break; 576 583 } 577 584 break; 578 585 case mm_pool16c_op: ··· 584 593 case mm_jr16_op: 585 594 *contpc = regs->regs[insn.mm_i_format.rs]; 586 595 return 1; 587 - break; 588 596 } 589 597 break; 590 598 case mm_beqz16_op: ··· 595 605 *contpc = regs->cp0_epc + 596 606 dec_insn.pc_inc + dec_insn.next_pc_inc; 597 607 return 1; 598 - break; 599 608 case mm_bnez16_op: 600 609 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) 601 610 *contpc = regs->cp0_epc + ··· 604 615 *contpc = regs->cp0_epc + 605 616 dec_insn.pc_inc + dec_insn.next_pc_inc; 606 617 return 1; 607 - break; 608 618 case mm_b16_op: 609 619 *contpc = regs->cp0_epc + dec_insn.pc_inc + 610 620 (insn.mm_b0_format.simmediate << 1); 611 621 return 1; 612 - break; 613 622 case mm_beq32_op: 614 623 if (regs->regs[insn.mm_i_format.rs] == 615 624 regs->regs[insn.mm_i_format.rt]) ··· 619 632 dec_insn.pc_inc + 620 633 dec_insn.next_pc_inc; 621 634 return 1; 622 - break; 623 635 case mm_bne32_op: 624 636 if (regs->regs[insn.mm_i_format.rs] != 625 637 regs->regs[insn.mm_i_format.rt]) ··· 629 643 *contpc = regs->cp0_epc + 630 644 dec_insn.pc_inc + dec_insn.next_pc_inc; 631 645 return 1; 632 - break; 633 646 case mm_jalx32_op: 634 647 regs->regs[31] = regs->cp0_epc + 635 648 dec_insn.pc_inc + dec_insn.next_pc_inc; ··· 637 652 *contpc <<= 28; 638 653 *contpc |= (insn.j_format.target << 2); 639 654 return 1; 640 - break; 641 655 case mm_jals32_op: 642 656 case mm_jal32_op: 643 657 regs->regs[31] = regs->cp0_epc + ··· 649 665 *contpc |= (insn.j_format.target << 1); 650 666 set_isa16_mode(*contpc); 651 667 return 1; 652 - break; 653 668 } 654 669 return 0; 655 670 } ··· 677 694 case jr_op: 678 695 *contpc = regs->regs[insn.r_format.rs]; 679 696 return 1; 680 - break; 681 697 } 682 698 break; 683 699 case bcond_op: ··· 698 716 dec_insn.pc_inc + 699 717 dec_insn.next_pc_inc; 700 718 return 1; 701 - break; 702 719 case bgezal_op: 703 720 case bgezall_op: 704 721 regs->regs[31] = regs->cp0_epc + ··· 715 734 dec_insn.pc_inc + 716 735 dec_insn.next_pc_inc; 717 736 return 1; 718 - break; 719 737 } 720 738 break; 721 739 case jalx_op: ··· 732 752 /* Set microMIPS mode bit: XOR for jalx. */ 733 753 *contpc ^= bit; 734 754 return 1; 735 - break; 736 755 case beq_op: 737 756 case beql_op: 738 757 if (regs->regs[insn.i_format.rs] == ··· 744 765 dec_insn.pc_inc + 745 766 dec_insn.next_pc_inc; 746 767 return 1; 747 - break; 748 768 case bne_op: 749 769 case bnel_op: 750 770 if (regs->regs[insn.i_format.rs] != ··· 756 778 dec_insn.pc_inc + 757 779 dec_insn.next_pc_inc; 758 780 return 1; 759 - break; 760 781 case blez_op: 761 782 case blezl_op: 762 783 if ((long)regs->regs[insn.i_format.rs] <= 0) ··· 767 790 dec_insn.pc_inc + 768 791 dec_insn.next_pc_inc; 769 792 return 1; 770 - break; 771 793 case bgtz_op: 772 794 case bgtzl_op: 773 795 if ((long)regs->regs[insn.i_format.rs] > 0) ··· 778 802 dec_insn.pc_inc + 779 803 dec_insn.next_pc_inc; 780 804 return 1; 781 - break; 782 805 #ifdef CONFIG_CPU_CAVIUM_OCTEON 783 806 case lwc2_op: /* This is bbit0 on Octeon */ 784 807 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) ··· 831 856 dec_insn.pc_inc + 832 857 dec_insn.next_pc_inc; 833 858 return 1; 834 - break; 835 859 case 1: /* bc1t */ 836 860 case 3: /* bc1tl */ 837 861 if (fcr31 & (1 << bit)) ··· 842 868 dec_insn.pc_inc + 843 869 dec_insn.next_pc_inc; 844 870 return 1; 845 - break; 846 871 } 847 872 } 848 873 break;