tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom-qmp-pcie: Add RC init sequence for SDX55

Add PCIe RC init sequence making use of the common init sequence. The RC
mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and
powerdown.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 364c748d 458aa820

+50 -1
+48 -1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1146 1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1147 1147 }; 1148 1148 1149 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1150 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1151 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1152 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1153 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1154 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1155 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1156 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1157 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1158 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1159 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1160 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1161 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1162 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1163 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1164 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1165 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1166 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1167 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1168 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1169 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1170 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1171 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1172 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1173 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1174 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1175 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1176 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1177 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1178 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1179 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1180 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1181 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1182 + }; 1183 + 1149 1184 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1150 1185 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1151 1186 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), ··· 1258 1223 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1259 1224 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1260 1225 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1226 + }; 1227 + 1228 + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1229 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1230 + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1261 1231 }; 1262 1232 1263 1233 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { ··· 2348 2308 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 2349 2309 }, 2350 2310 2311 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2312 + .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 2313 + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 2314 + .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 2315 + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 2316 + }, 2317 + 2351 2318 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2352 2319 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 2353 2320 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), ··· 2370 2323 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2371 2324 .regs = pciephy_v4_regs_layout, 2372 2325 2373 - .pwrdn_ctrl = SW_PWRDN, 2326 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2374 2327 .phy_status = PHYSTATUS_4_20, 2375 2328 }; 2376 2329
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
··· 6 6 #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ 7 7 #define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ 8 8 9 + #define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 10 + #define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 9 11 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 10 12 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 11 13 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4