tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: R5000: Fix TLB hazard handling.
R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.
So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+8
-15
+8
-15
arch/mips/mm/tlbex.c
+8
-15
arch/mips/mm/tlbex.c
···
511
511
512
512
case CPU_R4600:
513
513
case CPU_R4700:
514
-
case CPU_R5000:
515
-
case CPU_R5000A:
516
514
uasm_i_nop(p);
517
515
tlbw(p);
518
516
uasm_i_nop(p);
517
+
break;
518
+
519
+
case CPU_R5000:
520
+
case CPU_R5000A:
521
+
case CPU_NEVADA:
522
+
uasm_i_nop(p); /* QED specifies 2 nops hazard */
523
+
uasm_i_nop(p); /* QED specifies 2 nops hazard */
524
+
tlbw(p);
519
525
break;
520
526
521
527
case CPU_R4300:
···
555
549
uasm_i_nop(p);
556
550
case CPU_ALCHEMY:
557
551
tlbw(p);
558
-
break;
559
-
560
-
case CPU_NEVADA:
561
-
uasm_i_nop(p); /* QED specifies 2 nops hazard */
562
-
uasm_i_nop(p); /* QED specifies 2 nops hazard */
563
-
/*
564
-
* This branch uses up a mtc0 hazard nop slot and saves
565
-
* a nop after the tlbw instruction.
566
-
*/
567
-
uasm_bgezl_hazard(p, r, hazard_instance);
568
-
tlbw(p);
569
-
uasm_bgezl_label(l, p, hazard_instance);
570
-
hazard_instance++;
571
552
break;
572
553
573
554
case CPU_RM7000: