tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdkfd: Preserve cp_hqd_pq_control on update_mqd

When userspace applications call AMDKFD_IOC_UPDATE_QUEUE. Preserve
bitfields that do not need to be modified as they contain flags to
track queue states that are used by CP FW.

Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 8150827990b709ab5a40c46c30d21b7f7b9e9440)
Cc: stable@vger.kernel.org

authored by

David Yat Sin and committed by
Alex Deucher 3502ab50 91dcc66b

+14 -7
+4 -2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
··· 107 107 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 108 108 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 109 109 110 + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 111 + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 110 112 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 111 113 112 114 m->cp_mqd_base_addr_lo = lower_32_bits(addr); ··· 169 167 170 168 m = get_mqd(mqd); 171 169 172 - m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 170 + m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 173 171 m->cp_hqd_pq_control |= 174 172 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 175 - m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 173 + 176 174 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 177 175 178 176 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+3 -2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
··· 154 154 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 155 155 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 156 156 157 + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 158 + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 157 159 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 158 160 159 161 m->cp_mqd_base_addr_lo = lower_32_bits(addr); ··· 223 221 224 222 m = get_mqd(mqd); 225 223 226 - m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 224 + m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 227 225 m->cp_hqd_pq_control |= 228 226 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 229 - m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 230 227 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 231 228 232 229 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+3 -2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
··· 121 121 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 122 122 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 123 123 124 + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 125 + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 124 126 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 125 127 126 128 m->cp_mqd_base_addr_lo = lower_32_bits(addr); ··· 186 184 187 185 m = get_mqd(mqd); 188 186 189 - m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 187 + m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 190 188 m->cp_hqd_pq_control |= 191 189 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 192 - m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 193 190 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 194 191 195 192 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+4 -1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
··· 183 183 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 184 184 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 185 185 186 + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 187 + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 188 + 186 189 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 187 190 188 191 m->cp_mqd_base_addr_lo = lower_32_bits(addr); ··· 248 245 249 246 m = get_mqd(mqd); 250 247 251 - m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 248 + m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 252 249 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 253 250 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 254 251