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drm/amd/pm: update driver if file for sienna cichlid

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Likun Gao and committed by
Alex Deucher 34d903d1 93a80241

+12 -28
+11 -5
drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
··· 27 27 // *** IMPORTANT *** 28 28 // SMU TEAM: Always increment the interface version if 29 29 // any structure is changed in this file 30 - #define SMU11_DRIVER_IF_VERSION 0x3A 30 + #define SMU11_DRIVER_IF_VERSION 0x3B 31 31 32 - #define PPTABLE_Sienna_Cichlid_SMU_VERSION 6 32 + #define PPTABLE_Sienna_Cichlid_SMU_VERSION 7 33 33 34 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 35 #define NUM_SMNCLK_DPM_LEVELS 2 ··· 437 437 PIECEWISE_LINEAR_FUSED_MODEL = 0, 438 438 PIECEWISE_LINEAR_PP_MODEL, 439 439 QUADRATIC_PP_MODEL, 440 + PERPART_PIECEWISE_LINEAR_PP_MODEL, 440 441 } DfllDroopModelSelect_e; 441 442 442 443 typedef struct { ··· 613 612 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 614 613 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 615 614 616 - uint32_t PaddingAPCC[4]; 615 + uint32_t PaddingAPCC; 616 + uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 617 + uint16_t PaddingPerPartDroop; 617 618 618 619 // SECTION: Throttler settings 619 620 uint32_t ThrottlerControlMask; // See Throtter masks defines ··· 670 667 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 671 668 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 672 669 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 673 - uint32_t Paddingclks[16]; 670 + uint32_t Paddingclks; 671 + 672 + DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 674 673 675 674 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 676 675 ··· 1226 1221 #define WORKLOAD_PPLIB_VR_BIT 4 1227 1222 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1228 1223 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1229 - #define WORKLOAD_PPLIB_COUNT 7 1224 + #define WORKLOAD_PPLIB_W3D_BIT 7 1225 + #define WORKLOAD_PPLIB_COUNT 8 1230 1226 1231 1227 1232 1228 // These defines are used with the following messages:
+1 -1
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
··· 30 30 #define SMU11_DRIVER_IF_VERSION_NV10 0x36 31 31 #define SMU11_DRIVER_IF_VERSION_NV12 0x36 32 32 #define SMU11_DRIVER_IF_VERSION_NV14 0x36 33 - #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A 33 + #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B 34 34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5 35 35 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02 36 36 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD
-22
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
··· 1805 1805 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 1806 1806 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 1807 1807 } 1808 - dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]); 1809 - dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]); 1810 - dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]); 1811 - dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]); 1812 - 1813 1808 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 1814 1809 1815 1810 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); ··· 2030 2035 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2031 2036 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2032 2037 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2033 - 2034 - dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]); 2035 - dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]); 2036 - dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]); 2037 - dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]); 2038 - dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]); 2039 - dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]); 2040 - dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]); 2041 - dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]); 2042 - dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]); 2043 - dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]); 2044 - dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]); 2045 - dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]); 2046 - dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]); 2047 - dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]); 2048 - dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]); 2049 - dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]); 2050 2038 2051 2039 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2052 2040 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);