tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle 34adb28d f9861407

+40 -43
+6 -9
arch/mips/Kconfig
··· 63 63 64 64 config MIPS_ALCHEMY 65 65 bool "Alchemy processor based machines" 66 - select 64BIT_PHYS_ADDR 66 + select ARCH_PHYS_ADDR_T_64BIT 67 67 select CEVT_R4K 68 68 select CSRC_R4K 69 69 select IRQ_CPU ··· 771 771 config CAVIUM_OCTEON_SOC 772 772 bool "Cavium Networks Octeon SoC based boards" 773 773 select CEVT_R4K 774 - select 64BIT_PHYS_ADDR 774 + select ARCH_PHYS_ADDR_T_64BIT 775 775 select DMA_COHERENT 776 776 select SYS_SUPPORTS_64BIT_KERNEL 777 777 select SYS_SUPPORTS_BIG_ENDIAN ··· 813 813 select SWAP_IO_SPACE 814 814 select SYS_SUPPORTS_32BIT_KERNEL 815 815 select SYS_SUPPORTS_64BIT_KERNEL 816 - select 64BIT_PHYS_ADDR 816 + select ARCH_PHYS_ADDR_T_64BIT 817 817 select SYS_SUPPORTS_BIG_ENDIAN 818 818 select SYS_SUPPORTS_HIGHMEM 819 819 select DMA_COHERENT ··· 839 839 select HW_HAS_PCI 840 840 select SYS_SUPPORTS_32BIT_KERNEL 841 841 select SYS_SUPPORTS_64BIT_KERNEL 842 - select 64BIT_PHYS_ADDR 842 + select ARCH_PHYS_ADDR_T_64BIT 843 843 select SYS_SUPPORTS_BIG_ENDIAN 844 844 select SYS_SUPPORTS_LITTLE_ENDIAN 845 845 select SYS_SUPPORTS_HIGHMEM ··· 979 979 bool 980 980 981 981 config ARCH_DMA_ADDR_T_64BIT 982 - def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT 982 + def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT 983 983 984 984 config DMA_MAYBE_COHERENT 985 985 select DMA_NONCOHERENT ··· 2124 2124 default y 2125 2125 2126 2126 2127 - config 64BIT_PHYS_ADDR 2128 - bool 2129 - 2130 2127 config ARCH_PHYS_ADDR_T_64BIT 2131 - def_bool 64BIT_PHYS_ADDR 2128 + bool 2132 2129 2133 2130 config CPU_HAS_SMARTMIPS 2134 2131 depends on SYS_SUPPORTS_SMARTMIPS
+1 -1
arch/mips/alchemy/common/setup.c
··· 70 70 iomem_resource.end = IOMEM_RESOURCE_END; 71 71 } 72 72 73 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) 73 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI) 74 74 /* This routine should be valid for all Au1x based boards */ 75 75 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 76 76 {
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arch/mips/include/asm/mach-au1x00/ioremap.h
··· 11 11 12 12 #include <linux/types.h> 13 13 14 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) 14 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI) 15 15 extern phys_t __fixup_bigphys_addr(phys_t, phys_t); 16 16 #else 17 17 static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+1 -1
arch/mips/include/asm/page.h
··· 116 116 /* 117 117 * These are used to make use of C type-checking.. 118 118 */ 119 - #ifdef CONFIG_64BIT_PHYS_ADDR 119 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 120 120 #ifdef CONFIG_CPU_MIPS32 121 121 typedef struct { unsigned long pte_low, pte_high; } pte_t; 122 122 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+7 -7
arch/mips/include/asm/pgtable-32.h
··· 69 69 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 70 70 #endif 71 71 72 - #ifdef CONFIG_64BIT_PHYS_ADDR 72 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 73 73 #define pte_ERROR(e) \ 74 74 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) 75 75 #else ··· 103 103 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 104 104 } 105 105 106 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 106 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 107 107 #define pte_page(x) pfn_to_page(pte_pfn(x)) 108 108 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 109 109 static inline pte_t ··· 126 126 #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) 127 127 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) 128 128 #endif 129 - #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 129 + #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ 130 130 131 131 #define __pgd_offset(address) pgd_index(address) 132 132 #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) ··· 177 177 #else 178 178 179 179 /* Swap entries must have VALID and GLOBAL bits cleared. */ 180 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 180 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 181 181 #define __swp_type(x) (((x).val >> 2) & 0x1f) 182 182 #define __swp_offset(x) ((x).val >> 7) 183 183 #define __swp_entry(type,offset) \ ··· 187 187 #define __swp_offset(x) ((x).val >> 13) 188 188 #define __swp_entry(type,offset) \ 189 189 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) 190 - #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 190 + #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ 191 191 192 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 192 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 193 193 /* 194 194 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset... 195 195 */ ··· 216 216 217 217 #endif 218 218 219 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 219 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 220 220 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) 221 221 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) 222 222 #else
+2 -2
arch/mips/include/asm/pgtable-bits.h
··· 32 32 * unpredictable things. The code (when it is written) to deal with 33 33 * this problem will be in the update_mmu_cache() code for the r4k. 34 34 */ 35 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 35 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 36 36 37 37 /* 38 38 * The following bits are directly used by the TLB hardware ··· 172 172 173 173 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 174 174 175 - #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 175 + #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 176 176 177 177 #ifndef _PFN_SHIFT 178 178 #define _PFN_SHIFT PAGE_SHIFT
+4 -4
arch/mips/include/asm/pgtable.h
··· 125 125 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 126 126 pte_t pteval); 127 127 128 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 128 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 129 129 130 130 #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 131 131 #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) ··· 227 227 * The following only work if pte_present() is true. 228 228 * Undefined behaviour if not.. 229 229 */ 230 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 230 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 231 231 static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } 232 232 static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } 233 233 static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } ··· 382 382 */ 383 383 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 384 384 385 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 385 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 386 386 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 387 387 { 388 388 pte.pte_low &= _PAGE_CHG_MASK; ··· 419 419 420 420 #define kern_addr_valid(addr) (1) 421 421 422 - #ifdef CONFIG_64BIT_PHYS_ADDR 422 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 423 423 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); 424 424 425 425 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+1 -1
arch/mips/include/asm/types.h
··· 22 22 /* 23 23 * Don't use phys_t. You've been warned. 24 24 */ 25 - #ifdef CONFIG_64BIT_PHYS_ADDR 25 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 26 26 typedef unsigned long long phys_t; 27 27 #else 28 28 typedef unsigned long phys_t;
+1 -1
arch/mips/mm/gup.c
··· 17 17 18 18 static inline pte_t gup_get_pte(pte_t *ptep) 19 19 { 20 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 20 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 21 21 pte_t pte; 22 22 23 23 retry:
+1 -1
arch/mips/mm/init.c
··· 95 95 idx += in_interrupt() ? FIX_N_COLOURS : 0; 96 96 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 97 97 pte = mk_pte(page, prot); 98 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 98 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 99 99 entrylo = pte.pte_high; 100 100 #else 101 101 entrylo = pte_to_entrylo(pte_val(pte));
+1 -1
arch/mips/mm/tlb-r4k.c
··· 332 332 { 333 333 ptep = pte_offset_map(pmdp, address); 334 334 335 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 335 + #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 336 336 write_c0_entrylo0(ptep->pte_high); 337 337 ptep++; 338 338 write_c0_entrylo1(ptep->pte_high);
+9 -9
arch/mips/mm/tlbex.c
··· 637 637 if (cpu_has_rixi) { 638 638 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 639 639 } else { 640 - #ifdef CONFIG_64BIT_PHYS_ADDR 640 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 641 641 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 642 642 #else 643 643 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); ··· 1009 1009 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1010 1010 * Kernel is a special case. Only a few CPUs use it. 1011 1011 */ 1012 - #ifdef CONFIG_64BIT_PHYS_ADDR 1012 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 1013 1013 if (cpu_has_64bits) { 1014 1014 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ 1015 1015 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ ··· 1510 1510 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1511 1511 { 1512 1512 #ifdef CONFIG_SMP 1513 - # ifdef CONFIG_64BIT_PHYS_ADDR 1513 + # ifdef CONFIG_PHYS_ADDR_T_64BIT 1514 1514 if (cpu_has_64bits) 1515 1515 uasm_i_lld(p, pte, 0, ptr); 1516 1516 else 1517 1517 # endif 1518 1518 UASM_i_LL(p, pte, 0, ptr); 1519 1519 #else 1520 - # ifdef CONFIG_64BIT_PHYS_ADDR 1520 + # ifdef CONFIG_PHYS_ADDR_T_64BIT 1521 1521 if (cpu_has_64bits) 1522 1522 uasm_i_ld(p, pte, 0, ptr); 1523 1523 else ··· 1530 1530 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1531 1531 unsigned int mode) 1532 1532 { 1533 - #ifdef CONFIG_64BIT_PHYS_ADDR 1533 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 1534 1534 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1535 1535 #endif 1536 1536 1537 1537 uasm_i_ori(p, pte, pte, mode); 1538 1538 #ifdef CONFIG_SMP 1539 - # ifdef CONFIG_64BIT_PHYS_ADDR 1539 + # ifdef CONFIG_PHYS_ADDR_T_64BIT 1540 1540 if (cpu_has_64bits) 1541 1541 uasm_i_scd(p, pte, 0, ptr); 1542 1542 else ··· 1548 1548 else 1549 1549 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1550 1550 1551 - # ifdef CONFIG_64BIT_PHYS_ADDR 1551 + # ifdef CONFIG_PHYS_ADDR_T_64BIT 1552 1552 if (!cpu_has_64bits) { 1553 1553 /* no uasm_i_nop needed */ 1554 1554 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); ··· 1563 1563 uasm_i_nop(p); 1564 1564 # endif 1565 1565 #else 1566 - # ifdef CONFIG_64BIT_PHYS_ADDR 1566 + # ifdef CONFIG_PHYS_ADDR_T_64BIT 1567 1567 if (cpu_has_64bits) 1568 1568 uasm_i_sd(p, pte, 0, ptr); 1569 1569 else 1570 1570 # endif 1571 1571 UASM_i_SW(p, pte, 0, ptr); 1572 1572 1573 - # ifdef CONFIG_64BIT_PHYS_ADDR 1573 + # ifdef CONFIG_PHYS_ADDR_T_64BIT 1574 1574 if (!cpu_has_64bits) { 1575 1575 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1576 1576 uasm_i_ori(p, pte, pte, hwmode);
+2 -2
arch/mips/sibyte/common/cfe.c
··· 38 38 #define MAX_RAM_SIZE (~0ULL) 39 39 #else 40 40 #ifdef CONFIG_HIGHMEM 41 - #ifdef CONFIG_64BIT_PHYS_ADDR 41 + #ifdef CONFIG_PHYS_ADDR_T_64BIT 42 42 #define MAX_RAM_SIZE (~0ULL) 43 43 #else 44 44 #define MAX_RAM_SIZE (0xffffffffULL) ··· 96 96 97 97 static __init void prom_meminit(void) 98 98 { 99 - u64 addr, size, type; /* regardless of 64BIT_PHYS_ADDR */ 99 + u64 addr, size, type; /* regardless of PHYS_ADDR_T_64BIT */ 100 100 int mem_flags = 0; 101 101 unsigned int idx; 102 102 int rd_flag;
+1 -1
drivers/dma/txx9dmac.c
··· 76 76 77 77 static void channel64_clear_CHAR(const struct txx9dmac_chan *dc) 78 78 { 79 - #if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR) 79 + #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) 80 80 channel64_writel(dc, CHAR, 0); 81 81 channel64_writel(dc, __pad_CHAR, 0); 82 82 #else
+2 -2
drivers/dma/txx9dmac.h
··· 67 67 68 68 /* Hardware register definitions. */ 69 69 struct txx9dmac_cregs { 70 - #if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR) 70 + #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) 71 71 TXX9_DMA_REG32(CHAR); /* Chain Address Register */ 72 72 #else 73 73 u64 CHAR; /* Chain Address Register */ ··· 201 201 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN 202 202 /* Hardware descriptor definition. (for simple-chain) */ 203 203 struct txx9dmac_hwdesc { 204 - #if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR) 204 + #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) 205 205 TXX9_DMA_REG32(CHAR); 206 206 #else 207 207 u64 CHAR;