Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'arm-soc/for-5.20/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 5.20, please pull the following:

- Stefan drops the unnecessary "#address-cells" and "#size-cells"
properties from the DPI node of BCM283x

- Anand documents and adds support for the 63178 and 6858 SoCs

- William migrates the 63138 platform over to ARCH_BCMBCA and ensures
that it is documented within the BCMBCA Device Tree binding documents.
He updates the 47622 DTS to remove unnecessary PSCI properties, fix
the GIC nodes and some minor cosmetic changes. He finally adds support
for the 63158, 4912, 6846, 6855, 6756, 63146, 6856, 63148, 6813, 6318
SoCs.

- Peter, Nicolas and Stefan adds the necessary Device Tree nodes to the
BCM2711 (Raspberry Pi 4) DTS to enable the use of the V3D GPU on these
platforms.

- Christian adds support for the BCM53015 based Cisco Meraki MR26
Wi-Fi access point.

- Krzysztof updates the Broadcom platforms DTS to add a missing
whitespace between the property name and its value.

* tag 'arm-soc/for-5.20/devicetree' of https://github.com/Broadcom/stblinux: (35 commits)
ARM: dts: Add BCM63138 generic board dts
ARM: dts: update dts files for bcmbca SoC BCM63138
ARM: dts: Move BCM963138DVT board dts to ARCH_BCMBCA
dt-bindings: arm: add BCM63138 SoC
ARM: dts: bcm2711: Use proper compatible in PM/Watchdog node
ARM: dts: bcm2835/bcm2711: Introduce reg-names in watchdog node
dt-bindings: soc: bcm: bcm2835-pm: Add support for bcm2711
dt-bindings: soc: bcm: bcm2835-pm: Introduce reg-names
dt-bindings: soc: bcm: bcm2835-pm: Convert bindings to DT schema
ARM: dts: BCM5301X: Add DT for Meraki MR26
dt-bindings: ARM: add bindings for the Meraki MR26
dt-bindings: arm64: Add BCM6813 SoC
ARM: dts: Add DTS files for bcmbca SoC BCM63148
dt-bindings: arm: Add BCM63148 SoC
dt-bindings: arm64: Add BCM6856 SoC
dt-bindings: arm64: Add BCM63146 SoC
ARM: dts: broadcom: correct gpio-keys properties
ARM: dts: broadcom: align gpio-key node names with dtschema
ARM: dts: Add DTS files for bcmbca SoC BCM6756
dt-bindings: arm: Add BCM6756 SoC
...

Link: https://lore.kernel.org/r/20220711164451.3542127-4-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

+1389 -183
+7
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
··· 87 87 - const: brcm,bcm53012 88 88 - const: brcm,bcm4708 89 89 90 + - description: BCM53015 based boards 91 + items: 92 + - enum: 93 + - meraki,mr26 94 + - const: brcm,bcm53015 95 + - const: brcm,bcm4708 96 + 90 97 - description: BCM53016 based boards 91 98 items: 92 99 - enum:
+92
Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
··· 28 28 - const: brcm,bcm47622 29 29 - const: brcm,bcmbca 30 30 31 + - description: BCM4912 based boards 32 + items: 33 + - enum: 34 + - brcm,bcm94912 35 + - const: brcm,bcm4912 36 + - const: brcm,bcmbca 37 + 38 + - description: BCM63138 based boards 39 + items: 40 + - enum: 41 + - brcm,bcm963138 42 + - brcm,BCM963138DVT 43 + - const: brcm,bcm63138 44 + - const: brcm,bcmbca 45 + 46 + - description: BCM63146 based boards 47 + items: 48 + - enum: 49 + - brcm,bcm963146 50 + - const: brcm,bcm63146 51 + - const: brcm,bcmbca 52 + 53 + - description: BCM63148 based boards 54 + items: 55 + - enum: 56 + - brcm,bcm963148 57 + - const: brcm,bcm63148 58 + - const: brcm,bcmbca 59 + 60 + - description: BCM63158 based boards 61 + items: 62 + - enum: 63 + - brcm,bcm963158 64 + - const: brcm,bcm63158 65 + - const: brcm,bcmbca 66 + 67 + - description: BCM63178 based boards 68 + items: 69 + - enum: 70 + - brcm,bcm963178 71 + - const: brcm,bcm63178 72 + - const: brcm,bcmbca 73 + 74 + - description: BCM6756 based boards 75 + items: 76 + - enum: 77 + - brcm,bcm96756 78 + - const: brcm,bcm6756 79 + - const: brcm,bcmbca 80 + 81 + - description: BCM6813 based boards 82 + items: 83 + - enum: 84 + - brcm,bcm96813 85 + - const: brcm,bcm6813 86 + - const: brcm,bcmbca 87 + 88 + - description: BCM6846 based boards 89 + items: 90 + - enum: 91 + - brcm,bcm96846 92 + - const: brcm,bcm6846 93 + - const: brcm,bcmbca 94 + 95 + - description: BCM6855 based boards 96 + items: 97 + - enum: 98 + - brcm,bcm96855 99 + - const: brcm,bcm6855 100 + - const: brcm,bcmbca 101 + 102 + - description: BCM6856 based boards 103 + items: 104 + - enum: 105 + - brcm,bcm96856 106 + - const: brcm,bcm6856 107 + - const: brcm,bcmbca 108 + 109 + - description: BCM6858 based boards 110 + items: 111 + - enum: 112 + - brcm,bcm96858 113 + - const: brcm,bcm6858 114 + - const: brcm,bcmbca 115 + 116 + - description: BCM6878 based boards 117 + items: 118 + - enum: 119 + - brcm,bcm96878 120 + - const: brcm,bcm6878 121 + - const: brcm,bcmbca 122 + 31 123 additionalProperties: true 32 124 33 125 ...
-46
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt
··· 1 - BCM2835 PM (Power domains, watchdog) 2 - 3 - The PM block controls power domains and some reset lines, and includes 4 - a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt 5 - binding which covered some of PM's register range and functionality. 6 - 7 - Required properties: 8 - 9 - - compatible: Should be "brcm,bcm2835-pm" 10 - - reg: Specifies base physical address and size of the two 11 - register ranges ("PM" and "ASYNC_BRIDGE" in that 12 - order) 13 - - clocks: a) v3d: The V3D clock from CPRMAN 14 - b) peri_image: The PERI_IMAGE clock from CPRMAN 15 - c) h264: The H264 clock from CPRMAN 16 - d) isp: The ISP clock from CPRMAN 17 - - #reset-cells: Should be 1. This property follows the reset controller 18 - bindings[1]. 19 - - #power-domain-cells: Should be 1. This property follows the power domain 20 - bindings[2]. 21 - 22 - Optional properties: 23 - 24 - - timeout-sec: Contains the watchdog timeout in seconds 25 - - system-power-controller: Whether the watchdog is controlling the 26 - system power. This node follows the power controller bindings[3]. 27 - 28 - [1] Documentation/devicetree/bindings/reset/reset.txt 29 - [2] Documentation/devicetree/bindings/power/power-domain.yaml 30 - [3] Documentation/devicetree/bindings/power/power-controller.txt 31 - 32 - Example: 33 - 34 - pm { 35 - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 36 - #power-domain-cells = <1>; 37 - #reset-cells = <1>; 38 - reg = <0x7e100000 0x114>, 39 - <0x7e00a000 0x24>; 40 - clocks = <&clocks BCM2835_CLOCK_V3D>, 41 - <&clocks BCM2835_CLOCK_PERI_IMAGE>, 42 - <&clocks BCM2835_CLOCK_H264>, 43 - <&clocks BCM2835_CLOCK_ISP>; 44 - clock-names = "v3d", "peri_image", "h264", "isp"; 45 - system-power-controller; 46 - };
+86
Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-pm.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: BCM2835 PM (Power domains, watchdog) 8 + 9 + description: | 10 + The PM block controls power domains and some reset lines, and includes a 11 + watchdog timer. 12 + 13 + maintainers: 14 + - Nicolas Saenz Julienne <nsaenz@kernel.org> 15 + 16 + allOf: 17 + - $ref: ../../watchdog/watchdog.yaml# 18 + 19 + properties: 20 + compatible: 21 + items: 22 + - enum: 23 + - brcm,bcm2835-pm 24 + - brcm,bcm2711-pm 25 + - const: brcm,bcm2835-pm-wdt 26 + 27 + reg: 28 + minItems: 2 29 + maxItems: 3 30 + 31 + reg-names: 32 + minItems: 2 33 + items: 34 + - const: pm 35 + - const: asb 36 + - const: rpivid_asb 37 + 38 + "#power-domain-cells": 39 + const: 1 40 + 41 + "#reset-cells": 42 + const: 1 43 + 44 + clocks: 45 + minItems: 4 46 + maxItems: 4 47 + 48 + clock-names: 49 + items: 50 + - const: v3d 51 + - const: peri_image 52 + - const: h264 53 + - const: isp 54 + 55 + system-power-controller: 56 + type: boolean 57 + 58 + timeout-sec: true 59 + 60 + required: 61 + - compatible 62 + - reg 63 + - "#power-domain-cells" 64 + - "#reset-cells" 65 + - clocks 66 + 67 + additionalProperties: false 68 + 69 + examples: 70 + - | 71 + #include <dt-bindings/clock/bcm2835.h> 72 + 73 + watchdog@7e100000 { 74 + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 75 + #power-domain-cells = <1>; 76 + #reset-cells = <1>; 77 + reg = <0x7e100000 0x114>, 78 + <0x7e00a000 0x24>; 79 + reg-names = "pm", "asb"; 80 + clocks = <&clocks BCM2835_CLOCK_V3D>, 81 + <&clocks BCM2835_CLOCK_PERI_IMAGE>, 82 + <&clocks BCM2835_CLOCK_H264>, 83 + <&clocks BCM2835_CLOCK_ISP>; 84 + clock-names = "v3d", "peri_image", "h264", "isp"; 85 + system-power-controller; 86 + };
+10 -3
arch/arm/boot/dts/Makefile
··· 135 135 bcm47094-luxul-xwr-3150-v1.dtb \ 136 136 bcm47094-netgear-r8500.dtb \ 137 137 bcm47094-phicomm-k3.dtb \ 138 + bcm53015-meraki-mr26.dtb \ 138 139 bcm53016-meraki-mr32.dtb \ 139 140 bcm94708.dtb \ 140 141 bcm94709.dtb \ ··· 147 146 bcm47189-luxul-xap-810.dtb \ 148 147 bcm47189-tenda-ac9.dtb \ 149 148 bcm947189acdbmr.dtb 150 - dtb-$(CONFIG_ARCH_BCM_63XX) += \ 151 - bcm963138dvt.dtb 152 149 dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ 153 150 bcm911360_entphn.dtb \ 154 151 bcm911360k.dtb \ ··· 181 182 dtb-$(CONFIG_ARCH_BRCMSTB) += \ 182 183 bcm7445-bcm97445svmb.dtb 183 184 dtb-$(CONFIG_ARCH_BCMBCA) += \ 184 - bcm947622.dtb 185 + bcm947622.dtb \ 186 + bcm963138.dtb \ 187 + bcm963138dvt.dtb \ 188 + bcm963148.dtb \ 189 + bcm963178.dtb \ 190 + bcm96756.dtb \ 191 + bcm96846.dtb \ 192 + bcm96855.dtb \ 193 + bcm96878.dtb 185 194 dtb-$(CONFIG_ARCH_CLPS711X) += \ 186 195 ep7211-edb7211.dtb 187 196 dtb-$(CONFIG_ARCH_DAVINCI) += \
+4
arch/arm/boot/dts/bcm2711-rpi.dtsi
··· 69 69 }; 70 70 }; 71 71 72 + &v3d { 73 + clocks = <&firmware_clocks 5>; 74 + }; 75 + 72 76 &vchiq { 73 77 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 74 78 };
+13 -1
arch/arm/boot/dts/bcm2711.dtsi
··· 107 107 }; 108 108 109 109 pm: watchdog@7e100000 { 110 - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 110 + compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; 111 111 #power-domain-cells = <1>; 112 112 #reset-cells = <1>; 113 113 reg = <0x7e100000 0x114>, 114 114 <0x7e00a000 0x24>, 115 115 <0x7ec11000 0x20>; 116 + reg-names = "pm", "asb", "rpivid_asb"; 116 117 clocks = <&clocks BCM2835_CLOCK_V3D>, 117 118 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 118 119 <&clocks BCM2835_CLOCK_H264>, ··· 601 600 #address-cells = <0x1>; 602 601 #size-cells = <0x0>; 603 602 }; 603 + }; 604 + 605 + v3d: gpu@7ec00000 { 606 + compatible = "brcm,2711-v3d"; 607 + reg = <0x0 0x7ec00000 0x4000>, 608 + <0x0 0x7ec04000 0x4000>; 609 + reg-names = "hub", "core0"; 610 + 611 + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 612 + resets = <&pm BCM2835_RESET_V3D>; 613 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 604 614 }; 605 615 }; 606 616 };
+4 -4
arch/arm/boot/dts/bcm28155-ap.dts
··· 31 31 }; 32 32 33 33 i2c@3e016000 { 34 - status="okay"; 34 + status = "okay"; 35 35 clock-frequency = <400000>; 36 36 }; 37 37 38 38 i2c@3e017000 { 39 - status="okay"; 39 + status = "okay"; 40 40 clock-frequency = <400000>; 41 41 }; 42 42 43 43 i2c@3e018000 { 44 - status="okay"; 44 + status = "okay"; 45 45 clock-frequency = <400000>; 46 46 }; 47 47 48 48 i2c@3500d000 { 49 - status="okay"; 49 + status = "okay"; 50 50 clock-frequency = <100000>; 51 51 52 52 pmu: pmu@8 {
+1
arch/arm/boot/dts/bcm2835-common.dtsi
··· 62 62 #reset-cells = <1>; 63 63 reg = <0x7e100000 0x114>, 64 64 <0x7e00a000 0x24>; 65 + reg-names = "pm", "asb"; 65 66 clocks = <&clocks BCM2835_CLOCK_V3D>, 66 67 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 67 68 <&clocks BCM2835_CLOCK_H264>,
+3 -5
arch/arm/boot/dts/bcm283x.dtsi
··· 50 50 51 51 trips { 52 52 cpu-crit { 53 - temperature = <90000>; 54 - hysteresis = <0>; 55 - type = "critical"; 53 + temperature = <90000>; 54 + hysteresis = <0>; 55 + type = "critical"; 56 56 }; 57 57 }; 58 58 ··· 352 352 clocks = <&clocks BCM2835_CLOCK_VPU>, 353 353 <&clocks BCM2835_CLOCK_DPI>; 354 354 clock-names = "core", "pixel"; 355 - #address-cells = <1>; 356 - #size-cells = <0>; 357 355 status = "disabled"; 358 356 }; 359 357
+3 -3
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
··· 70 70 gpio-keys { 71 71 compatible = "gpio-keys"; 72 72 73 - rfkill { 73 + button-rfkill { 74 74 label = "WiFi"; 75 75 linux,code = <KEY_RFKILL>; 76 76 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 77 77 }; 78 78 79 - restart { 79 + button-restart { 80 80 label = "Reset"; 81 81 linux,code = <KEY_RESTART>; 82 82 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 83 83 }; 84 84 85 - wps { 85 + button-wps { 86 86 label = "WPS"; 87 87 linux,code = <KEY_WPS_BUTTON>; 88 88 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+4 -4
arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
··· 54 54 gpio-keys { 55 55 compatible = "gpio-keys"; 56 56 57 - brightness { 57 + button-brightness { 58 58 label = "Backlight"; 59 59 linux,code = <KEY_BRIGHTNESS_ZERO>; 60 60 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; 61 61 }; 62 62 63 - wps { 63 + button-wps { 64 64 label = "WPS"; 65 65 linux,code = <KEY_WPS_BUTTON>; 66 66 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 67 67 }; 68 68 69 - restart { 69 + button-restart { 70 70 label = "Reset"; 71 71 linux,code = <KEY_RESTART>; 72 72 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 73 73 }; 74 74 75 - rfkill { 75 + button-rfkill { 76 76 label = "WiFi"; 77 77 linux,code = <KEY_RFKILL>; 78 78 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+5 -5
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
··· 104 104 gpio-keys { 105 105 compatible = "gpio-keys"; 106 106 107 - restart { 107 + button-restart { 108 108 label = "Reset"; 109 109 linux,code = <KEY_RESTART>; 110 110 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 111 111 }; 112 112 113 - aoss { 113 + button-aoss { 114 114 label = "AOSS"; 115 115 linux,code = <KEY_WPS_BUTTON>; 116 116 gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; 117 117 }; 118 118 119 119 /* Commit mode set by switch? */ 120 - mode { 120 + button-mode { 121 121 label = "Mode"; 122 122 linux,code = <KEY_SETUP>; 123 123 gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; 124 124 }; 125 125 126 126 /* Switch: AP mode */ 127 - sw_ap { 127 + button-sw-ap { 128 128 label = "AP"; 129 129 linux,code = <BTN_0>; 130 130 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; 131 131 }; 132 132 133 - eject { 133 + button-eject { 134 134 label = "USB eject"; 135 135 linux,code = <KEY_EJECTCD>; 136 136 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+5 -5
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
··· 100 100 gpio-keys { 101 101 compatible = "gpio-keys"; 102 102 103 - restart { 103 + button-restart { 104 104 label = "Reset"; 105 105 linux,code = <KEY_RESTART>; 106 106 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 107 107 }; 108 108 109 - aoss { 109 + button-aoss { 110 110 label = "AOSS"; 111 111 linux,code = <KEY_WPS_BUTTON>; 112 112 gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; 113 113 }; 114 114 115 115 /* Commit mode set by switch? */ 116 - mode { 116 + button-mode { 117 117 label = "Mode"; 118 118 linux,code = <KEY_SETUP>; 119 119 gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; 120 120 }; 121 121 122 122 /* Switch: AP mode */ 123 - sw_ap { 123 + button-sw-ap { 124 124 label = "AP"; 125 125 linux,code = <BTN_0>; 126 126 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; 127 127 }; 128 128 129 - eject { 129 + button-eject { 130 130 label = "USB eject"; 131 131 linux,code = <KEY_EJECTCD>; 132 132 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+2 -2
arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
··· 29 29 gpio-keys { 30 30 compatible = "gpio-keys"; 31 31 32 - wps { 32 + button-wps { 33 33 label = "WPS"; 34 34 linux,code = <KEY_WPS_BUTTON>; 35 35 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 36 36 }; 37 37 38 - restart { 38 + button-restart { 39 39 label = "Reset"; 40 40 linux,code = <KEY_RESTART>; 41 41 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+2 -2
arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
··· 25 25 gpio-keys { 26 26 compatible = "gpio-keys"; 27 27 28 - wps { 28 + button-wps { 29 29 label = "WPS"; 30 30 linux,code = <KEY_WPS_BUTTON>; 31 31 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 32 32 }; 33 33 34 - restart { 34 + button-restart { 35 35 label = "Reset"; 36 36 linux,code = <KEY_RESTART>; 37 37 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
··· 45 45 gpio-keys { 46 46 compatible = "gpio-keys"; 47 47 48 - restart { 48 + button-restart { 49 49 label = "Reset"; 50 50 linux,code = <KEY_RESTART>; 51 51 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
··· 52 52 gpio-keys { 53 53 compatible = "gpio-keys"; 54 54 55 - restart { 55 + button-restart { 56 56 label = "Reset"; 57 57 linux,code = <KEY_RESTART>; 58 58 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+3 -3
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
··· 63 63 gpio-keys { 64 64 compatible = "gpio-keys"; 65 65 66 - wps { 66 + button-wps { 67 67 label = "WPS"; 68 68 linux,code = <KEY_WPS_BUTTON>; 69 69 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; 70 70 }; 71 71 72 - rfkill { 72 + button-rfkill { 73 73 label = "WiFi"; 74 74 linux,code = <KEY_RFKILL>; 75 75 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; 76 76 }; 77 77 78 - restart { 78 + button-restart { 79 79 label = "Reset"; 80 80 linux,code = <KEY_RESTART>; 81 81 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+3 -3
arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
··· 59 59 gpio-keys { 60 60 compatible = "gpio-keys"; 61 61 62 - wps { 62 + button-wps { 63 63 label = "WPS"; 64 64 linux,code = <KEY_WPS_BUTTON>; 65 65 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; 66 66 }; 67 67 68 - rfkill { 68 + button-rfkill { 69 69 label = "WiFi"; 70 70 linux,code = <KEY_RFKILL>; 71 71 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; 72 72 }; 73 73 74 - restart { 74 + button-restart { 75 75 label = "Reset"; 76 76 linux,code = <KEY_RESTART>; 77 77 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+3 -3
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
··· 94 94 gpio-keys { 95 95 compatible = "gpio-keys"; 96 96 97 - rfkill { 97 + button-rfkill { 98 98 label = "WiFi"; 99 99 linux,code = <KEY_RFKILL>; 100 100 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; 101 101 }; 102 102 103 - wps { 103 + button-wps { 104 104 label = "WPS"; 105 105 linux,code = <KEY_WPS_BUTTON>; 106 106 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 107 107 }; 108 108 109 - restart { 109 + button-restart { 110 110 label = "Reset"; 111 111 linux,code = <KEY_RESTART>; 112 112 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+2 -2
arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
··· 60 60 gpio-keys { 61 61 compatible = "gpio-keys"; 62 62 63 - restart { 63 + button-restart { 64 64 label = "Reset"; 65 65 linux,code = <KEY_RESTART>; 66 66 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 67 67 }; 68 68 69 - wps { 69 + button-wps { 70 70 label = "WPS"; 71 71 linux,code = <KEY_WPS_BUTTON>; 72 72 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+4 -4
arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
··· 91 91 gpio-keys { 92 92 compatible = "gpio-keys"; 93 93 94 - aoss { 94 + button-aoss { 95 95 label = "AOSS"; 96 96 linux,code = <KEY_WPS_BUTTON>; 97 97 gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; 98 98 }; 99 99 100 - restart { 100 + button-restart { 101 101 label = "Reset"; 102 102 linux,code = <KEY_RESTART>; 103 103 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 104 104 }; 105 105 106 106 /* Switch device mode? */ 107 - mode { 107 + button-mode { 108 108 label = "Mode"; 109 109 linux,code = <KEY_SETUP>; 110 110 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; 111 111 }; 112 112 113 - eject { 113 + button-eject { 114 114 label = "USB eject"; 115 115 linux,code = <KEY_EJECTCD>; 116 116 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
··· 96 96 gpio-keys { 97 97 compatible = "gpio-keys"; 98 98 99 - restart { 99 + button-restart { 100 100 label = "Reset"; 101 101 linux,code = <KEY_RESTART>; 102 102 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
··· 45 45 gpio-keys { 46 46 compatible = "gpio-keys"; 47 47 48 - restart { 48 + button-restart { 49 49 label = "Reset"; 50 50 linux,code = <KEY_RESTART>; 51 51 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
··· 94 94 gpio-keys { 95 95 compatible = "gpio-keys"; 96 96 97 - restart { 97 + button-restart { 98 98 label = "Reset"; 99 99 linux,code = <KEY_RESTART>; 100 100 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+2 -4
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
··· 47 47 48 48 gpio-keys { 49 49 compatible = "gpio-keys"; 50 - #address-cells = <1>; 51 - #size-cells = <0>; 52 50 53 - wps { 51 + button-wps { 54 52 label = "WPS"; 55 53 linux,code = <KEY_WPS_BUTTON>; 56 54 gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; 57 55 }; 58 56 59 - restart { 57 + button-restart { 60 58 label = "Reset"; 61 59 linux,code = <KEY_RESTART>; 62 60 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+6 -8
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
··· 77 77 78 78 gpio-keys { 79 79 compatible = "gpio-keys"; 80 - #address-cells = <1>; 81 - #size-cells = <0>; 82 80 83 - power { 81 + button-power { 84 82 label = "Power"; 85 83 linux,code = <KEY_POWER>; 86 84 gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; 87 85 }; 88 86 89 - restart { 87 + button-restart { 90 88 label = "Reset"; 91 89 linux,code = <KEY_RESTART>; 92 90 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; 93 91 }; 94 92 95 - aoss { 93 + button-aoss { 96 94 label = "AOSS"; 97 95 linux,code = <KEY_WPS_BUTTON>; 98 96 gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; 99 97 }; 100 98 101 99 /* Commit mode set by switch? */ 102 - mode { 100 + button-mode { 103 101 label = "Mode"; 104 102 linux,code = <KEY_SETUP>; 105 103 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; 106 104 }; 107 105 108 106 /* Switch: AP mode */ 109 - sw_ap { 107 + button-sw-ap { 110 108 label = "AP"; 111 109 linux,code = <BTN_0>; 112 110 gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; 113 111 }; 114 112 115 - eject { 113 + button-eject { 116 114 label = "USB eject"; 117 115 linux,code = <KEY_EJECTCD>; 118 116 gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
+2 -4
arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
··· 29 29 30 30 gpio-keys { 31 31 compatible = "gpio-keys"; 32 - #address-cells = <1>; 33 - #size-cells = <0>; 34 32 35 - wps { 33 + button-wps { 36 34 label = "WPS"; 37 35 linux,code = <KEY_WPS_BUTTON>; 38 36 gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; 39 37 }; 40 38 41 - restart { 39 + button-restart { 42 40 label = "Reset"; 43 41 linux,code = <KEY_RESTART>; 44 42 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+3 -5
arch/arm/boot/dts/bcm4709-netgear-r7000.dts
··· 72 72 73 73 gpio-keys { 74 74 compatible = "gpio-keys"; 75 - #address-cells = <1>; 76 - #size-cells = <0>; 77 75 78 - wps { 76 + button-wps { 79 77 label = "WPS"; 80 78 linux,code = <KEY_WPS_BUTTON>; 81 79 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; 82 80 }; 83 81 84 - rfkill { 82 + button-rfkill { 85 83 label = "WiFi"; 86 84 linux,code = <KEY_RFKILL>; 87 85 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; 88 86 }; 89 87 90 - restart { 88 + button-restart { 91 89 label = "Reset"; 92 90 linux,code = <KEY_RESTART>; 93 91 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+4 -6
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
··· 99 99 100 100 gpio-keys { 101 101 compatible = "gpio-keys"; 102 - #address-cells = <1>; 103 - #size-cells = <0>; 104 102 105 - rfkill { 103 + button-rfkill { 106 104 label = "WiFi"; 107 105 linux,code = <KEY_RFKILL>; 108 106 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; 109 107 }; 110 108 111 - wps { 109 + button-wps { 112 110 label = "WPS"; 113 111 linux,code = <KEY_WPS_BUTTON>; 114 112 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; 115 113 }; 116 114 117 - restart { 115 + button-restart { 118 116 label = "Reset"; 119 117 linux,code = <KEY_RESTART>; 120 118 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; 121 119 }; 122 120 123 - brightness { 121 + button-brightness { 124 122 label = "Backlight"; 125 123 linux,code = <KEY_BRIGHTNESS_ZERO>; 126 124 gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+4 -4
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
··· 72 72 gpio-keys { 73 73 compatible = "gpio-keys"; 74 74 75 - wps { 75 + button-wps { 76 76 label = "WPS"; 77 77 linux,code = <KEY_WPS_BUTTON>; 78 78 gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; 79 79 }; 80 80 81 - reset { 81 + button-reset { 82 82 label = "Reset"; 83 83 linux,code = <KEY_RESTART>; 84 84 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 85 85 }; 86 86 87 - wifi { 87 + button-wifi { 88 88 label = "Wi-Fi"; 89 89 linux,code = <KEY_RFKILL>; 90 90 gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; 91 91 }; 92 92 93 - led { 93 + button-led { 94 94 label = "Backlight"; 95 95 linux,code = <KEY_BRIGHTNESS_ZERO>; 96 96 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+3 -3
arch/arm/boot/dts/bcm47094-linksys-panamera.dts
··· 30 30 gpio-keys { 31 31 compatible = "gpio-keys"; 32 32 33 - wps { 33 + button-wps { 34 34 label = "WPS"; 35 35 linux,code = <KEY_WPS_BUTTON>; 36 36 gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; 37 37 }; 38 38 39 - rfkill { 39 + button-rfkill { 40 40 label = "WiFi"; 41 41 linux,code = <KEY_RFKILL>; 42 42 gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; 43 43 }; 44 44 45 - reset { 45 + button-reset { 46 46 label = "Reset"; 47 47 linux,code = <KEY_RESTART>; 48 48 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
··· 49 49 gpio-keys { 50 50 compatible = "gpio-keys"; 51 51 52 - restart { 52 + button-restart { 53 53 label = "Reset"; 54 54 linux,code = <KEY_RESTART>; 55 55 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
··· 43 43 gpio-keys { 44 44 compatible = "gpio-keys"; 45 45 46 - restart { 46 + button-restart { 47 47 label = "Reset"; 48 48 linux,code = <KEY_RESTART>; 49 49 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
··· 49 49 gpio-keys { 50 50 compatible = "gpio-keys"; 51 51 52 - restart { 52 + button-restart { 53 53 label = "Reset"; 54 54 linux,code = <KEY_RESTART>; 55 55 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+1 -3
arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
··· 34 34 35 35 gpio-keys { 36 36 compatible = "gpio-keys"; 37 - #address-cells = <1>; 38 - #size-cells = <0>; 39 37 40 - restart { 38 + button-restart { 41 39 label = "Reset"; 42 40 linux,code = <KEY_RESTART>; 43 41 gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
··· 89 89 gpio-keys { 90 90 compatible = "gpio-keys"; 91 91 92 - restart { 92 + button-restart { 93 93 label = "Reset"; 94 94 linux,code = <KEY_RESTART>; 95 95 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
··· 67 67 gpio-keys { 68 68 compatible = "gpio-keys"; 69 69 70 - restart { 70 + button-restart { 71 71 label = "Reset"; 72 72 linux,code = <KEY_RESTART>; 73 73 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+4 -4
arch/arm/boot/dts/bcm47094-netgear-r8500.dts
··· 65 65 gpio-keys { 66 66 compatible = "gpio-keys"; 67 67 68 - brightness { 68 + button-brightness { 69 69 label = "Backlight"; 70 70 linux,code = <KEY_BRIGHTNESS_ZERO>; 71 71 gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; 72 72 }; 73 73 74 - restart { 74 + button-restart { 75 75 label = "Reset"; 76 76 linux,code = <KEY_RESTART>; 77 77 gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; 78 78 }; 79 79 80 - wps { 80 + button-wps { 81 81 label = "WPS"; 82 82 linux,code = <KEY_WPS_BUTTON>; 83 83 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; 84 84 }; 85 85 86 - rfkill { 86 + button-rfkill { 87 87 label = "WiFi"; 88 88 linux,code = <KEY_RFKILL>; 89 89 gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47094-phicomm-k3.dts
··· 22 22 gpio-keys { 23 23 compatible = "gpio-keys"; 24 24 25 - restart { 25 + button-restart { 26 26 label = "Reset"; 27 27 linux,code = <KEY_RESTART>; 28 28 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
··· 39 39 gpio-keys { 40 40 compatible = "gpio-keys"; 41 41 42 - restart { 42 + button-restart { 43 43 label = "Reset"; 44 44 linux,code = <KEY_RESTART>; 45 45 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
··· 49 49 gpio-keys { 50 50 compatible = "gpio-keys"; 51 51 52 - restart { 52 + button-restart { 53 53 label = "Reset"; 54 54 linux,code = <KEY_RESTART>; 55 55 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+3 -3
arch/arm/boot/dts/bcm47189-tenda-ac9.dts
··· 59 59 gpio-keys { 60 60 compatible = "gpio-keys"; 61 61 62 - rfkill { 62 + button-rfkill { 63 63 label = "WiFi"; 64 64 linux,code = <KEY_RFKILL>; 65 65 gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; 66 66 }; 67 67 68 - restart { 68 + button-restart { 69 69 label = "Reset"; 70 70 linux,code = <KEY_RESTART>; 71 71 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; 72 72 }; 73 73 74 - wps { 74 + button-wps { 75 75 label = "WPS"; 76 76 linux,code = <KEY_WPS_BUTTON>; 77 77 gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+9 -5
arch/arm/boot/dts/bcm47622.dtsi
··· 32 32 next-level-cache = <&L2_0>; 33 33 enable-method = "psci"; 34 34 }; 35 + 35 36 CA7_2: cpu@2 { 36 37 device_type = "cpu"; 37 38 compatible = "arm,cortex-a7"; ··· 40 39 next-level-cache = <&L2_0>; 41 40 enable-method = "psci"; 42 41 }; 42 + 43 43 CA7_3: cpu@3 { 44 44 device_type = "cpu"; 45 45 compatible = "arm,cortex-a7"; ··· 48 46 next-level-cache = <&L2_0>; 49 47 enable-method = "psci"; 50 48 }; 49 + 51 50 L2_0: l2-cache0 { 52 51 compatible = "cache"; 53 52 }; ··· 79 76 #clock-cells = <0>; 80 77 clock-frequency = <200000000>; 81 78 }; 79 + 82 80 uart_clk: uart-clk { 83 81 compatible = "fixed-factor-clock"; 84 82 #clock-cells = <0>; ··· 92 88 psci { 93 89 compatible = "arm,psci-0.2"; 94 90 method = "smc"; 95 - cpu_off = <1>; 96 - cpu_on = <2>; 97 91 }; 98 92 99 93 axi@81000000 { 100 94 compatible = "simple-bus"; 101 95 #address-cells = <1>; 102 96 #size-cells = <1>; 103 - ranges = <0 0x81000000 0x818000>; 97 + ranges = <0 0x81000000 0x8000>; 104 98 105 99 gic: interrupt-controller@1000 { 106 100 compatible = "arm,cortex-a7-gic"; 107 101 #interrupt-cells = <3>; 108 - #address-cells = <0>; 109 102 interrupt-controller; 103 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 104 reg = <0x1000 0x1000>, 111 - <0x2000 0x2000>; 105 + <0x2000 0x2000>, 106 + <0x4000 0x2000>, 107 + <0x6000 0x2000>; 112 108 }; 113 109 }; 114 110
+166
arch/arm/boot/dts/bcm53015-meraki-mr26.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Broadcom BCM470X / BCM5301X ARM platform code. 4 + * DTS for Meraki MR26 / Codename: Venom 5 + * 6 + * Copyright (C) 2022 Christian Lamparter <chunkeey@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "bcm4708.dtsi" 12 + #include "bcm5301x-nand-cs0-bch8.dtsi" 13 + #include <dt-bindings/leds/common.h> 14 + 15 + / { 16 + compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708"; 17 + model = "Meraki MR26"; 18 + 19 + memory@0 { 20 + reg = <0x00000000 0x08000000>; 21 + device_type = "memory"; 22 + }; 23 + 24 + leds { 25 + compatible = "gpio-leds"; 26 + 27 + led-0 { 28 + function = LED_FUNCTION_FAULT; 29 + color = <LED_COLOR_ID_AMBER>; 30 + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; 31 + panic-indicator; 32 + }; 33 + led-1 { 34 + function = LED_FUNCTION_INDICATOR; 35 + color = <LED_COLOR_ID_WHITE>; 36 + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; 37 + }; 38 + }; 39 + 40 + keys { 41 + compatible = "gpio-keys"; 42 + #address-cells = <1>; 43 + #size-cells = <0>; 44 + 45 + key-restart { 46 + label = "Reset"; 47 + linux,code = <KEY_RESTART>; 48 + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; 49 + }; 50 + }; 51 + }; 52 + 53 + &uart0 { 54 + clock-frequency = <50000000>; 55 + /delete-property/ clocks; 56 + }; 57 + 58 + &uart1 { 59 + status = "disabled"; 60 + }; 61 + 62 + &gmac0 { 63 + status = "okay"; 64 + }; 65 + 66 + &gmac1 { 67 + status = "disabled"; 68 + }; 69 + &gmac2 { 70 + status = "disabled"; 71 + }; 72 + &gmac3 { 73 + status = "disabled"; 74 + }; 75 + 76 + &nandcs { 77 + nand-ecc-algo = "hw"; 78 + 79 + partitions { 80 + compatible = "fixed-partitions"; 81 + #address-cells = <0x1>; 82 + #size-cells = <0x1>; 83 + 84 + partition@0 { 85 + label = "u-boot"; 86 + reg = <0x0 0x200000>; 87 + read-only; 88 + }; 89 + 90 + partition@200000 { 91 + label = "u-boot-env"; 92 + reg = <0x200000 0x200000>; 93 + /* empty */ 94 + }; 95 + 96 + partition@400000 { 97 + label = "u-boot-backup"; 98 + reg = <0x400000 0x200000>; 99 + /* empty */ 100 + }; 101 + 102 + partition@600000 { 103 + label = "u-boot-env-backup"; 104 + reg = <0x600000 0x200000>; 105 + /* empty */ 106 + }; 107 + 108 + partition@800000 { 109 + label = "ubi"; 110 + reg = <0x800000 0x7780000>; 111 + }; 112 + }; 113 + }; 114 + 115 + &srab { 116 + status = "okay"; 117 + 118 + ports { 119 + port@0 { 120 + reg = <0>; 121 + label = "poe"; 122 + }; 123 + 124 + port@5 { 125 + reg = <5>; 126 + label = "cpu"; 127 + ethernet = <&gmac0>; 128 + 129 + fixed-link { 130 + speed = <1000>; 131 + duplex-full; 132 + }; 133 + }; 134 + }; 135 + }; 136 + 137 + &i2c0 { 138 + status = "okay"; 139 + 140 + pinctrl-names = "default"; 141 + pinctrl-0 = <&pinmux_i2c>; 142 + 143 + clock-frequency = <100000>; 144 + 145 + ina219@40 { 146 + compatible = "ti,ina219"; /* PoE power */ 147 + reg = <0x40>; 148 + shunt-resistor = <60000>; /* = 60 mOhms */ 149 + }; 150 + 151 + eeprom@56 { 152 + compatible = "atmel,24c64"; 153 + reg = <0x56>; 154 + pagesize = <32>; 155 + read-only; 156 + #address-cells = <1>; 157 + #size-cells = <1>; 158 + 159 + /* it's empty */ 160 + }; 161 + }; 162 + 163 + &thermal { 164 + status = "disabled"; 165 + /* does not work, reads 418 degree Celsius */ 166 + };
+1 -3
arch/arm/boot/dts/bcm53016-meraki-mr32.dts
··· 47 47 48 48 keys { 49 49 compatible = "gpio-keys"; 50 - #address-cells = <1>; 51 - #size-cells = <0>; 52 50 53 - restart { 51 + button-restart { 54 52 label = "Reset"; 55 53 linux,code = <KEY_RESTART>; 56 54 gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
+3 -3
arch/arm/boot/dts/bcm5301x.dtsi
··· 568 568 569 569 trips { 570 570 cpu-crit { 571 - temperature = <125000>; 572 - hysteresis = <0>; 573 - type = "critical"; 571 + temperature = <125000>; 572 + hysteresis = <0>; 573 + type = "critical"; 574 574 }; 575 575 }; 576 576
+2 -2
arch/arm/boot/dts/bcm63138.dtsi
··· 9 9 / { 10 10 #address-cells = <1>; 11 11 #size-cells = <1>; 12 - compatible = "brcm,bcm63138"; 13 - model = "Broadcom BCM63138 DSL SoC"; 12 + compatible = "brcm,bcm63138", "brcm,bcmbca"; 13 + model = "Broadcom BCM963138 Reference Board"; 14 14 interrupt-parent = <&gic>; 15 15 16 16 aliases {
+103
arch/arm/boot/dts/bcm63148.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + 9 + / { 10 + compatible = "brcm,bcm63148", "brcm,bcmbca"; 11 + #address-cells = <1>; 12 + #size-cells = <1>; 13 + 14 + interrupt-parent = <&gic>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + B15_0: cpu@0 { 21 + device_type = "cpu"; 22 + compatible = "brcm,brahma-b15"; 23 + reg = <0x0>; 24 + next-level-cache = <&L2_0>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + B15_1: cpu@1 { 29 + device_type = "cpu"; 30 + compatible = "brcm,brahma-b15"; 31 + reg = <0x1>; 32 + next-level-cache = <&L2_0>; 33 + enable-method = "psci"; 34 + }; 35 + 36 + L2_0: l2-cache0 { 37 + compatible = "cache"; 38 + }; 39 + }; 40 + 41 + timer { 42 + compatible = "arm,armv7-timer"; 43 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 44 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 45 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 46 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 47 + }; 48 + 49 + pmu: pmu { 50 + compatible = "arm,cortex-a15-pmu"; 51 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 52 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 53 + interrupt-affinity = <&B15_0>, <&B15_1>; 54 + }; 55 + 56 + clocks: clocks { 57 + periph_clk: periph-clk { 58 + compatible = "fixed-clock"; 59 + #clock-cells = <0>; 60 + clock-frequency = <50000000>; 61 + }; 62 + }; 63 + 64 + psci { 65 + compatible = "arm,psci-0.2"; 66 + method = "smc"; 67 + }; 68 + 69 + axi@80030000 { 70 + compatible = "simple-bus"; 71 + #address-cells = <1>; 72 + #size-cells = <1>; 73 + ranges = <0 0x80030000 0x8000>; 74 + 75 + gic: interrupt-controller@1000 { 76 + compatible = "arm,cortex-a15-gic"; 77 + #interrupt-cells = <3>; 78 + interrupt-controller; 79 + reg = <0x1000 0x1000>, 80 + <0x2000 0x2000>, 81 + <0x4000 0x2000>, 82 + <0x6000 0x2000>; 83 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 84 + IRQ_TYPE_LEVEL_HIGH)>; 85 + }; 86 + }; 87 + 88 + bus@ff800000 { 89 + compatible = "simple-bus"; 90 + #address-cells = <1>; 91 + #size-cells = <1>; 92 + ranges = <0 0xfffe8000 0x8000>; 93 + 94 + uart0: serial@600 { 95 + compatible = "brcm,bcm6345-uart"; 96 + reg = <0x600 0x20>; 97 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 98 + clocks = <&periph_clk>; 99 + clock-names = "refclk"; 100 + status = "disabled"; 101 + }; 102 + }; 103 + };
+118
arch/arm/boot/dts/bcm63178.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + 9 + / { 10 + compatible = "brcm,bcm63178", "brcm,bcmbca"; 11 + #address-cells = <1>; 12 + #size-cells = <1>; 13 + 14 + interrupt-parent = <&gic>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + CA7_0: cpu@0 { 21 + device_type = "cpu"; 22 + compatible = "arm,cortex-a7"; 23 + reg = <0x0>; 24 + next-level-cache = <&L2_0>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + CA7_1: cpu@1 { 29 + device_type = "cpu"; 30 + compatible = "arm,cortex-a7"; 31 + reg = <0x1>; 32 + next-level-cache = <&L2_0>; 33 + enable-method = "psci"; 34 + }; 35 + CA7_2: cpu@2 { 36 + device_type = "cpu"; 37 + compatible = "arm,cortex-a7"; 38 + reg = <0x2>; 39 + next-level-cache = <&L2_0>; 40 + enable-method = "psci"; 41 + }; 42 + L2_0: l2-cache0 { 43 + compatible = "cache"; 44 + }; 45 + }; 46 + 47 + timer { 48 + compatible = "arm,armv7-timer"; 49 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 50 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 52 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 53 + arm,cpu-registers-not-fw-configured; 54 + }; 55 + 56 + pmu: pmu { 57 + compatible = "arm,cortex-a7-pmu"; 58 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 59 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 60 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 61 + interrupt-affinity = <&CA7_0>, <&CA7_1>, 62 + <&CA7_2>; 63 + }; 64 + 65 + clocks: clocks { 66 + periph_clk: periph-clk { 67 + compatible = "fixed-clock"; 68 + #clock-cells = <0>; 69 + clock-frequency = <200000000>; 70 + }; 71 + uart_clk: uart-clk { 72 + compatible = "fixed-factor-clock"; 73 + #clock-cells = <0>; 74 + clocks = <&periph_clk>; 75 + clock-div = <4>; 76 + clock-mult = <1>; 77 + }; 78 + }; 79 + 80 + psci { 81 + compatible = "arm,psci-0.2"; 82 + method = "smc"; 83 + cpu_off = <1>; 84 + cpu_on = <2>; 85 + }; 86 + 87 + axi@81000000 { 88 + compatible = "simple-bus"; 89 + #address-cells = <1>; 90 + #size-cells = <1>; 91 + ranges = <0 0x81000000 0x4000>; 92 + 93 + gic: interrupt-controller@1000 { 94 + compatible = "arm,cortex-a7-gic"; 95 + #interrupt-cells = <3>; 96 + #address-cells = <0>; 97 + interrupt-controller; 98 + reg = <0x1000 0x1000>, 99 + <0x2000 0x2000>; 100 + }; 101 + }; 102 + 103 + bus@ff800000 { 104 + compatible = "simple-bus"; 105 + #address-cells = <1>; 106 + #size-cells = <1>; 107 + ranges = <0 0xff800000 0x800000>; 108 + 109 + uart0: serial@12000 { 110 + compatible = "arm,pl011", "arm,primecell"; 111 + reg = <0x12000 0x1000>; 112 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 113 + clocks = <&uart_clk>, <&uart_clk>; 114 + clock-names = "uartclk", "apb_pclk"; 115 + status = "disabled"; 116 + }; 117 + }; 118 + };
+130
arch/arm/boot/dts/bcm6756.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + 9 + / { 10 + compatible = "brcm,bcm6756", "brcm,bcmbca"; 11 + #address-cells = <1>; 12 + #size-cells = <1>; 13 + 14 + interrupt-parent = <&gic>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + CA7_0: cpu@0 { 21 + device_type = "cpu"; 22 + compatible = "arm,cortex-a7"; 23 + reg = <0x0>; 24 + next-level-cache = <&L2_0>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + CA7_1: cpu@1 { 29 + device_type = "cpu"; 30 + compatible = "arm,cortex-a7"; 31 + reg = <0x1>; 32 + next-level-cache = <&L2_0>; 33 + enable-method = "psci"; 34 + }; 35 + 36 + CA7_2: cpu@2 { 37 + device_type = "cpu"; 38 + compatible = "arm,cortex-a7"; 39 + reg = <0x2>; 40 + next-level-cache = <&L2_0>; 41 + enable-method = "psci"; 42 + }; 43 + 44 + CA7_3: cpu@3 { 45 + device_type = "cpu"; 46 + compatible = "arm,cortex-a7"; 47 + reg = <0x3>; 48 + next-level-cache = <&L2_0>; 49 + enable-method = "psci"; 50 + }; 51 + 52 + L2_0: l2-cache0 { 53 + compatible = "cache"; 54 + }; 55 + }; 56 + 57 + timer { 58 + compatible = "arm,armv7-timer"; 59 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 63 + arm,cpu-registers-not-fw-configured; 64 + }; 65 + 66 + pmu: pmu { 67 + compatible = "arm,cortex-a7-pmu"; 68 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 69 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 70 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 71 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 72 + interrupt-affinity = <&CA7_0>, <&CA7_1>, 73 + <&CA7_2>, <&CA7_3>; 74 + }; 75 + 76 + clocks: clocks { 77 + periph_clk: periph-clk { 78 + compatible = "fixed-clock"; 79 + #clock-cells = <0>; 80 + clock-frequency = <200000000>; 81 + }; 82 + 83 + uart_clk: uart-clk { 84 + compatible = "fixed-factor-clock"; 85 + #clock-cells = <0>; 86 + clocks = <&periph_clk>; 87 + clock-div = <4>; 88 + clock-mult = <1>; 89 + }; 90 + }; 91 + 92 + psci { 93 + compatible = "arm,psci-0.2"; 94 + method = "smc"; 95 + }; 96 + 97 + axi@81000000 { 98 + compatible = "simple-bus"; 99 + #address-cells = <1>; 100 + #size-cells = <1>; 101 + ranges = <0 0x81000000 0x8000>; 102 + 103 + gic: interrupt-controller@1000 { 104 + compatible = "arm,cortex-a7-gic"; 105 + #interrupt-cells = <3>; 106 + interrupt-controller; 107 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 + reg = <0x1000 0x1000>, 109 + <0x2000 0x2000>, 110 + <0x4000 0x2000>, 111 + <0x6000 0x2000>; 112 + }; 113 + }; 114 + 115 + bus@ff800000 { 116 + compatible = "simple-bus"; 117 + #address-cells = <1>; 118 + #size-cells = <1>; 119 + ranges = <0 0xff800000 0x800000>; 120 + 121 + uart0: serial@12000 { 122 + compatible = "arm,pl011", "arm,primecell"; 123 + reg = <0x12000 0x1000>; 124 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 125 + clocks = <&uart_clk>, <&uart_clk>; 126 + clock-names = "uartclk", "apb_pclk"; 127 + status = "disabled"; 128 + }; 129 + }; 130 + };
+103
arch/arm/boot/dts/bcm6846.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + 9 + / { 10 + compatible = "brcm,bcm6846", "brcm,bcmbca"; 11 + #address-cells = <1>; 12 + #size-cells = <1>; 13 + 14 + interrupt-parent = <&gic>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + CA7_0: cpu@0 { 21 + device_type = "cpu"; 22 + compatible = "arm,cortex-a7"; 23 + reg = <0x0>; 24 + next-level-cache = <&L2_0>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + CA7_1: cpu@1 { 29 + device_type = "cpu"; 30 + compatible = "arm,cortex-a7"; 31 + reg = <0x1>; 32 + next-level-cache = <&L2_0>; 33 + enable-method = "psci"; 34 + }; 35 + 36 + L2_0: l2-cache0 { 37 + compatible = "cache"; 38 + }; 39 + }; 40 + 41 + timer { 42 + compatible = "arm,armv7-timer"; 43 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 44 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 45 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 46 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 47 + arm,cpu-registers-not-fw-configured; 48 + }; 49 + 50 + pmu: pmu { 51 + compatible = "arm,cortex-a7-pmu"; 52 + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 53 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 54 + interrupt-affinity = <&CA7_0>, <&CA7_1>; 55 + }; 56 + 57 + clocks: clocks { 58 + periph_clk: periph-clk { 59 + compatible = "fixed-clock"; 60 + #clock-cells = <0>; 61 + clock-frequency = <200000000>; 62 + }; 63 + }; 64 + 65 + psci { 66 + compatible = "arm,psci-0.2"; 67 + method = "smc"; 68 + cpu_off = <1>; 69 + cpu_on = <2>; 70 + }; 71 + 72 + axi@81000000 { 73 + compatible = "simple-bus"; 74 + #address-cells = <1>; 75 + #size-cells = <1>; 76 + ranges = <0 0x81000000 0x4000>; 77 + 78 + gic: interrupt-controller@1000 { 79 + compatible = "arm,cortex-a7-gic"; 80 + #interrupt-cells = <3>; 81 + #address-cells = <0>; 82 + interrupt-controller; 83 + reg = <0x1000 0x1000>, 84 + <0x2000 0x2000>; 85 + }; 86 + }; 87 + 88 + bus@ff800000 { 89 + compatible = "simple-bus"; 90 + #address-cells = <1>; 91 + #size-cells = <1>; 92 + ranges = <0 0xff800000 0x800000>; 93 + 94 + uart0: serial@640 { 95 + compatible = "brcm,bcm6345-uart"; 96 + reg = <0x640 0x1b>; 97 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 98 + clocks = <&periph_clk>; 99 + clock-names = "refclk"; 100 + status = "disabled"; 101 + }; 102 + }; 103 + };
+120
arch/arm/boot/dts/bcm6855.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + 9 + / { 10 + compatible = "brcm,bcm6855", "brcm,bcmbca"; 11 + #address-cells = <1>; 12 + #size-cells = <1>; 13 + 14 + interrupt-parent = <&gic>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + CA7_0: cpu@0 { 21 + device_type = "cpu"; 22 + compatible = "arm,cortex-a7"; 23 + reg = <0x0>; 24 + next-level-cache = <&L2_0>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + CA7_1: cpu@1 { 29 + device_type = "cpu"; 30 + compatible = "arm,cortex-a7"; 31 + reg = <0x1>; 32 + next-level-cache = <&L2_0>; 33 + enable-method = "psci"; 34 + }; 35 + 36 + CA7_2: cpu@2 { 37 + device_type = "cpu"; 38 + compatible = "arm,cortex-a7"; 39 + reg = <0x2>; 40 + next-level-cache = <&L2_0>; 41 + enable-method = "psci"; 42 + }; 43 + 44 + L2_0: l2-cache0 { 45 + compatible = "cache"; 46 + }; 47 + }; 48 + 49 + timer { 50 + compatible = "arm,armv7-timer"; 51 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 52 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 53 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 54 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; 55 + arm,cpu-registers-not-fw-configured; 56 + }; 57 + 58 + pmu: pmu { 59 + compatible = "arm,cortex-a7-pmu"; 60 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 61 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 62 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 63 + interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; 64 + }; 65 + 66 + clocks: clocks { 67 + periph_clk: periph-clk { 68 + compatible = "fixed-clock"; 69 + #clock-cells = <0>; 70 + clock-frequency = <200000000>; 71 + }; 72 + 73 + uart_clk: uart-clk { 74 + compatible = "fixed-factor-clock"; 75 + #clock-cells = <0>; 76 + clocks = <&periph_clk>; 77 + clock-div = <4>; 78 + clock-mult = <1>; 79 + }; 80 + }; 81 + 82 + psci { 83 + compatible = "arm,psci-0.2"; 84 + method = "smc"; 85 + }; 86 + 87 + axi@81000000 { 88 + compatible = "simple-bus"; 89 + #address-cells = <1>; 90 + #size-cells = <1>; 91 + ranges = <0 0x81000000 0x8000>; 92 + 93 + gic: interrupt-controller@1000 { 94 + compatible = "arm,cortex-a7-gic"; 95 + #interrupt-cells = <3>; 96 + interrupt-controller; 97 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; 98 + reg = <0x1000 0x1000>, 99 + <0x2000 0x2000>, 100 + <0x4000 0x2000>, 101 + <0x6000 0x2000>; 102 + }; 103 + }; 104 + 105 + bus@ff800000 { 106 + compatible = "simple-bus"; 107 + #address-cells = <1>; 108 + #size-cells = <1>; 109 + ranges = <0 0xff800000 0x800000>; 110 + 111 + uart0: serial@12000 { 112 + compatible = "arm,pl011", "arm,primecell"; 113 + reg = <0x12000 0x1000>; 114 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 115 + clocks = <&uart_clk>, <&uart_clk>; 116 + clock-names = "uartclk", "apb_pclk"; 117 + status = "disabled"; 118 + }; 119 + }; 120 + };
+110
arch/arm/boot/dts/bcm6878.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/arm-gic.h> 7 + #include <dt-bindings/interrupt-controller/irq.h> 8 + 9 + / { 10 + compatible = "brcm,bcm6878", "brcm,bcmbca"; 11 + #address-cells = <1>; 12 + #size-cells = <1>; 13 + 14 + interrupt-parent = <&gic>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + CA7_0: cpu@0 { 21 + device_type = "cpu"; 22 + compatible = "arm,cortex-a7"; 23 + reg = <0x0>; 24 + next-level-cache = <&L2_0>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + CA7_1: cpu@1 { 29 + device_type = "cpu"; 30 + compatible = "arm,cortex-a7"; 31 + reg = <0x1>; 32 + next-level-cache = <&L2_0>; 33 + enable-method = "psci"; 34 + }; 35 + L2_0: l2-cache0 { 36 + compatible = "cache"; 37 + }; 38 + }; 39 + 40 + timer { 41 + compatible = "arm,armv7-timer"; 42 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 44 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 45 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 46 + arm,cpu-registers-not-fw-configured; 47 + }; 48 + 49 + pmu: pmu { 50 + compatible = "arm,cortex-a7-pmu"; 51 + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 52 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 53 + interrupt-affinity = <&CA7_0>, <&CA7_1>; 54 + }; 55 + 56 + clocks: clocks { 57 + periph_clk: periph-clk { 58 + compatible = "fixed-clock"; 59 + #clock-cells = <0>; 60 + clock-frequency = <200000000>; 61 + }; 62 + uart_clk: uart-clk { 63 + compatible = "fixed-factor-clock"; 64 + #clock-cells = <0>; 65 + clocks = <&periph_clk>; 66 + clock-div = <4>; 67 + clock-mult = <1>; 68 + }; 69 + }; 70 + 71 + psci { 72 + compatible = "arm,psci-0.2"; 73 + method = "smc"; 74 + }; 75 + 76 + axi@81000000 { 77 + compatible = "simple-bus"; 78 + #address-cells = <1>; 79 + #size-cells = <1>; 80 + ranges = <0 0x81000000 0x8000>; 81 + 82 + gic: interrupt-controller@1000 { 83 + compatible = "arm,cortex-a7-gic"; 84 + #interrupt-cells = <3>; 85 + interrupt-controller; 86 + reg = <0x1000 0x1000>, 87 + <0x2000 0x2000>, 88 + <0x4000 0x2000>, 89 + <0x6000 0x2000>; 90 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 91 + IRQ_TYPE_LEVEL_HIGH)>; 92 + }; 93 + }; 94 + 95 + bus@ff800000 { 96 + compatible = "simple-bus"; 97 + #address-cells = <1>; 98 + #size-cells = <1>; 99 + ranges = <0 0xff800000 0x800000>; 100 + 101 + uart0: serial@12000 { 102 + compatible = "arm,pl011", "arm,primecell"; 103 + reg = <0x12000 0x1000>; 104 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 105 + clocks = <&uart_clk>, <&uart_clk>; 106 + clock-names = "uartclk", "apb_pclk"; 107 + status = "disabled"; 108 + }; 109 + }; 110 + };
+2 -2
arch/arm/boot/dts/bcm911360_entphn.dts
··· 47 47 stdout-path = "serial0:115200n8"; 48 48 }; 49 49 50 - gpio_keys { 50 + gpio-keys { 51 51 compatible = "gpio-keys"; 52 52 53 - hook { 53 + button-hook { 54 54 label = "HOOK"; 55 55 linux,code = <KEY_O>; 56 56 gpios = <&gpio_asiu 48 0>;
+2 -2
arch/arm/boot/dts/bcm947189acdbmr.dts
··· 44 44 gpio-keys { 45 45 compatible = "gpio-keys"; 46 46 47 - restart { 47 + button-restart { 48 48 label = "Reset"; 49 49 linux,code = <KEY_RESTART>; 50 50 gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; 51 51 }; 52 52 53 - wps { 53 + button-wps { 54 54 label = "WPS"; 55 55 linux,code = <KEY_WPS_BUTTON>; 56 56 gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+2 -2
arch/arm/boot/dts/bcm953012er.dts
··· 47 47 gpio-keys { 48 48 compatible = "gpio-keys"; 49 49 50 - wps { 50 + button-wps { 51 51 label = "WPS"; 52 52 linux,code = <KEY_WPS_BUTTON>; 53 53 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; 54 54 }; 55 55 56 - restart { 56 + button-restart { 57 57 label = "Reset"; 58 58 linux,code = <KEY_RESTART>; 59 59 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
··· 13 13 autorepeat; 14 14 poll-interval = <20>; 15 15 16 - reset { 16 + button-reset { 17 17 label = "reset"; 18 18 linux,code = <KEY_RESTART>; 19 19 gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+1 -1
arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
··· 14 14 autorepeat; 15 15 poll-interval = <20>; 16 16 17 - reset { 17 + button-reset { 18 18 label = "reset"; 19 19 linux,code = <KEY_RESTART>; 20 20 gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
+27
arch/arm/boot/dts/bcm963138.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm63138.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM963138 Reference Board"; 12 + compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; 13 + 14 + chosen { 15 + bootargs = "console=ttyS0,115200"; 16 + stdout-path = &serial0; 17 + }; 18 + 19 + memory@0 { 20 + device_type = "memory"; 21 + reg = <0x0 0x08000000>; 22 + }; 23 + }; 24 + 25 + &serial0 { 26 + status = "okay"; 27 + };
+1 -1
arch/arm/boot/dts/bcm963138dvt.dts
··· 8 8 #include "bcm63138.dtsi" 9 9 10 10 / { 11 - compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; 11 + compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca"; 12 12 model = "Broadcom BCM963138DVT"; 13 13 14 14 chosen {
+30
arch/arm/boot/dts/bcm963148.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm63148.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM963148 Reference Board"; 12 + compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; 13 + 14 + aliases { 15 + serial0 = &uart0; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial0:115200n8"; 20 + }; 21 + 22 + memory@0 { 23 + device_type = "memory"; 24 + reg = <0x0 0x08000000>; 25 + }; 26 + }; 27 + 28 + &uart0 { 29 + status = "okay"; 30 + };
+30
arch/arm/boot/dts/bcm963178.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm63178.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM963178 Reference Board"; 12 + compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; 13 + 14 + aliases { 15 + serial0 = &uart0; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial0:115200n8"; 20 + }; 21 + 22 + memory@0 { 23 + device_type = "memory"; 24 + reg = <0x0 0x08000000>; 25 + }; 26 + }; 27 + 28 + &uart0 { 29 + status = "okay"; 30 + };
+30
arch/arm/boot/dts/bcm96756.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm6756.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM96756 Reference Board"; 12 + compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; 13 + 14 + aliases { 15 + serial0 = &uart0; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial0:115200n8"; 20 + }; 21 + 22 + memory@0 { 23 + device_type = "memory"; 24 + reg = <0x0 0x08000000>; 25 + }; 26 + }; 27 + 28 + &uart0 { 29 + status = "okay"; 30 + };
+30
arch/arm/boot/dts/bcm96846.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm6846.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM96846 Reference Board"; 12 + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; 13 + 14 + aliases { 15 + serial0 = &uart0; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial0:115200n8"; 20 + }; 21 + 22 + memory@0 { 23 + device_type = "memory"; 24 + reg = <0x0 0x08000000>; 25 + }; 26 + }; 27 + 28 + &uart0 { 29 + status = "okay"; 30 + };
+30
arch/arm/boot/dts/bcm96855.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm6855.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM96855 Reference Board"; 12 + compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; 13 + 14 + aliases { 15 + serial0 = &uart0; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial0:115200n8"; 20 + }; 21 + 22 + memory@0 { 23 + device_type = "memory"; 24 + reg = <0x0 0x08000000>; 25 + }; 26 + }; 27 + 28 + &uart0 { 29 + status = "okay"; 30 + };
+30
arch/arm/boot/dts/bcm96878.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2019 Broadcom Ltd. 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "bcm6878.dtsi" 9 + 10 + / { 11 + model = "Broadcom BCM96878 Reference Board"; 12 + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; 13 + 14 + aliases { 15 + serial0 = &uart0; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial0:115200n8"; 20 + }; 21 + 22 + memory@0 { 23 + device_type = "memory"; 24 + reg = <0x0 0x08000000>; 25 + }; 26 + }; 27 + 28 + &uart0 { 29 + status = "okay"; 30 + };