tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull more ACPI updates from Rafael Wysocki:
"Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk
driver and the Designware i2c driver (changes from Akshu Agrawal and
Pu Wen)"
* tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
clk: x86: Support RV architecture
ACPI: APD: Add a fmw property is_raven
clk: x86: Change name from ST to FCH
ACPI: APD: Change name from ST to FCH
i2c: designware: Add device HID for Hygon I2C controller
+121
-91
+12
-7
drivers/acpi/acpi_apd.c
+12
-7
drivers/acpi/acpi_apd.c
···
8
8
*/
9
9
10
10
#include <linux/clk-provider.h>
11
-
#include <linux/platform_data/clk-st.h>
11
+
#include <linux/platform_data/clk-fch.h>
12
12
#include <linux/platform_device.h>
13
13
#include <linux/pm_domain.h>
14
14
#include <linux/clkdev.h>
···
79
79
return !acpi_dev_resource_memory(ares, &res);
80
80
}
81
81
82
-
static int st_misc_setup(struct apd_private_data *pdata)
82
+
static int fch_misc_setup(struct apd_private_data *pdata)
83
83
{
84
84
struct acpi_device *adev = pdata->adev;
85
+
const union acpi_object *obj;
85
86
struct platform_device *clkdev;
86
-
struct st_clk_data *clk_data;
87
+
struct fch_clk_data *clk_data;
87
88
struct resource_entry *rentry;
88
89
struct list_head resource_list;
89
90
int ret;
···
99
98
if (ret < 0)
100
99
return -ENOENT;
101
100
101
+
acpi_dev_get_property(adev, "is-rv", ACPI_TYPE_INTEGER, &obj);
102
+
clk_data->is_rv = obj->integer.value;
103
+
102
104
list_for_each_entry(rentry, &resource_list, node) {
103
105
clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
104
106
resource_size(rentry->res));
···
110
106
111
107
acpi_dev_free_resource_list(&resource_list);
112
108
113
-
clkdev = platform_device_register_data(&adev->dev, "clk-st",
109
+
clkdev = platform_device_register_data(&adev->dev, "clk-fch",
114
110
PLATFORM_DEVID_NONE, clk_data,
115
111
sizeof(*clk_data));
116
112
return PTR_ERR_OR_ZERO(clkdev);
···
139
135
.properties = uart_properties,
140
136
};
141
137
142
-
static const struct apd_device_desc st_misc_desc = {
143
-
.setup = st_misc_setup,
138
+
static const struct apd_device_desc fch_misc_desc = {
139
+
.setup = fch_misc_setup,
144
140
};
145
141
#endif
146
142
···
243
239
{ "AMD0020", APD_ADDR(cz_uart_desc) },
244
240
{ "AMDI0020", APD_ADDR(cz_uart_desc) },
245
241
{ "AMD0030", },
246
-
{ "AMD0040", APD_ADDR(st_misc_desc)},
242
+
{ "AMD0040", APD_ADDR(fch_misc_desc)},
243
+
{ "HYGO0010", APD_ADDR(wt_i2c_desc) },
247
244
#endif
248
245
#ifdef CONFIG_ARM64
249
246
{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
+1
-1
drivers/clk/x86/Makefile
+1
-1
drivers/clk/x86/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0-only
2
2
obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o
3
-
obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-st.o
3
+
obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-fch.o
4
4
clk-x86-lpss-objs := clk-lpt.o
5
5
obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
6
6
obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
+101
drivers/clk/x86/clk-fch.c
+101
drivers/clk/x86/clk-fch.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* clock framework for AMD Stoney based clocks
4
+
*
5
+
* Copyright 2018 Advanced Micro Devices, Inc.
6
+
*/
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/clkdev.h>
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/platform_data/clk-fch.h>
12
+
#include <linux/platform_device.h>
13
+
14
+
/* Clock Driving Strength 2 register */
15
+
#define CLKDRVSTR2 0x28
16
+
/* Clock Control 1 register */
17
+
#define MISCCLKCNTL1 0x40
18
+
/* Auxiliary clock1 enable bit */
19
+
#define OSCCLKENB 2
20
+
/* 25Mhz auxiliary output clock freq bit */
21
+
#define OSCOUT1CLK25MHZ 16
22
+
23
+
#define ST_CLK_48M 0
24
+
#define ST_CLK_25M 1
25
+
#define ST_CLK_MUX 2
26
+
#define ST_CLK_GATE 3
27
+
#define ST_MAX_CLKS 4
28
+
29
+
#define RV_CLK_48M 0
30
+
#define RV_CLK_GATE 1
31
+
#define RV_MAX_CLKS 2
32
+
33
+
static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
34
+
static struct clk_hw *hws[ST_MAX_CLKS];
35
+
36
+
static int fch_clk_probe(struct platform_device *pdev)
37
+
{
38
+
struct fch_clk_data *fch_data;
39
+
40
+
fch_data = dev_get_platdata(&pdev->dev);
41
+
if (!fch_data || !fch_data->base)
42
+
return -EINVAL;
43
+
44
+
if (!fch_data->is_rv) {
45
+
hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
46
+
NULL, 0, 48000000);
47
+
hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
48
+
NULL, 0, 25000000);
49
+
50
+
hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
51
+
clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
52
+
0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
53
+
NULL);
54
+
55
+
clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
56
+
57
+
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
58
+
"oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,
59
+
OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
60
+
61
+
devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
62
+
"oscout1", NULL);
63
+
} else {
64
+
hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
65
+
NULL, 0, 48000000);
66
+
67
+
hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
68
+
"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
69
+
OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
70
+
71
+
devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],
72
+
"oscout1", NULL);
73
+
}
74
+
75
+
return 0;
76
+
}
77
+
78
+
static int fch_clk_remove(struct platform_device *pdev)
79
+
{
80
+
int i, clks;
81
+
struct fch_clk_data *fch_data;
82
+
83
+
fch_data = dev_get_platdata(&pdev->dev);
84
+
85
+
clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;
86
+
87
+
for (i = 0; i < clks; i++)
88
+
clk_hw_unregister(hws[i]);
89
+
90
+
return 0;
91
+
}
92
+
93
+
static struct platform_driver fch_clk_driver = {
94
+
.driver = {
95
+
.name = "clk-fch",
96
+
.suppress_bind_attrs = true,
97
+
},
98
+
.probe = fch_clk_probe,
99
+
.remove = fch_clk_remove,
100
+
};
101
+
builtin_platform_driver(fch_clk_driver);
-78
drivers/clk/x86/clk-st.c
-78
drivers/clk/x86/clk-st.c
···
1
-
// SPDX-License-Identifier: MIT
2
-
/*
3
-
* clock framework for AMD Stoney based clocks
4
-
*
5
-
* Copyright 2018 Advanced Micro Devices, Inc.
6
-
*/
7
-
8
-
#include <linux/clk.h>
9
-
#include <linux/clkdev.h>
10
-
#include <linux/clk-provider.h>
11
-
#include <linux/platform_data/clk-st.h>
12
-
#include <linux/platform_device.h>
13
-
14
-
/* Clock Driving Strength 2 register */
15
-
#define CLKDRVSTR2 0x28
16
-
/* Clock Control 1 register */
17
-
#define MISCCLKCNTL1 0x40
18
-
/* Auxiliary clock1 enable bit */
19
-
#define OSCCLKENB 2
20
-
/* 25Mhz auxiliary output clock freq bit */
21
-
#define OSCOUT1CLK25MHZ 16
22
-
23
-
#define ST_CLK_48M 0
24
-
#define ST_CLK_25M 1
25
-
#define ST_CLK_MUX 2
26
-
#define ST_CLK_GATE 3
27
-
#define ST_MAX_CLKS 4
28
-
29
-
static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
30
-
static struct clk_hw *hws[ST_MAX_CLKS];
31
-
32
-
static int st_clk_probe(struct platform_device *pdev)
33
-
{
34
-
struct st_clk_data *st_data;
35
-
36
-
st_data = dev_get_platdata(&pdev->dev);
37
-
if (!st_data || !st_data->base)
38
-
return -EINVAL;
39
-
40
-
hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
41
-
48000000);
42
-
hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
43
-
25000000);
44
-
45
-
hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
46
-
clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
47
-
0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
48
-
49
-
clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
50
-
51
-
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
52
-
0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
53
-
CLK_GATE_SET_TO_DISABLE, NULL);
54
-
55
-
devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1",
56
-
NULL);
57
-
58
-
return 0;
59
-
}
60
-
61
-
static int st_clk_remove(struct platform_device *pdev)
62
-
{
63
-
int i;
64
-
65
-
for (i = 0; i < ST_MAX_CLKS; i++)
66
-
clk_hw_unregister(hws[i]);
67
-
return 0;
68
-
}
69
-
70
-
static struct platform_driver st_clk_driver = {
71
-
.driver = {
72
-
.name = "clk-st",
73
-
.suppress_bind_attrs = true,
74
-
},
75
-
.probe = st_clk_probe,
76
-
.remove = st_clk_remove,
77
-
};
78
-
builtin_platform_driver(st_clk_driver);
+1
drivers/i2c/busses/i2c-designware-platdrv.c
+1
drivers/i2c/busses/i2c-designware-platdrv.c
+6
-5
include/linux/platform_data/clk-st.h
include/linux/platform_data/clk-fch.h
+6
-5
include/linux/platform_data/clk-st.h
include/linux/platform_data/clk-fch.h
···
1
1
/* SPDX-License-Identifier: MIT */
2
2
/*
3
-
* clock framework for AMD Stoney based clock
3
+
* clock framework for AMD misc clocks
4
4
*
5
5
* Copyright 2018 Advanced Micro Devices, Inc.
6
6
*/
7
7
8
-
#ifndef __CLK_ST_H
9
-
#define __CLK_ST_H
8
+
#ifndef __CLK_FCH_H
9
+
#define __CLK_FCH_H
10
10
11
11
#include <linux/compiler.h>
12
12
13
-
struct st_clk_data {
13
+
struct fch_clk_data {
14
14
void __iomem *base;
15
+
u32 is_rv;
15
16
};
16
17
17
-
#endif /* __CLK_ST_H */
18
+
#endif /* __CLK_FCH_H */