tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into master
Pull spi fixes from Mark Brown:
"A couple of small driver specific fixes for fairly minor issues"
* tag 'spi-fix-v5.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spi-sun6i: sun6i_spi_transfer_one(): fix setting of clock rate
spi: mediatek: use correct SPI_CFG2_REG MACRO
+14
-15
+8
-7
drivers/spi/spi-mt65xx.c
+8
-7
drivers/spi/spi-mt65xx.c
···
36
36
#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
38
38
#define SPI_CFG0_CS_SETUP_OFFSET 24
39
-
#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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40
#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
42
41
···
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51
+
#define SPI_CFG2_SCK_HIGH_OFFSET 0
52
+
#define SPI_CFG2_SCK_LOW_OFFSET 16
50
53
51
54
#define SPI_CMD_ACT BIT(0)
52
55
#define SPI_CMD_RESUME BIT(1)
···
284
283
static void mtk_spi_prepare_transfer(struct spi_master *master,
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284
struct spi_transfer *xfer)
286
285
{
287
-
u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
286
+
u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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spi_clk_hz = clk_get_rate(mdata->spi_clk);
···
297
296
cs_time = sck_time * 2;
298
297
299
298
if (mdata->dev_comp->enhance_timing) {
299
+
reg_val = (((sck_time - 1) & 0xffff)
300
+
<< SPI_CFG2_SCK_HIGH_OFFSET);
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301
reg_val |= (((sck_time - 1) & 0xffff)
301
-
<< SPI_CFG0_SCK_HIGH_OFFSET);
302
-
reg_val |= (((sck_time - 1) & 0xffff)
303
-
<< SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
302
+
<< SPI_CFG2_SCK_LOW_OFFSET);
304
303
writel(reg_val, mdata->base + SPI_CFG2_REG);
305
-
reg_val |= (((cs_time - 1) & 0xffff)
304
+
reg_val = (((cs_time - 1) & 0xffff)
306
305
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
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306
reg_val |= (((cs_time - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
309
308
writel(reg_val, mdata->base + SPI_CFG0_REG);
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} else {
311
-
reg_val |= (((sck_time - 1) & 0xff)
310
+
reg_val = (((sck_time - 1) & 0xff)
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<< SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
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reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
+6
-8
drivers/spi/spi-sun6i.c
+6
-8
drivers/spi/spi-sun6i.c
···
198
198
struct spi_transfer *tfr)
199
199
{
200
200
struct sun6i_spi *sspi = spi_master_get_devdata(master);
201
-
unsigned int mclk_rate, div, timeout;
201
+
unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
202
202
unsigned int start, end, tx_time;
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unsigned int trig_level;
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unsigned int tx_len = 0;
···
287
287
* First try CDR2, and if we can't reach the expected
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* frequency, fall back to CDR1.
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*/
290
-
div = mclk_rate / (2 * tfr->speed_hz);
291
-
if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
292
-
if (div > 0)
293
-
div--;
294
-
295
-
reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
290
+
div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
291
+
div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
292
+
if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
293
+
reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
296
294
} else {
297
-
div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
295
+
div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
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reg = SUN6I_CLK_CTL_CDR1(div);
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}
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298