tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
"New Support:

- Qualcomm SM8650 UFS, PCIe and USB/DP Combo PHY, eUSB2 PHY, SDX75
USB3, X1E80100 USB3 support

- Mediatek MT8195 support

- Rockchip RK3128 usb2 support

- TI SGMII mode for J784S4

Updates:

- Qualcomm v7 register offsets updates

- Mediatek tphy support for force phy mode switch"

* tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (34 commits)
phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4
phy: ti: gmii-sel: Enable SGMII mode for J784S4
phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support
dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding
phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible
dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible
phy: mediatek: tphy: add support force phy mode switch
dt-bindings: phy: mediatek: tphy: add a property for force-mode switch
phy: phy-can-transceiver: insert space after include
phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header
phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY
phy: qcom-qmp: qserdes-txrx: Add v7 register offsets
phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets
phy: qcom-qmp: qserdes-com: Add v7 register offsets
phy: qcom-qmp: pcs-usb: Add v7 register offsets
phy: qcom-qmp: pcs: Add v7 register offsets
phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
...

Linus Torvalds 33a9caa4 4d5d604c

+1168 -78
-12
Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
··· 16 16 "#phy-cells": 17 17 const: 0 18 18 19 - reg: 20 - maxItems: 1 21 - 22 19 required: 23 20 - compatible 24 - - reg 25 21 - "#phy-cells" 26 22 27 23 additionalProperties: false 28 - 29 - examples: 30 - - | 31 - phy@0 { 32 - compatible = "amlogic,g12a-mipi-dphy-analog"; 33 - reg = <0x0 0xc>; 34 - #phy-cells = <0>; 35 - };
-17
Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
··· 9 9 maintainers: 10 10 - Remi Pommarel <repk@triplefau.lt> 11 11 12 - description: |+ 13 - The Everything-Else Power Domains node should be the child of a syscon 14 - node with the required property: 15 - 16 - - compatible: Should be the following: 17 - "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon" 18 - 19 - Refer to the bindings described in 20 - Documentation/devicetree/bindings/mfd/syscon.yaml 21 - 22 12 properties: 23 13 compatible: 24 14 const: amlogic,axg-mipi-pcie-analog-phy ··· 21 31 - "#phy-cells" 22 32 23 33 additionalProperties: false 24 - 25 - examples: 26 - - | 27 - mpphy: phy { 28 - compatible = "amlogic,axg-mipi-pcie-analog-phy"; 29 - #phy-cells = <0>; 30 - };
+1
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
··· 31 31 - items: 32 32 - enum: 33 33 - mediatek,mt8188-mipi-tx 34 + - mediatek,mt8195-mipi-tx 34 35 - mediatek,mt8365-mipi-tx 35 36 - const: mediatek,mt8183-mipi-tx 36 37 - const: mediatek,mt2701-mipi-tx
+9
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
··· 235 235 Specify the flag to enable BC1.2 if support it 236 236 type: boolean 237 237 238 + mediatek,force-mode: 239 + description: 240 + The force mode is used to manually switch the shared phy mode between 241 + USB3 and PCIe, when USB3 phy type is selected by the consumer, and 242 + force-mode is set, will cause phy's power and pipe toggled and force 243 + phy as USB3 mode which switched from default PCIe mode. But perfer to 244 + use the property "mediatek,syscon-type" for newer SoCs that support it. 245 + type: boolean 246 + 238 247 mediatek,syscon-type: 239 248 $ref: /schemas/types.yaml#/definitions/phandle-array 240 249 maxItems: 1
+5
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
··· 36 36 - qcom,sm8450-qmp-gen4x2-pcie-phy 37 37 - qcom,sm8550-qmp-gen3x2-pcie-phy 38 38 - qcom,sm8550-qmp-gen4x2-pcie-phy 39 + - qcom,sm8650-qmp-gen3x2-pcie-phy 40 + - qcom,sm8650-qmp-gen4x2-pcie-phy 39 41 40 42 reg: 41 43 minItems: 1 ··· 149 147 - qcom,sm8450-qmp-gen3x2-pcie-phy 150 148 - qcom,sm8550-qmp-gen3x2-pcie-phy 151 149 - qcom,sm8550-qmp-gen4x2-pcie-phy 150 + - qcom,sm8650-qmp-gen3x2-pcie-phy 151 + - qcom,sm8650-qmp-gen4x2-pcie-phy 152 152 then: 153 153 properties: 154 154 clocks: ··· 193 189 contains: 194 190 enum: 195 191 - qcom,sm8550-qmp-gen4x2-pcie-phy 192 + - qcom,sm8650-qmp-gen4x2-pcie-phy 196 193 then: 197 194 properties: 198 195 resets:
+2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
··· 32 32 - qcom,sm8350-qmp-ufs-phy 33 33 - qcom,sm8450-qmp-ufs-phy 34 34 - qcom,sm8550-qmp-ufs-phy 35 + - qcom,sm8650-qmp-ufs-phy 35 36 36 37 reg: 37 38 maxItems: 1 ··· 113 112 - qcom,sm8250-qmp-ufs-phy 114 113 - qcom,sm8350-qmp-ufs-phy 115 114 - qcom,sm8550-qmp-ufs-phy 115 + - qcom,sm8650-qmp-ufs-phy 116 116 then: 117 117 properties: 118 118 clocks:
+3
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
··· 32 32 - qcom,sm8150-qmp-usb3-uni-phy 33 33 - qcom,sm8250-qmp-usb3-uni-phy 34 34 - qcom,sm8350-qmp-usb3-uni-phy 35 + - qcom,x1e80100-qmp-usb3-uni-phy 35 36 36 37 37 38 reg: ··· 136 135 - qcom,sm8150-qmp-usb3-uni-phy 137 136 - qcom,sm8250-qmp-usb3-uni-phy 138 137 - qcom,sm8350-qmp-usb3-uni-phy 138 + - qcom,x1e80100-qmp-usb3-uni-phy 139 139 then: 140 140 properties: 141 141 clocks: ··· 173 171 enum: 174 172 - qcom,sa8775p-qmp-usb3-uni-phy 175 173 - qcom,sc8280xp-qmp-usb3-uni-phy 174 + - qcom,x1e80100-qmp-usb3-uni-phy 176 175 then: 177 176 required: 178 177 - power-domains
+6 -2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
··· 27 27 - qcom,sm8350-qmp-usb3-dp-phy 28 28 - qcom,sm8450-qmp-usb3-dp-phy 29 29 - qcom,sm8550-qmp-usb3-dp-phy 30 + - qcom,sm8650-qmp-usb3-dp-phy 31 + - qcom,x1e80100-qmp-usb3-dp-phy 30 32 31 33 reg: 32 34 maxItems: 1 ··· 64 62 "#clock-cells": 65 63 const: 1 66 64 description: 67 - See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h 65 + See include/dt-bindings/phy/phy-qcom-qmp.h 68 66 69 67 "#phy-cells": 70 68 const: 1 71 69 description: 72 - See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h 70 + See include/dt-bindings/phy/phy-qcom-qmp.h 73 71 74 72 orientation-switch: 75 73 description: ··· 130 128 - qcom,sc8280xp-qmp-usb43dp-phy 131 129 - qcom,sm6350-qmp-usb3-dp-phy 132 130 - qcom,sm8550-qmp-usb3-dp-phy 131 + - qcom,sm8650-qmp-usb3-dp-phy 132 + - qcom,x1e80100-qmp-usb3-dp-phy 133 133 then: 134 134 required: 135 135 - power-domains
+2
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
··· 18 18 - items: 19 19 - enum: 20 20 - qcom,sdx75-snps-eusb2-phy 21 + - qcom,sm8650-snps-eusb2-phy 22 + - qcom,x1e80100-snps-eusb2-phy 21 23 - const: qcom,sm8550-snps-eusb2-phy 22 24 - const: qcom,sm8550-snps-eusb2-phy 23 25
+25
drivers/phy/mediatek/phy-mtk-tphy.c
··· 185 185 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 186 186 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 187 187 188 + #define U3P_U3_PHYD_TOP1 0x100 189 + #define P3D_RG_PHY_MODE GENMASK(2, 1) 190 + #define P3D_RG_FORCE_PHY_MODE BIT(0) 191 + 188 192 #define U3P_U3_PHYD_RXDET1 0x128 189 193 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 190 194 ··· 331 327 int discth; 332 328 int pre_emphasis; 333 329 bool bc12_en; 330 + bool type_force_mode; 334 331 }; 335 332 336 333 struct mtk_tphy { ··· 773 768 void __iomem *phya = u3_banks->phya; 774 769 void __iomem *phyd = u3_banks->phyd; 775 770 771 + if (instance->type_force_mode) { 772 + /* force phy as usb mode, default is pcie rc mode */ 773 + mtk_phy_update_field(phyd + U3P_U3_PHYD_TOP1, P3D_RG_PHY_MODE, 1); 774 + mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE); 775 + /* power down phy by ip and pipe reset */ 776 + mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, 777 + P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN); 778 + mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, 779 + P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN); 780 + udelay(10); 781 + /* power on phy again */ 782 + mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, 783 + P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN); 784 + mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, 785 + P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN); 786 + } 787 + 776 788 /* gating PCIe Analog XTAL clock */ 777 789 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, 778 790 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); ··· 1141 1119 struct mtk_phy_instance *instance) 1142 1120 { 1143 1121 struct device *dev = &instance->phy->dev; 1122 + 1123 + if (instance->type == PHY_TYPE_USB3) 1124 + instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode"); 1144 1125 1145 1126 if (instance->type != PHY_TYPE_USB2) 1146 1127 return;
+5 -5
drivers/phy/phy-can-transceiver.c
··· 6 6 * 7 7 */ 8 8 #include <linux/of.h> 9 - #include<linux/phy/phy.h> 10 - #include<linux/platform_device.h> 11 - #include<linux/module.h> 12 - #include<linux/gpio.h> 13 - #include<linux/gpio/consumer.h> 9 + #include <linux/phy/phy.h> 10 + #include <linux/platform_device.h> 11 + #include <linux/module.h> 12 + #include <linux/gpio.h> 13 + #include <linux/gpio/consumer.h> 14 14 #include <linux/mux/consumer.h> 15 15 16 16 struct can_transceiver_data {
+2 -2
drivers/phy/phy-core.c
··· 959 959 if (!phy) 960 960 return ERR_PTR(-ENOMEM); 961 961 962 - id = ida_simple_get(&phy_ida, 0, 0, GFP_KERNEL); 962 + id = ida_alloc(&phy_ida, GFP_KERNEL); 963 963 if (id < 0) { 964 964 dev_err(dev, "unable to get id\n"); 965 965 ret = id; ··· 1232 1232 dev_vdbg(dev, "releasing '%s'\n", dev_name(dev)); 1233 1233 debugfs_remove_recursive(phy->debugfs); 1234 1234 regulator_put(phy->pwr); 1235 - ida_simple_remove(&phy_ida, phy->id); 1235 + ida_free(&phy_ida, phy->id); 1236 1236 kfree(phy); 1237 1237 } 1238 1238
+174
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 1203 1203 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1204 1204 }; 1205 1205 1206 + static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1207 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1208 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1209 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1210 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1211 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1212 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1213 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1214 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1215 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1216 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1217 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1218 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1219 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1220 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1221 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1222 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1223 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1224 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1225 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1226 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1227 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1228 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1229 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1230 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1231 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1232 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1233 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1234 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1235 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1236 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1237 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1238 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1239 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1240 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1241 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1242 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1243 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1244 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1245 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1246 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1247 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1248 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1249 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1250 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1251 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1252 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1253 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1254 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1255 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1256 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1257 + }; 1258 + 1259 + static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1260 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1261 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1262 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1263 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1264 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1265 + }; 1266 + 1267 + static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1268 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1269 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1270 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1271 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1272 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1273 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1274 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1275 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1276 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1277 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1278 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1279 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1280 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1281 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1282 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1283 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1284 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1285 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1286 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1287 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1288 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1289 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1290 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1291 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1292 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1293 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1294 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1295 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1296 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1297 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1298 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1299 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1300 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1301 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1302 + QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1303 + }; 1304 + 1305 + static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1306 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1307 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1308 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1309 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 1310 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 1311 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 1312 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 1313 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55), 1314 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 1315 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1316 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1317 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 1318 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 1319 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 1320 + }; 1321 + 1322 + static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1323 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1324 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1325 + }; 1326 + 1206 1327 /* list of regulators */ 1207 1328 struct qmp_regulator_data { 1208 1329 const char *name; ··· 1801 1680 .vreg_list = qmp_phy_vreg_l, 1802 1681 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1803 1682 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1683 + }; 1684 + 1685 + static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 1686 + .offsets = &qmp_combo_offsets_v5, 1687 + 1688 + .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 1689 + .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 1690 + .tx_tbl = x1e80100_usb43dp_tx_tbl, 1691 + .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 1692 + .rx_tbl = x1e80100_usb43dp_rx_tbl, 1693 + .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 1694 + .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 1695 + .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 1696 + .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 1697 + .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 1698 + 1699 + .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1700 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1701 + .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1702 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1703 + 1704 + .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1705 + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1706 + .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1707 + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1708 + .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1709 + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1710 + .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1711 + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1712 + 1713 + .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1714 + .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1715 + .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1716 + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1717 + 1718 + .dp_aux_init = qmp_v4_dp_aux_init, 1719 + .configure_dp_tx = qmp_v4_configure_dp_tx, 1720 + .configure_dp_phy = qmp_v4_configure_dp_phy, 1721 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1722 + 1723 + .reset_list = msm8996_usb3phy_reset_l, 1724 + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1725 + .vreg_list = qmp_phy_vreg_l, 1726 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1727 + .regs = qmp_v45_usb3phy_regs_layout, 1804 1728 }; 1805 1729 1806 1730 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { ··· 3683 3517 { 3684 3518 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3685 3519 .data = &sm8550_usb3dpphy_cfg, 3520 + }, 3521 + { 3522 + .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 3523 + .data = &sm8550_usb3dpphy_cfg, 3524 + }, 3525 + { 3526 + .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 3527 + .data = &x1e80100_usb3dpphy_cfg, 3686 3528 }, 3687 3529 { } 3688 3530 };
+65
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1909 1909 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 1910 1910 }; 1911 1911 1912 + static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 1913 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 1914 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1915 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1916 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1917 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 1918 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 1919 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1920 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1921 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1922 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1923 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1924 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1925 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 1926 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 1927 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 1928 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1929 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 1930 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1931 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1932 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 1933 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 1934 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1935 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1936 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 1937 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1938 + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1939 + }; 1940 + 1912 1941 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 1913 1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1914 1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ··· 3076 3047 .has_nocsr_reset = true, 3077 3048 }; 3078 3049 3050 + static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 3051 + .lanes = 2, 3052 + 3053 + .offsets = &qmp_pcie_offsets_v6_20, 3054 + 3055 + .tbls = { 3056 + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3057 + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3058 + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3059 + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3060 + .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 3061 + .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 3062 + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3063 + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3064 + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3065 + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3066 + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3067 + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3068 + }, 3069 + .reset_list = sdm845_pciephy_reset_l, 3070 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3071 + .vreg_list = sm8550_qmp_phy_vreg_l, 3072 + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3073 + .regs = pciephy_v5_regs_layout, 3074 + 3075 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3076 + .phy_status = PHYSTATUS_4_20, 3077 + .has_nocsr_reset = true, 3078 + }; 3079 + 3079 3080 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 3080 3081 .lanes = 2, 3081 3082 .offsets = &qmp_pcie_offsets_v5_20, ··· 3879 3820 }, { 3880 3821 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 3881 3822 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 3823 + }, { 3824 + .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 3825 + .data = &sm8550_qmp_gen3x2_pciephy_cfg, 3826 + }, { 3827 + .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 3828 + .data = &sm8650_qmp_gen4x2_pciephy_cfg, 3882 3829 }, 3883 3830 { }, 3884 3831 };
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
··· 12 12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008 13 13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 14 14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 15 + #define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020 15 16 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c 16 17 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 17 18 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
+17
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_USB_V7_H_ 7 + #define QCOM_PHY_QMP_PCS_USB_V7_H_ 8 + 9 + #define QPHY_V7_PCS_USB3_POWER_STATE_CONFIG1 0x00 10 + #define QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08 11 + #define QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14 12 + #define QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 13 + #define QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c 14 + #define QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 15 + #define QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44 16 + 17 + #endif
+32
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_V7_H_ 7 + #define QCOM_PHY_QMP_PCS_V7_H_ 8 + 9 + /* Only for QMP V7 PHY - USB/PCIe PCS registers */ 10 + #define QPHY_V7_PCS_SW_RESET 0x000 11 + #define QPHY_V7_PCS_PCS_STATUS1 0x014 12 + #define QPHY_V7_PCS_POWER_DOWN_CONTROL 0x040 13 + #define QPHY_V7_PCS_START_CONTROL 0x044 14 + #define QPHY_V7_PCS_POWER_STATE_CONFIG1 0x090 15 + #define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0x0c4 16 + #define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0x0c8 17 + #define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc 18 + #define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8 19 + #define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0dc 20 + #define QPHY_V7_PCS_RX_SIGDET_LVL 0x188 21 + #define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 22 + #define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 23 + #define QPHY_V7_PCS_RATE_SLEW_CNTRL1 0x198 24 + #define QPHY_V7_PCS_CDR_RESET_TIME 0x1b0 25 + #define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1 0x1c0 26 + #define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2 0x1c4 27 + #define QPHY_V7_PCS_PCS_TX_RX_CONFIG 0x1d0 28 + #define QPHY_V7_PCS_EQ_CONFIG1 0x1dc 29 + #define QPHY_V7_PCS_EQ_CONFIG2 0x1e0 30 + #define QPHY_V7_PCS_EQ_CONFIG5 0x1ec 31 + 32 + #endif
+5
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
··· 22 22 #define QSERDES_V6_COM_DIV_FRAC_START2_MODE1 0x34 23 23 #define QSERDES_V6_COM_DIV_FRAC_START3_MODE1 0x38 24 24 #define QSERDES_V6_COM_HSCLK_SEL_1 0x3c 25 + #define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1 0x40 26 + #define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1 0x44 25 27 #define QSERDES_V6_COM_VCO_TUNE1_MODE1 0x48 26 28 #define QSERDES_V6_COM_VCO_TUNE2_MODE1 0x4c 27 29 #define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50 ··· 50 48 #define QSERDES_V6_COM_VCO_TUNE2_MODE0 0xac 51 49 #define QSERDES_V6_COM_BG_TIMER 0xbc 52 50 #define QSERDES_V6_COM_SSC_EN_CENTER 0xc0 51 + #define QSERDES_V6_COM_SSC_ADJ_PER1 0xc4 53 52 #define QSERDES_V6_COM_SSC_PER1 0xcc 54 53 #define QSERDES_V6_COM_SSC_PER2 0xd0 55 54 #define QSERDES_V6_COM_PLL_POST_DIV_MUX 0xd8 ··· 59 56 #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4 60 57 #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8 61 58 #define QSERDES_V6_COM_PLL_IVCO 0xf4 59 + #define QSERDES_V6_COM_PLL_IVCO_MODE1 0xf8 62 60 #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110 63 61 #define QSERDES_V6_COM_RESETSM_CNTRL 0x118 64 62 #define QSERDES_V6_COM_LOCK_CMP_EN 0x120 ··· 67 63 #define QSERDES_V6_COM_VCO_TUNE_CTRL 0x13c 68 64 #define QSERDES_V6_COM_VCO_TUNE_MAP 0x140 69 65 #define QSERDES_V6_COM_VCO_TUNE_INITVAL2 0x148 66 + #define QSERDES_V6_COM_VCO_TUNE_MAXVAL2 0x158 70 67 #define QSERDES_V6_COM_CLK_SELECT 0x164 71 68 #define QSERDES_V6_COM_CORE_CLK_EN 0x170 72 69 #define QSERDES_V6_COM_CMN_CONFIG_1 0x174
+87
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_COM_V7_H_ 7 + #define QCOM_PHY_QMP_QSERDES_COM_V7_H_ 8 + 9 + /* Only for QMP V7 PHY - QSERDES COM registers */ 10 + 11 + #define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1 0x00 12 + #define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1 0x04 13 + #define QSERDES_V7_COM_CP_CTRL_MODE1 0x10 14 + #define QSERDES_V7_COM_PLL_RCTRL_MODE1 0x14 15 + #define QSERDES_V7_COM_PLL_CCTRL_MODE1 0x18 16 + #define QSERDES_V7_COM_CORECLK_DIV_MODE1 0x1c 17 + #define QSERDES_V7_COM_LOCK_CMP1_MODE1 0x20 18 + #define QSERDES_V7_COM_LOCK_CMP2_MODE1 0x24 19 + #define QSERDES_V7_COM_DEC_START_MODE1 0x28 20 + #define QSERDES_V7_COM_DEC_START_MSB_MODE1 0x2c 21 + #define QSERDES_V7_COM_DIV_FRAC_START1_MODE1 0x30 22 + #define QSERDES_V7_COM_DIV_FRAC_START2_MODE1 0x34 23 + #define QSERDES_V7_COM_DIV_FRAC_START3_MODE1 0x38 24 + #define QSERDES_V7_COM_HSCLK_SEL_1 0x3c 25 + #define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE1 0x40 26 + #define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE1 0x44 27 + #define QSERDES_V7_COM_VCO_TUNE1_MODE1 0x48 28 + #define QSERDES_V7_COM_VCO_TUNE2_MODE1 0x4c 29 + #define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50 30 + #define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54 31 + #define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58 32 + #define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c 33 + #define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0 0x60 34 + #define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0 0x64 35 + #define QSERDES_V7_COM_CP_CTRL_MODE0 0x70 36 + #define QSERDES_V7_COM_PLL_RCTRL_MODE0 0x74 37 + #define QSERDES_V7_COM_PLL_CCTRL_MODE0 0x78 38 + #define QSERDES_V7_COM_PLL_CORE_CLK_DIV_MODE0 0x7c 39 + #define QSERDES_V7_COM_LOCK_CMP1_MODE0 0x80 40 + #define QSERDES_V7_COM_LOCK_CMP2_MODE0 0x84 41 + #define QSERDES_V7_COM_DEC_START_MODE0 0x88 42 + #define QSERDES_V7_COM_DEC_START_MSB_MODE0 0x8c 43 + #define QSERDES_V7_COM_DIV_FRAC_START1_MODE0 0x90 44 + #define QSERDES_V7_COM_DIV_FRAC_START2_MODE0 0x94 45 + #define QSERDES_V7_COM_DIV_FRAC_START3_MODE0 0x98 46 + #define QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL_1 0x9c 47 + #define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE0 0xa0 48 + #define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE0 0xa4 49 + #define QSERDES_V7_COM_VCO_TUNE1_MODE0 0xa8 50 + #define QSERDES_V7_COM_VCO_TUNE2_MODE0 0xac 51 + #define QSERDES_V7_COM_BG_TIMER 0xbc 52 + #define QSERDES_V7_COM_SSC_EN_CENTER 0xc0 53 + #define QSERDES_V7_COM_SSC_ADJ_PER1 0xc4 54 + #define QSERDES_V7_COM_SSC_PER1 0xcc 55 + #define QSERDES_V7_COM_SSC_PER2 0xd0 56 + #define QSERDES_V7_COM_PLL_POST_DIV_MUX 0xd8 57 + #define QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc 58 + #define QSERDES_V7_COM_CLK_ENABLE1 0xe0 59 + #define QSERDES_V7_COM_SYS_CLK_CTRL 0xe4 60 + #define QSERDES_V7_COM_SYSCLK_BUF_ENABLE 0xe8 61 + #define QSERDES_V7_COM_PLL_IVCO 0xf4 62 + #define QSERDES_V7_COM_PLL_IVCO_MODE1 0xf8 63 + #define QSERDES_V7_COM_SYSCLK_EN_SEL 0x110 64 + #define QSERDES_V7_COM_RESETSM_CNTRL 0x118 65 + #define QSERDES_V7_COM_LOCK_CMP_EN 0x120 66 + #define QSERDES_V7_COM_LOCK_CMP_CFG 0x124 67 + #define QSERDES_V7_COM_VCO_TUNE_CTRL 0x13c 68 + #define QSERDES_V7_COM_VCO_TUNE_MAP 0x140 69 + #define QSERDES_V7_COM_VCO_TUNE_INITVAL2 0x148 70 + #define QSERDES_V7_COM_VCO_TUNE_MAXVAL2 0x158 71 + #define QSERDES_V7_COM_CLK_SELECT 0x164 72 + #define QSERDES_V7_COM_CORE_CLK_EN 0x170 73 + #define QSERDES_V7_COM_CMN_CONFIG_1 0x174 74 + #define QSERDES_V7_COM_SVS_MODE_CLK_SEL 0x17c 75 + #define QSERDES_V7_COM_CMN_MISC_1 0x184 76 + #define QSERDES_V7_COM_CMN_MODE 0x188 77 + #define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL 0x198 78 + #define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 79 + #define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 80 + #define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac 81 + #define QSERDES_V7_COM_ADDITIONAL_MISC 0x1b4 82 + #define QSERDES_V7_COM_ADDITIONAL_MISC_2 0x1b8 83 + #define QSERDES_V7_COM_ADDITIONAL_MISC_3 0x1bc 84 + #define QSERDES_V7_COM_CMN_STATUS 0x1d0 85 + #define QSERDES_V7_COM_C_READY_STATUS 0x1f8 86 + 87 + #endif
+8
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
··· 10 10 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c 11 11 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 12 12 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 13 + #define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c 14 + #define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 13 15 14 16 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 15 17 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 18 + #define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28 19 + #define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58 20 + #define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4 21 + #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 22 + #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc 16 23 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 24 + #define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0 17 25 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 18 26 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c 19 27 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
+1
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
··· 23 23 #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 24 24 #define QSERDES_V6_TX_BIST_PATTERN7 0x7c 25 25 #define QSERDES_V6_TX_LANE_MODE_1 0x84 26 + #define QSERDES_V6_TX_LANE_MODE_2 0x88 26 27 #define QSERDES_V6_TX_LANE_MODE_3 0x8c 27 28 #define QSERDES_V6_TX_LANE_MODE_4 0x90 28 29 #define QSERDES_V6_TX_LANE_MODE_5 0x94
+4
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
··· 15 15 16 16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 17 17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c 18 + #define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18 18 19 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 19 20 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 20 21 #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c 21 22 #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 23 + #define QSERDES_V6_20_RX_DFE_1 0xac 24 + #define QSERDES_V6_20_RX_DFE_2 0xb0 22 25 #define QSERDES_V6_20_RX_DFE_3 0xb4 23 26 #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 24 27 #define QSERDES_V6_20_RX_GM_CAL 0x10c ··· 44 41 #define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 45 42 #define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 46 43 #define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 44 + #define QSERDES_V6_20_RX_BKUP_CTRL1 0x22c 47 45 48 46 #endif
+51
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_ 7 + #define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_ 8 + 9 + #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x30 10 + #define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x34 11 + #define QSERDES_V6_N4_TX_LANE_MODE_1 0x78 12 + #define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c 13 + #define QSERDES_V6_N4_TX_LANE_MODE_3 0x80 14 + 15 + #define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x8 16 + #define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x18 17 + #define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS 0x20 18 + #define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE 0x94 19 + #define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2 0x9c 20 + #define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET 0xa0 21 + #define QSERDES_V6_N4_RX_DFE_3 0xb4 22 + #define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1 0xe0 23 + #define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL 0xe8 24 + #define QSERDES_V6_N4_RX_GM_CAL 0x10c 25 + #define QSERDES_V6_N4_RX_SIGDET_ENABLES 0x148 26 + #define QSERDES_V6_N4_RX_SIGDET_CNTRL 0x14c 27 + #define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL 0x154 28 + #define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 29 + #define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc 30 + #define QSERDES_V6_N4_RX_UCDR_PI_CTRL1 0x23c 31 + #define QSERDES_V6_N4_RX_UCDR_PI_CTRL2 0x240 32 + #define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2 0x27c 33 + #define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1 0x298 34 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0 0x2b8 35 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1 0x2bc 36 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2 0x2c0 37 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3 0x2c4 38 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4 0x2c8 39 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5 0x2cc 40 + #define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6 0x2d0 41 + #define QSERDES_V6_N4_RX_MODE_RATE2_B0 0x2d4 42 + #define QSERDES_V6_N4_RX_MODE_RATE2_B1 0x2d8 43 + #define QSERDES_V6_N4_RX_MODE_RATE2_B2 0x2dc 44 + #define QSERDES_V6_N4_RX_MODE_RATE2_B3 0x2e0 45 + #define QSERDES_V6_N4_RX_MODE_RATE2_B4 0x2e4 46 + #define QSERDES_V6_N4_RX_MODE_RATE2_B5 0x2e8 47 + #define QSERDES_V6_N4_RX_MODE_RATE2_B6 0x2ec 48 + #define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE 0x30c 49 + #define QSERDES_V6_N4_RX_RX_BKUP_CTRL1 0x310 50 + 51 + #endif
+78
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V7_H_ 7 + #define QCOM_PHY_QMP_QSERDES_TXRX_V7_H_ 8 + 9 + #define QSERDES_V7_TX_CLKBUF_ENABLE 0x08 10 + #define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c 11 + #define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20 12 + #define QSERDES_V7_TX_TX_BAND 0x24 13 + #define QSERDES_V7_TX_INTERFACE_SELECT 0x2c 14 + #define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34 15 + #define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38 16 + #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c 17 + #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40 18 + #define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 19 + #define QSERDES_V7_TX_BIST_PATTERN7 0x7c 20 + #define QSERDES_V7_TX_LANE_MODE_1 0x84 21 + #define QSERDES_V7_TX_LANE_MODE_2 0x88 22 + #define QSERDES_V7_TX_LANE_MODE_3 0x8c 23 + #define QSERDES_V7_TX_LANE_MODE_4 0x90 24 + #define QSERDES_V7_TX_LANE_MODE_5 0x94 25 + #define QSERDES_V7_TX_RCV_DETECT_LVL_2 0xa4 26 + #define QSERDES_V7_TX_TRAN_DRVR_EMP_EN 0xc0 27 + #define QSERDES_V7_TX_TX_INTERFACE_MODE 0xc4 28 + #define QSERDES_V7_TX_VMODE_CTRL1 0xc8 29 + #define QSERDES_V7_TX_PI_QEC_CTRL 0xe4 30 + 31 + #define QSERDES_V7_RX_UCDR_FO_GAIN 0x08 32 + #define QSERDES_V7_RX_UCDR_SO_GAIN 0x14 33 + #define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN 0x30 34 + #define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 35 + #define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c 36 + #define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 37 + #define QSERDES_V7_RX_UCDR_PI_CONTROLS 0x44 38 + #define QSERDES_V7_RX_UCDR_SB2_THRESH1 0x4c 39 + #define QSERDES_V7_RX_UCDR_SB2_THRESH2 0x50 40 + #define QSERDES_V7_RX_UCDR_SB2_GAIN1 0x54 41 + #define QSERDES_V7_RX_UCDR_SB2_GAIN2 0x58 42 + #define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE 0x60 43 + #define QSERDES_V7_RX_TX_ADAPT_POST_THRESH 0xcc 44 + #define QSERDES_V7_RX_VGA_CAL_CNTRL1 0xd4 45 + #define QSERDES_V7_RX_VGA_CAL_CNTRL2 0xd8 46 + #define QSERDES_V7_RX_GM_CAL 0xdc 47 + #define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2 0xec 48 + #define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 49 + #define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 50 + #define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW 0xf8 51 + #define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH 0xfc 52 + #define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 53 + #define QSERDES_V7_RX_SIDGET_ENABLES 0x118 54 + #define QSERDES_V7_RX_SIGDET_CNTRL 0x11c 55 + #define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL 0x124 56 + #define QSERDES_V7_RX_RX_MODE_00_LOW 0x15c 57 + #define QSERDES_V7_RX_RX_MODE_00_HIGH 0x160 58 + #define QSERDES_V7_RX_RX_MODE_00_HIGH2 0x164 59 + #define QSERDES_V7_RX_RX_MODE_00_HIGH3 0x168 60 + #define QSERDES_V7_RX_RX_MODE_00_HIGH4 0x16c 61 + #define QSERDES_V7_RX_RX_MODE_01_LOW 0x170 62 + #define QSERDES_V7_RX_RX_MODE_01_HIGH 0x174 63 + #define QSERDES_V7_RX_RX_MODE_01_HIGH2 0x178 64 + #define QSERDES_V7_RX_RX_MODE_01_HIGH3 0x17c 65 + #define QSERDES_V7_RX_RX_MODE_01_HIGH4 0x180 66 + #define QSERDES_V7_RX_RX_MODE_10_LOW 0x184 67 + #define QSERDES_V7_RX_RX_MODE_10_HIGH 0x188 68 + #define QSERDES_V7_RX_RX_MODE_10_HIGH2 0x18c 69 + #define QSERDES_V7_RX_RX_MODE_10_HIGH3 0x190 70 + #define QSERDES_V7_RX_RX_MODE_10_HIGH4 0x194 71 + #define QSERDES_V7_RX_DFE_EN_TIMER 0x1a0 72 + #define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 73 + #define QSERDES_V7_RX_DCC_CTRL1 0x1a8 74 + #define QSERDES_V7_RX_VTH_CODE 0x1b0 75 + #define QSERDES_V7_RX_SIGDET_CAL_CTRL1 0x1e4 76 + #define QSERDES_V7_RX_SIGDET_CAL_TRIM 0x1f8 77 + 78 + #endif
+105 -9
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 763 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 764 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 765 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 766 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), 767 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 768 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 769 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 770 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), 771 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 766 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 767 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 768 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 769 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 770 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 771 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 772 + }; 773 + 774 + static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { 775 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 772 776 }; 773 777 774 778 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { 775 - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), 779 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 776 780 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 781 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), 777 782 }; 778 783 779 784 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { 780 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c), 781 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f), 785 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 782 786 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 783 787 784 788 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), ··· 804 800 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 805 801 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 806 802 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), 803 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 804 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 805 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 806 + }; 807 + 808 + static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 809 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 810 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 811 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 812 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 813 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 814 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 815 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 816 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 817 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 818 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 819 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 820 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 821 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 822 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 823 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 824 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 825 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 826 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 827 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 828 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 829 + }; 830 + 831 + static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = { 832 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 833 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 834 + }; 835 + 836 + static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 837 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 838 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), 839 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 840 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 841 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 842 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 843 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 844 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 845 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 846 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 847 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 848 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 849 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 850 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 851 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), 852 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f), 853 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 854 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), 855 + }; 856 + 857 + static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = { 858 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00), 859 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 860 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1), 861 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 862 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 863 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 864 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 865 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 807 866 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 808 867 }; 809 868 ··· 1362 1295 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1363 1296 .pcs = sm8550_ufsphy_pcs, 1364 1297 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1298 + }, 1299 + .tbls_hs_b = { 1300 + .serdes = sm8550_ufsphy_hs_b_serdes, 1301 + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1302 + }, 1303 + .clk_list = sdm845_ufs_phy_clk_l, 1304 + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1305 + .vreg_list = qmp_phy_vreg_l, 1306 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1307 + .regs = ufsphy_v6_regs_layout, 1308 + }; 1309 + 1310 + static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { 1311 + .lanes = 2, 1312 + 1313 + .offsets = &qmp_ufs_offsets_v6, 1314 + 1315 + .tbls = { 1316 + .serdes = sm8650_ufsphy_serdes, 1317 + .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes), 1318 + .tx = sm8650_ufsphy_tx, 1319 + .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx), 1320 + .rx = sm8650_ufsphy_rx, 1321 + .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx), 1322 + .pcs = sm8650_ufsphy_pcs, 1323 + .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1365 1324 }, 1366 1325 .clk_list = sdm845_ufs_phy_clk_l, 1367 1326 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ··· 1919 1826 }, { 1920 1827 .compatible = "qcom,sm8550-qmp-ufs-phy", 1921 1828 .data = &sm8550_ufsphy_cfg, 1829 + }, { 1830 + .compatible = "qcom,sm8650-qmp-ufs-phy", 1831 + .data = &sm8650_ufsphy_cfg, 1922 1832 }, 1923 1833 { }, 1924 1834 };
+344
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
··· 24 24 #include "phy-qcom-qmp-pcs-misc-v4.h" 25 25 #include "phy-qcom-qmp-pcs-usb-v4.h" 26 26 #include "phy-qcom-qmp-pcs-usb-v5.h" 27 + #include "phy-qcom-qmp-pcs-usb-v6.h" 28 + #include "phy-qcom-qmp-pcs-usb-v7.h" 27 29 28 30 /* QPHY_SW_RESET bit */ 29 31 #define SW_RESET BIT(0) ··· 151 149 /* In PCS_USB */ 152 150 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 153 151 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 152 + }; 153 + 154 + static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 155 + [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 156 + [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 157 + [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 158 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 159 + 160 + /* In PCS_USB */ 161 + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 162 + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 163 + }; 164 + 165 + static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 166 + [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET, 167 + [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL, 168 + [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1, 169 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL, 170 + 171 + /* In PCS_USB */ 172 + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL, 173 + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 154 174 }; 155 175 156 176 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { ··· 895 871 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 896 872 }; 897 873 874 + static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = { 875 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e), 876 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 877 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 878 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 879 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 880 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 881 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 882 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 883 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 884 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 885 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea), 886 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 887 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 888 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 889 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 890 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 891 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 892 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 893 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 894 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e), 895 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 896 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 897 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 898 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 899 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 900 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 901 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 902 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 903 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 904 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 905 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 906 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 907 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 908 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 909 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 910 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 911 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 912 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 913 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 914 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 915 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 916 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 917 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 918 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 919 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 920 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 921 + }; 922 + 923 + static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = { 924 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 925 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 926 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 927 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 928 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 929 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 930 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 931 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 932 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 933 + QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21), 934 + }; 935 + 936 + static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = { 937 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 938 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 939 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 940 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 941 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 942 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 943 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 944 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 945 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 946 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 947 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 948 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 949 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 950 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 951 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 952 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 953 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 954 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 955 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 956 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 957 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 958 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 959 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 960 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 961 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 962 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff), 963 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf), 964 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed), 965 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 966 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 967 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 968 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 969 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 970 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 971 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 972 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 973 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 974 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 975 + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 976 + }; 977 + 978 + static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = { 979 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 980 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 981 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 982 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 983 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 984 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa), 985 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 986 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 987 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 988 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 989 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 990 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 991 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 992 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 993 + }; 994 + 995 + static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = { 996 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 997 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 998 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 999 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1000 + }; 1001 + 898 1002 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 899 1003 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 900 1004 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ··· 1313 1161 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1314 1162 }; 1315 1163 1164 + static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = { 1165 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1166 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1167 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02), 1168 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16), 1169 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36), 1170 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04), 1171 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16), 1172 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41), 1173 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41), 1174 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55), 1175 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75), 1176 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01), 1177 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01), 1178 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25), 1179 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02), 1180 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1181 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1182 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1183 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1184 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1185 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1186 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02), 1187 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16), 1188 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36), 1189 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08), 1190 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a), 1191 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41), 1192 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55), 1193 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75), 1194 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01), 1195 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25), 1196 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02), 1197 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a), 1198 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01), 1199 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62), 1200 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02), 1201 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a), 1202 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a), 1203 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14), 1204 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04), 1205 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20), 1206 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16), 1207 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1208 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 1209 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 1210 + QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c), 1211 + }; 1212 + 1213 + static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = { 1214 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00), 1215 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00), 1216 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1217 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1218 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5), 1219 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f), 1220 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f), 1221 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f), 1222 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12), 1223 + QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21), 1224 + }; 1225 + 1226 + static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = { 1227 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a), 1228 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06), 1229 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1230 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1231 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1232 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1233 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99), 1234 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08), 1235 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08), 1236 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00), 1237 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a), 1238 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1239 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54), 1240 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f), 1241 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13), 1242 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1243 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1244 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1245 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1246 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1247 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1248 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04), 1249 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1250 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f), 1251 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf), 1252 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff), 1253 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf), 1254 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed), 1255 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc), 1256 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c), 1257 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c), 1258 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d), 1259 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09), 1260 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04), 1261 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1262 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c), 1263 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10), 1264 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14), 1265 + QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08), 1266 + }; 1267 + 1268 + static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = { 1269 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1270 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89), 1271 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20), 1272 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13), 1273 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21), 1274 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa), 1275 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1276 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1277 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a), 1278 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1279 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1280 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c), 1281 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b), 1282 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10), 1283 + }; 1284 + 1285 + static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = { 1286 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1287 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1288 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1289 + QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1290 + }; 1291 + 1316 1292 struct qmp_usb_offsets { 1317 1293 u16 serdes; 1318 1294 u16 pcs; ··· 1590 1310 }; 1591 1311 1592 1312 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1313 + .serdes = 0, 1314 + .pcs = 0x0200, 1315 + .pcs_usb = 0x1200, 1316 + .tx = 0x0e00, 1317 + .rx = 0x1000, 1318 + }; 1319 + 1320 + static const struct qmp_usb_offsets qmp_usb_offsets_v6 = { 1321 + .serdes = 0, 1322 + .pcs = 0x0200, 1323 + .pcs_usb = 0x1200, 1324 + .tx = 0x0e00, 1325 + .rx = 0x1000, 1326 + }; 1327 + 1328 + static const struct qmp_usb_offsets qmp_usb_offsets_v7 = { 1593 1329 .serdes = 0, 1594 1330 .pcs = 0x0200, 1595 1331 .pcs_usb = 0x1200, ··· 1837 1541 .has_pwrdn_delay = true, 1838 1542 }; 1839 1543 1544 + static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { 1545 + .lanes = 1, 1546 + .offsets = &qmp_usb_offsets_v6, 1547 + 1548 + .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl, 1549 + .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl), 1550 + .tx_tbl = sdx75_usb3_uniphy_tx_tbl, 1551 + .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl), 1552 + .rx_tbl = sdx75_usb3_uniphy_rx_tbl, 1553 + .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl), 1554 + .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl, 1555 + .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl), 1556 + .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl, 1557 + .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl), 1558 + .vreg_list = qmp_phy_vreg_l, 1559 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1560 + .regs = qmp_v6_usb3phy_regs_layout, 1561 + .pcs_usb_offset = 0x1000, 1562 + 1563 + .has_pwrdn_delay = true, 1564 + }; 1565 + 1840 1566 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1841 1567 .lanes = 1, 1842 1568 ··· 1898 1580 .vreg_list = qmp_phy_vreg_l, 1899 1581 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1900 1582 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 1583 + }; 1584 + 1585 + static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = { 1586 + .lanes = 1, 1587 + 1588 + .offsets = &qmp_usb_offsets_v7, 1589 + 1590 + .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl, 1591 + .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl), 1592 + .tx_tbl = x1e80100_usb3_uniphy_tx_tbl, 1593 + .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl), 1594 + .rx_tbl = x1e80100_usb3_uniphy_rx_tbl, 1595 + .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl), 1596 + .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl, 1597 + .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl), 1598 + .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl, 1599 + .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl), 1600 + .vreg_list = qmp_phy_vreg_l, 1601 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1602 + .regs = qmp_v7_usb3phy_regs_layout, 1901 1603 }; 1902 1604 1903 1605 static void qmp_usb_configure_lane(void __iomem *base, ··· 2595 2257 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2596 2258 .data = &sdx65_usb3_uniphy_cfg, 2597 2259 }, { 2260 + .compatible = "qcom,sdx75-qmp-usb3-uni-phy", 2261 + .data = &sdx75_usb3_uniphy_cfg, 2262 + }, { 2598 2263 .compatible = "qcom,sm6115-qmp-usb3-phy", 2599 2264 .data = &qcm2290_usb3phy_cfg, 2600 2265 }, { ··· 2609 2268 }, { 2610 2269 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2611 2270 .data = &sm8350_usb3_uniphy_cfg, 2271 + }, { 2272 + .compatible = "qcom,x1e80100-qmp-usb3-uni-phy", 2273 + .data = &x1e80100_usb3_uniphy_cfg, 2612 2274 }, 2613 2275 { }, 2614 2276 };
+6
drivers/phy/qualcomm/phy-qcom-qmp.h
··· 24 24 #include "phy-qcom-qmp-qserdes-com-v6.h" 25 25 #include "phy-qcom-qmp-qserdes-txrx-v6.h" 26 26 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h" 27 + #include "phy-qcom-qmp-qserdes-txrx-v6_n4.h" 27 28 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h" 29 + 30 + #include "phy-qcom-qmp-qserdes-com-v7.h" 31 + #include "phy-qcom-qmp-qserdes-txrx-v7.h" 28 32 29 33 #include "phy-qcom-qmp-qserdes-pll.h" 30 34 ··· 47 43 #include "phy-qcom-qmp-pcs-v6.h" 48 44 49 45 #include "phy-qcom-qmp-pcs-v6_20.h" 46 + 47 + #include "phy-qcom-qmp-pcs-v7.h" 50 48 51 49 /* Only for QMP V3 & V4 PHY - DP COM registers */ 52 50 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
+1 -1
drivers/phy/renesas/Kconfig
··· 13 13 config PHY_RCAR_GEN2 14 14 tristate "Renesas R-Car generation 2 USB PHY driver" 15 15 depends on ARCH_RENESAS 16 - depends on GENERIC_PHY 16 + select GENERIC_PHY 17 17 help 18 18 Support for USB PHY found on Renesas R-Car generation 2 SoCs. 19 19
+127 -29
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
··· 123 123 * @disrise_en: host disconnect rise edge detection enable. 124 124 * @disrise_st: host disconnect rise edge detection state. 125 125 * @disrise_clr: host disconnect rise edge detection clear. 126 - * @id_det_en: id detection enable register. 127 - * @id_det_st: id detection state register. 128 - * @id_det_clr: id detection clear register. 126 + * @idfall_det_en: id detection enable register, falling edge 127 + * @idfall_det_st: id detection state register, falling edge 128 + * @idfall_det_clr: id detection clear register, falling edge 129 + * @idrise_det_en: id detection enable register, rising edge 130 + * @idrise_det_st: id detection state register, rising edge 131 + * @idrise_det_clr: id detection clear register, rising edge 129 132 * @ls_det_en: linestate detection enable register. 130 133 * @ls_det_st: linestate detection state register. 131 134 * @ls_det_clr: linestate detection clear register. ··· 149 146 struct usb2phy_reg disrise_en; 150 147 struct usb2phy_reg disrise_st; 151 148 struct usb2phy_reg disrise_clr; 152 - struct usb2phy_reg id_det_en; 153 - struct usb2phy_reg id_det_st; 154 - struct usb2phy_reg id_det_clr; 149 + struct usb2phy_reg idfall_det_en; 150 + struct usb2phy_reg idfall_det_st; 151 + struct usb2phy_reg idfall_det_clr; 152 + struct usb2phy_reg idrise_det_en; 153 + struct usb2phy_reg idrise_det_st; 154 + struct usb2phy_reg idrise_det_clr; 155 155 struct usb2phy_reg ls_det_en; 156 156 struct usb2phy_reg ls_det_st; 157 157 struct usb2phy_reg ls_det_clr; ··· 494 488 if (ret) 495 489 goto out; 496 490 497 - /* clear id status and enable id detect irq */ 491 + /* clear id status and enable id detect irqs */ 498 492 ret = property_enable(rphy->grf, 499 - &rport->port_cfg->id_det_clr, 493 + &rport->port_cfg->idfall_det_clr, 500 494 true); 501 495 if (ret) 502 496 goto out; 503 497 504 498 ret = property_enable(rphy->grf, 505 - &rport->port_cfg->id_det_en, 499 + &rport->port_cfg->idrise_det_clr, 500 + true); 501 + if (ret) 502 + goto out; 503 + 504 + ret = property_enable(rphy->grf, 505 + &rport->port_cfg->idfall_det_en, 506 + true); 507 + if (ret) 508 + goto out; 509 + 510 + ret = property_enable(rphy->grf, 511 + &rport->port_cfg->idrise_det_en, 506 512 true); 507 513 if (ret) 508 514 goto out; ··· 1048 1030 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 1049 1031 bool id; 1050 1032 1051 - if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st)) 1033 + if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) && 1034 + !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) 1052 1035 return IRQ_NONE; 1053 1036 1054 1037 /* clear id detect irq pending status */ 1055 - property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true); 1038 + if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st)) 1039 + property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr, true); 1040 + 1041 + if (property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) 1042 + property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr, true); 1056 1043 1057 1044 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); 1058 1045 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); ··· 1487 1464 return ret; 1488 1465 } 1489 1466 1467 + static int rk3128_usb2phy_tuning(struct rockchip_usb2phy *rphy) 1468 + { 1469 + /* Turn off differential receiver in suspend mode */ 1470 + return regmap_write_bits(rphy->grf, 0x298, 1471 + BIT(2) << BIT_WRITEABLE_SHIFT | BIT(2), 1472 + BIT(2) << BIT_WRITEABLE_SHIFT | 0); 1473 + } 1474 + 1490 1475 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 1491 1476 { 1492 1477 int ret; ··· 1544 1513 return ret; 1545 1514 } 1546 1515 1516 + static const struct rockchip_usb2phy_cfg rk3128_phy_cfgs[] = { 1517 + { 1518 + .reg = 0x17c, 1519 + .num_ports = 2, 1520 + .phy_tuning = rk3128_usb2phy_tuning, 1521 + .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 1522 + .port_cfgs = { 1523 + [USB2PHY_PORT_OTG] = { 1524 + .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1525 + .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1526 + .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1527 + .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1528 + .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1529 + .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1530 + .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1531 + .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1532 + .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1533 + .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1534 + .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1535 + .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1536 + .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1537 + .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1538 + .utmi_id = { 0x014c, 8, 8, 0, 1 }, 1539 + .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1540 + }, 1541 + [USB2PHY_PORT_HOST] = { 1542 + .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1543 + .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1544 + .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1545 + .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1546 + } 1547 + }, 1548 + .chg_det = { 1549 + .opmode = { 0x017c, 3, 0, 5, 1 }, 1550 + .cp_det = { 0x02c0, 6, 6, 0, 1 }, 1551 + .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 1552 + .dp_det = { 0x02c0, 7, 7, 0, 1 }, 1553 + .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 1554 + .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 1555 + .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 1556 + .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 1557 + .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 1558 + .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 1559 + }, 1560 + }, 1561 + { /* sentinel */ } 1562 + }; 1563 + 1547 1564 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { 1548 1565 { 1549 1566 .reg = 0x760, ··· 1603 1524 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1604 1525 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1605 1526 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1606 - .id_det_en = { 0x0680, 6, 5, 0, 3 }, 1607 - .id_det_st = { 0x0690, 6, 5, 0, 3 }, 1608 - .id_det_clr = { 0x06a0, 6, 5, 0, 3 }, 1527 + .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 1528 + .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 1529 + .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 1530 + .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 1531 + .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 1532 + .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 1609 1533 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1610 1534 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1611 1535 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, ··· 1669 1587 .bvalid_det_en = { 0x3020, 3, 2, 0, 3 }, 1670 1588 .bvalid_det_st = { 0x3024, 3, 2, 0, 3 }, 1671 1589 .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 }, 1672 - .id_det_en = { 0x3020, 5, 4, 0, 3 }, 1673 - .id_det_st = { 0x3024, 5, 4, 0, 3 }, 1674 - .id_det_clr = { 0x3028, 5, 4, 0, 3 }, 1590 + .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1591 + .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1592 + .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1593 + .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1594 + .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1595 + .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1675 1596 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1676 1597 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1677 1598 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, ··· 1719 1634 .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, 1720 1635 .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, 1721 1636 .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, 1722 - .id_det_en = { 0x0110, 5, 4, 0, 3 }, 1723 - .id_det_st = { 0x0114, 5, 4, 0, 3 }, 1724 - .id_det_clr = { 0x0118, 5, 4, 0, 3 }, 1637 + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1638 + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1639 + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1640 + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1641 + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1642 + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1725 1643 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1726 1644 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1727 1645 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, ··· 1788 1700 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1789 1701 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1790 1702 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1791 - .id_det_en = { 0xe3c0, 5, 4, 0, 3 }, 1792 - .id_det_st = { 0xe3e0, 5, 4, 0, 3 }, 1793 - .id_det_clr = { 0xe3d0, 5, 4, 0, 3 }, 1703 + .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1704 + .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1705 + .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1706 + .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1707 + .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1708 + .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1794 1709 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1795 1710 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1796 1711 .utmi_id = { 0xe2ac, 8, 8, 0, 1 }, ··· 1830 1739 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1831 1740 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1832 1741 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1833 - .id_det_en = { 0xe3c0, 10, 9, 0, 3 }, 1834 - .id_det_st = { 0xe3e0, 10, 9, 0, 3 }, 1835 - .id_det_clr = { 0xe3d0, 10, 9, 0, 3 }, 1742 + .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1743 + .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1744 + .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1745 + .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1746 + .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1747 + .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1836 1748 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1837 1749 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1838 1750 .utmi_id = { 0xe2ac, 11, 11, 0, 1 }, ··· 1864 1770 .bvalid_det_en = { 0x0080, 3, 2, 0, 3 }, 1865 1771 .bvalid_det_st = { 0x0084, 3, 2, 0, 3 }, 1866 1772 .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 }, 1867 - .id_det_en = { 0x0080, 5, 4, 0, 3 }, 1868 - .id_det_st = { 0x0084, 5, 4, 0, 3 }, 1869 - .id_det_clr = { 0x0088, 5, 4, 0, 3 }, 1773 + .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1774 + .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1775 + .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1776 + .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1777 + .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1778 + .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1870 1779 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1871 1780 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1872 1781 .utmi_id = { 0x00c0, 6, 6, 0, 1 }, ··· 2087 1990 2088 1991 static const struct of_device_id rockchip_usb2phy_dt_match[] = { 2089 1992 { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs }, 1993 + { .compatible = "rockchip,rk3128-usb2phy", .data = &rk3128_phy_cfgs }, 2090 1994 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs }, 2091 1995 { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs }, 2092 1996 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
+1 -1
drivers/phy/ti/phy-gmii-sel.c
··· 248 248 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { 249 249 .use_of_data = true, 250 250 .regfields = phy_gmii_sel_fields_am654, 251 - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | 251 + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 252 252 BIT(PHY_INTERFACE_MODE_USXGMII), 253 253 .num_ports = 8, 254 254 .num_qsgmii_main_ports = 2,
+1
drivers/phy/ti/phy-j721e-wiz.c
··· 1240 1240 case J721E_WIZ_10G: 1241 1241 case J7200_WIZ_10G: 1242 1242 case J721S2_WIZ_10G: 1243 + case J784S4_WIZ_10G: 1243 1244 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1244 1245 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1245 1246 break;