drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

+8

drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h

··· 4552 4552 #define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 4553 4553 #define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 4554 4554 #define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 4555 + #define mmDP_DPHY_SCRAM_CNTL 0x4ab6 4556 + #define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6 4557 + #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 4558 + #define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6 4559 + #define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6 4560 + #define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6 4561 + #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6 4562 + #define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6 4555 4563 #define mmDP_DPHY_CRC_EN 0x4ab7 4556 4564 #define mmDP0_DP_DPHY_CRC_EN 0x4ab7 4557 4565 #define mmDP1_DP_DPHY_CRC_EN 0x4bb7

+4

drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h

··· 8690 8690 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 8691 8691 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 8692 8692 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 8693 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10 8694 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 8695 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00 8696 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 8693 8697 #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 8694 8698 #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 8695 8699 #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10

+9

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h

··· 4544 4544 #define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 4545 4545 #define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 4546 4546 #define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 4547 + #define mmDP_DPHY_SCRAM_CNTL 0x4ab6 4548 + #define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6 4549 + #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 4550 + #define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6 4551 + #define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6 4552 + #define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6 4553 + #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6 4554 + #define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6 4555 + #define mmDP8_DP_DPHY_SCRAM_CNTL 0x56b6 4547 4556 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc 4548 4557 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc 4549 4558 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc

+4

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h

··· 8366 8366 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 8367 8367 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 8368 8368 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 8369 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10 8370 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 8371 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00 8372 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 8369 8373 #define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff 8370 8374 #define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 8371 8375 #define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000

+9

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h

··· 5776 5776 #define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 5777 5777 #define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 5778 5778 #define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 5779 + #define mmDP_DPHY_SCRAM_CNTL 0x4ab6 5780 + #define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6 5781 + #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 5782 + #define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6 5783 + #define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6 5784 + #define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6 5785 + #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6 5786 + #define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6 5787 + #define mmDP8_DP_DPHY_SCRAM_CNTL 0x56b6 5779 5788 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc 5780 5789 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc 5781 5790 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc

+4

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h

··· 9628 9628 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 9629 9629 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 9630 9630 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 9631 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10 9632 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 9633 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00 9634 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 9631 9635 #define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff 9632 9636 #define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 9633 9637 #define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000

+8

drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h

··· 3920 3920 #define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4 3921 3921 #define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4 3922 3922 #define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4 3923 + #define mmDP_DPHY_SCRAM_CNTL 0x1cd5 3924 + #define mmDP0_DP_DPHY_SCRAM_CNTL 0x1cd5 3925 + #define mmDP1_DP_DPHY_SCRAM_CNTL 0x1fd5 3926 + #define mmDP2_DP_DPHY_SCRAM_CNTL 0x42d5 3927 + #define mmDP3_DP_DPHY_SCRAM_CNTL 0x45d5 3928 + #define mmDP4_DP_DPHY_SCRAM_CNTL 0x48d5 3929 + #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4bd5 3930 + #define mmDP6_DP_DPHY_SCRAM_CNTL 0x4ed5 3923 3931 #define mmDP_DPHY_CRC_EN 0x1cd6 3924 3932 #define mmDP0_DP_DPHY_CRC_EN 0x1cd6 3925 3933 #define mmDP1_DP_DPHY_CRC_EN 0x1fd6

+4

drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h

··· 9214 9214 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 9215 9215 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 9216 9216 #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 9217 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10 9218 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 9219 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00 9220 + #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 9217 9221 #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 9218 9222 #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 9219 9223 #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10