Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

spi/pxa2xx: convert to the common clk framework

Convert clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare() respectively in order to support the common clk
framework. Otherwise we get warnings on the console as the clock is not
prepared before it is enabled.

In addition we must cache the maximum clock rate to drv_data->max_clk_rate
at probe time because clk_get_rate() cannot be called in tasklet context.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

authored by

Mika Westerberg and committed by
Mark Brown
3343b7a6 7f86bde9

+20 -31
+20 -13
drivers/spi/spi-pxa2xx.c
··· 30 30 #include <linux/delay.h> 31 31 #include <linux/gpio.h> 32 32 #include <linux/slab.h> 33 + #include <linux/clk.h> 33 34 34 35 #include <asm/io.h> 35 36 #include <asm/irq.h> ··· 114 113 u32 int_cr1; 115 114 u32 clear_sr; 116 115 u32 mask_sr; 116 + 117 + /* Maximun clock rate */ 118 + unsigned long max_clk_rate; 117 119 118 120 /* Message Transfer pump */ 119 121 struct tasklet_struct pump_transfers; ··· 895 891 return retval; 896 892 } 897 893 898 - static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) 894 + static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 899 895 { 900 - unsigned long ssp_clk = clk_get_rate(ssp->clk); 896 + unsigned long ssp_clk = drv_data->max_clk_rate; 897 + const struct ssp_device *ssp = drv_data->ssp; 898 + 899 + rate = min_t(int, ssp_clk, rate); 901 900 902 901 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 903 902 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; ··· 915 908 struct spi_transfer *transfer = NULL; 916 909 struct spi_transfer *previous = NULL; 917 910 struct chip_data *chip = NULL; 918 - struct ssp_device *ssp = drv_data->ssp; 919 911 void __iomem *reg = drv_data->ioaddr; 920 912 u32 clk_div = 0; 921 913 u8 bits = 0; ··· 1011 1005 if (transfer->bits_per_word) 1012 1006 bits = transfer->bits_per_word; 1013 1007 1014 - clk_div = ssp_get_clk_div(ssp, speed); 1008 + clk_div = ssp_get_clk_div(drv_data, speed); 1015 1009 1016 1010 if (bits <= 8) { 1017 1011 drv_data->n_bytes = 1; ··· 1220 1214 struct pxa2xx_spi_chip *chip_info = NULL; 1221 1215 struct chip_data *chip; 1222 1216 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1223 - struct ssp_device *ssp = drv_data->ssp; 1224 1217 unsigned int clk_div; 1225 1218 uint tx_thres = TX_THRESH_DFLT; 1226 1219 uint rx_thres = RX_THRESH_DFLT; ··· 1301 1296 } 1302 1297 } 1303 1298 1304 - clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); 1299 + clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 1305 1300 chip->speed_hz = spi->max_speed_hz; 1306 1301 1307 1302 chip->cr0 = clk_div ··· 1317 1312 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1318 1313 if (!pxa25x_ssp_comp(drv_data)) 1319 1314 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1320 - clk_get_rate(ssp->clk) 1315 + drv_data->max_clk_rate 1321 1316 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 1322 1317 chip->enable_dma ? "DMA" : "PIO"); 1323 1318 else 1324 1319 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1325 - clk_get_rate(ssp->clk) / 2 1320 + drv_data->max_clk_rate / 2 1326 1321 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1327 1322 chip->enable_dma ? "DMA" : "PIO"); 1328 1323 ··· 1475 1470 } 1476 1471 1477 1472 /* Enable SOC clock */ 1478 - clk_enable(ssp->clk); 1473 + clk_prepare_enable(ssp->clk); 1474 + 1475 + drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1479 1476 1480 1477 /* Load default SSP configuration */ 1481 1478 write_SSCR0(0, drv_data->ioaddr); ··· 1506 1499 return status; 1507 1500 1508 1501 out_error_clock_enabled: 1509 - clk_disable(ssp->clk); 1502 + clk_disable_unprepare(ssp->clk); 1510 1503 1511 1504 out_error_dma_alloc: 1512 1505 if (drv_data->tx_channel != -1) ··· 1534 1527 1535 1528 /* Disable the SSP at the peripheral and SOC level */ 1536 1529 write_SSCR0(0, drv_data->ioaddr); 1537 - clk_disable(ssp->clk); 1530 + clk_disable_unprepare(ssp->clk); 1538 1531 1539 1532 /* Release DMA */ 1540 1533 if (drv_data->master_info->enable_dma) { ··· 1578 1571 if (status != 0) 1579 1572 return status; 1580 1573 write_SSCR0(0, drv_data->ioaddr); 1581 - clk_disable(ssp->clk); 1574 + clk_disable_unprepare(ssp->clk); 1582 1575 1583 1576 return 0; 1584 1577 } ··· 1597 1590 DRCMR_MAPVLD | drv_data->tx_channel; 1598 1591 1599 1592 /* Enable the SSP clock */ 1600 - clk_enable(ssp->clk); 1593 + clk_prepare_enable(ssp->clk); 1601 1594 1602 1595 /* Start the queue running */ 1603 1596 status = spi_master_resume(drv_data->master);
-18
include/linux/spi/pxa2xx_spi.h
··· 133 133 { 134 134 } 135 135 136 - /* 137 - * The CE4100 does not have the clk framework implemented and SPI clock can 138 - * not be switched on/off or the divider changed. 139 - */ 140 - static inline void clk_disable(struct clk *clk) 141 - { 142 - } 143 - 144 - static inline int clk_enable(struct clk *clk) 145 - { 146 - return 0; 147 - } 148 - 149 - static inline unsigned long clk_get_rate(struct clk *clk) 150 - { 151 - return 3686400; 152 - } 153 - 154 136 #endif 155 137 #endif