tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt

Armv8 Juno/FVP updates for v6.2

Just few addtions including updates to cache information on various
platforms to align well with the bindings, addition of cache information
on FVP Rev C model, addition of SPE to Foundation model and updates to
LED node names.

* tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: align LED node names with dtschema
arm64: dts: fvp: Add information about L1 and L2 caches
arm64: dts: fvp: Add SPE to Foundation FVP
arm64: dts: Update cache properties for Arm Ltd platforms
arm64: dts: juno: Add thermal critical trip points

Link: https://lore.kernel.org/r/20221129115111.2464233-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 33423a8b 7b16ab92

+110 -8
+8 -8
arch/arm/boot/dts/vexpress-v2m.dtsi
··· 383 383 leds { 384 384 compatible = "gpio-leds"; 385 385 386 - user1 { 386 + led-user1 { 387 387 label = "v2m:green:user1"; 388 388 gpios = <&v2m_led_gpios 0 0>; 389 389 linux,default-trigger = "heartbeat"; 390 390 }; 391 391 392 - user2 { 392 + led-user2 { 393 393 label = "v2m:green:user2"; 394 394 gpios = <&v2m_led_gpios 1 0>; 395 395 linux,default-trigger = "mmc0"; 396 396 }; 397 397 398 - user3 { 398 + led-user3 { 399 399 label = "v2m:green:user3"; 400 400 gpios = <&v2m_led_gpios 2 0>; 401 401 linux,default-trigger = "cpu0"; 402 402 }; 403 403 404 - user4 { 404 + led-user4 { 405 405 label = "v2m:green:user4"; 406 406 gpios = <&v2m_led_gpios 3 0>; 407 407 linux,default-trigger = "cpu1"; 408 408 }; 409 409 410 - user5 { 410 + led-user5 { 411 411 label = "v2m:green:user5"; 412 412 gpios = <&v2m_led_gpios 4 0>; 413 413 linux,default-trigger = "cpu2"; 414 414 }; 415 415 416 - user6 { 416 + led-user6 { 417 417 label = "v2m:green:user6"; 418 418 gpios = <&v2m_led_gpios 5 0>; 419 419 linux,default-trigger = "cpu3"; 420 420 }; 421 421 422 - user7 { 422 + led-user7 { 423 423 label = "v2m:green:user7"; 424 424 gpios = <&v2m_led_gpios 6 0>; 425 425 linux,default-trigger = "cpu4"; 426 426 }; 427 427 428 - user8 { 428 + led-user8 { 429 429 label = "v2m:green:user8"; 430 430 gpios = <&v2m_led_gpios 7 0>; 431 431 linux,default-trigger = "cpu5";
+1
arch/arm64/boot/dts/arm/corstone1000.dtsi
··· 53 53 54 54 L2_0: l2-cache0 { 55 55 compatible = "cache"; 56 + cache-unified; 56 57 cache-level = <2>; 57 58 cache-size = <0x80000>; 58 59 cache-line-size = <64>;
+6
arch/arm64/boot/dts/arm/foundation-v8.dtsi
··· 58 58 59 59 L2_0: l2-cache0 { 60 60 compatible = "cache"; 61 + cache-level = <2>; 61 62 }; 62 63 }; 63 64 ··· 83 82 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 84 83 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 85 84 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 85 + }; 86 + 87 + spe-pmu { 88 + compatible = "arm,statistical-profiling-extension-v1"; 89 + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 86 90 }; 87 91 88 92 watchdog@2a440000 {
+73
arch/arm64/boot/dts/arm/fvp-base-revc.dts
··· 47 47 compatible = "arm,armv8"; 48 48 reg = <0x0 0x000>; 49 49 enable-method = "psci"; 50 + i-cache-size = <0x8000>; 51 + i-cache-line-size = <64>; 52 + i-cache-sets = <256>; 53 + d-cache-size = <0x8000>; 54 + d-cache-line-size = <64>; 55 + d-cache-sets = <256>; 56 + next-level-cache = <&C0_L2>; 50 57 }; 51 58 cpu1: cpu@100 { 52 59 device_type = "cpu"; 53 60 compatible = "arm,armv8"; 54 61 reg = <0x0 0x100>; 55 62 enable-method = "psci"; 63 + i-cache-size = <0x8000>; 64 + i-cache-line-size = <64>; 65 + i-cache-sets = <256>; 66 + d-cache-size = <0x8000>; 67 + d-cache-line-size = <64>; 68 + d-cache-sets = <256>; 69 + next-level-cache = <&C0_L2>; 56 70 }; 57 71 cpu2: cpu@200 { 58 72 device_type = "cpu"; 59 73 compatible = "arm,armv8"; 60 74 reg = <0x0 0x200>; 61 75 enable-method = "psci"; 76 + i-cache-size = <0x8000>; 77 + i-cache-line-size = <64>; 78 + i-cache-sets = <256>; 79 + d-cache-size = <0x8000>; 80 + d-cache-line-size = <64>; 81 + d-cache-sets = <256>; 82 + next-level-cache = <&C0_L2>; 62 83 }; 63 84 cpu3: cpu@300 { 64 85 device_type = "cpu"; 65 86 compatible = "arm,armv8"; 66 87 reg = <0x0 0x300>; 67 88 enable-method = "psci"; 89 + i-cache-size = <0x8000>; 90 + i-cache-line-size = <64>; 91 + i-cache-sets = <256>; 92 + d-cache-size = <0x8000>; 93 + d-cache-line-size = <64>; 94 + d-cache-sets = <256>; 95 + next-level-cache = <&C0_L2>; 68 96 }; 69 97 cpu4: cpu@10000 { 70 98 device_type = "cpu"; 71 99 compatible = "arm,armv8"; 72 100 reg = <0x0 0x10000>; 73 101 enable-method = "psci"; 102 + i-cache-size = <0x8000>; 103 + i-cache-line-size = <64>; 104 + i-cache-sets = <256>; 105 + d-cache-size = <0x8000>; 106 + d-cache-line-size = <64>; 107 + d-cache-sets = <256>; 108 + next-level-cache = <&C1_L2>; 74 109 }; 75 110 cpu5: cpu@10100 { 76 111 device_type = "cpu"; 77 112 compatible = "arm,armv8"; 78 113 reg = <0x0 0x10100>; 79 114 enable-method = "psci"; 115 + i-cache-size = <0x8000>; 116 + i-cache-line-size = <64>; 117 + i-cache-sets = <256>; 118 + d-cache-size = <0x8000>; 119 + d-cache-line-size = <64>; 120 + d-cache-sets = <256>; 121 + next-level-cache = <&C1_L2>; 80 122 }; 81 123 cpu6: cpu@10200 { 82 124 device_type = "cpu"; 83 125 compatible = "arm,armv8"; 84 126 reg = <0x0 0x10200>; 85 127 enable-method = "psci"; 128 + i-cache-size = <0x8000>; 129 + i-cache-line-size = <64>; 130 + i-cache-sets = <256>; 131 + d-cache-size = <0x8000>; 132 + d-cache-line-size = <64>; 133 + d-cache-sets = <256>; 134 + next-level-cache = <&C1_L2>; 86 135 }; 87 136 cpu7: cpu@10300 { 88 137 device_type = "cpu"; 89 138 compatible = "arm,armv8"; 90 139 reg = <0x0 0x10300>; 91 140 enable-method = "psci"; 141 + i-cache-size = <0x8000>; 142 + i-cache-line-size = <64>; 143 + i-cache-sets = <256>; 144 + d-cache-size = <0x8000>; 145 + d-cache-line-size = <64>; 146 + d-cache-sets = <256>; 147 + next-level-cache = <&C1_L2>; 148 + }; 149 + C0_L2: l2-cache0 { 150 + compatible = "cache"; 151 + cache-size = <0x80000>; 152 + cache-line-size = <64>; 153 + cache-sets = <512>; 154 + cache-level = <2>; 155 + cache-unified; 156 + }; 157 + 158 + C1_L2: l2-cache1 { 159 + compatible = "cache"; 160 + cache-size = <0x80000>; 161 + cache-line-size = <64>; 162 + cache-sets = <512>; 163 + cache-level = <2>; 164 + cache-unified; 92 165 }; 93 166 }; 94 167
+14
arch/arm64/boot/dts/arm/juno-base.dtsi
··· 751 751 polling-delay = <1000>; 752 752 polling-delay-passive = <100>; 753 753 thermal-sensors = <&scpi_sensors0 0>; 754 + trips { 755 + pmic_crit0: trip0 { 756 + temperature = <90000>; 757 + hysteresis = <2000>; 758 + type = "critical"; 759 + }; 760 + }; 754 761 }; 755 762 756 763 soc { 757 764 polling-delay = <1000>; 758 765 polling-delay-passive = <100>; 759 766 thermal-sensors = <&scpi_sensors0 3>; 767 + trips { 768 + soc_crit0: trip0 { 769 + temperature = <80000>; 770 + hysteresis = <2000>; 771 + type = "critical"; 772 + }; 773 + }; 760 774 }; 761 775 762 776 big_cluster_thermal_zone: big-cluster {
+2
arch/arm64/boot/dts/arm/juno-r1.dts
··· 189 189 190 190 A57_L2: l2-cache0 { 191 191 compatible = "cache"; 192 + cache-unified; 192 193 cache-size = <0x200000>; 193 194 cache-line-size = <64>; 194 195 cache-sets = <2048>; ··· 198 197 199 198 A53_L2: l2-cache1 { 200 199 compatible = "cache"; 200 + cache-unified; 201 201 cache-size = <0x100000>; 202 202 cache-line-size = <64>; 203 203 cache-sets = <1024>;
+2
arch/arm64/boot/dts/arm/juno-r2.dts
··· 195 195 196 196 A72_L2: l2-cache0 { 197 197 compatible = "cache"; 198 + cache-unified; 198 199 cache-size = <0x200000>; 199 200 cache-line-size = <64>; 200 201 cache-sets = <2048>; ··· 204 203 205 204 A53_L2: l2-cache1 { 206 205 compatible = "cache"; 206 + cache-unified; 207 207 cache-size = <0x100000>; 208 208 cache-line-size = <64>; 209 209 cache-sets = <1024>;
+2
arch/arm64/boot/dts/arm/juno.dts
··· 194 194 195 195 A57_L2: l2-cache0 { 196 196 compatible = "cache"; 197 + cache-unified; 197 198 cache-size = <0x200000>; 198 199 cache-line-size = <64>; 199 200 cache-sets = <2048>; ··· 203 202 204 203 A53_L2: l2-cache1 { 205 204 compatible = "cache"; 205 + cache-unified; 206 206 cache-size = <0x100000>; 207 207 cache-line-size = <64>; 208 208 cache-sets = <1024>;
+1
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
··· 71 71 72 72 L2_0: l2-cache0 { 73 73 compatible = "cache"; 74 + cache-level = <2>; 74 75 }; 75 76 }; 76 77
+1
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
··· 57 57 58 58 L2_0: l2-cache0 { 59 59 compatible = "cache"; 60 + cache-level = <2>; 60 61 }; 61 62 }; 62 63