tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-msm-next-2021-06-23b' of https://gitlab.freedesktop.org/drm/msm into drm-next
* devcoredump support for display errors
* dpu: irq cleanup/refactor
* dpu: dt bindings conversion to yaml
* dsi: dt bindings conversion to yaml
* mdp5: alpha/blend_mode/zpos support
* a6xx: cached coherent buffer support
* a660 support
* gpu iova fault improvements:
- info about which block triggered the fault, etc
- generation of gpu devcoredump on fault
* assortment of other cleanups and fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs4=qsGBBbyn-4JWqW4-YUSTKh67X3DsPQ=T2D9aXKqNA@mail.gmail.com
+7160
-6231
+146
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+146
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MSM Display Port Controller
8
+
9
+
maintainers:
10
+
- Kuogee Hsieh <khsieh@codeaurora.org>
11
+
12
+
description: |
13
+
Device tree bindings for DisplayPort host controller for MSM targets
14
+
that are compatible with VESA DisplayPort interface specification.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sc7180-dp
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
interrupts:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
items:
29
+
- description: AHB clock to enable register access
30
+
- description: Display Port AUX clock
31
+
- description: Display Port Link clock
32
+
- description: Link interface clock between DP and PHY
33
+
- description: Display Port Pixel clock
34
+
35
+
clock-names:
36
+
items:
37
+
- const: core_iface
38
+
- const: core_aux
39
+
- const: ctrl_link
40
+
- const: ctrl_link_iface
41
+
- const: stream_pixel
42
+
43
+
assigned-clocks:
44
+
items:
45
+
- description: link clock source
46
+
- description: pixel clock source
47
+
48
+
assigned-clock-parents:
49
+
items:
50
+
- description: phy 0 parent
51
+
- description: phy 1 parent
52
+
53
+
phys:
54
+
maxItems: 1
55
+
56
+
phy-names:
57
+
items:
58
+
- const: dp
59
+
60
+
operating-points-v2:
61
+
maxItems: 1
62
+
63
+
power-domains:
64
+
maxItems: 1
65
+
66
+
"#sound-dai-cells":
67
+
const: 0
68
+
69
+
ports:
70
+
$ref: /schemas/graph.yaml#/properties/ports
71
+
properties:
72
+
port@0:
73
+
$ref: /schemas/graph.yaml#/properties/port
74
+
description: Input endpoint of the controller
75
+
76
+
port@1:
77
+
$ref: /schemas/graph.yaml#/properties/port
78
+
description: Output endpoint of the controller
79
+
80
+
required:
81
+
- compatible
82
+
- reg
83
+
- interrupts
84
+
- clocks
85
+
- clock-names
86
+
- phys
87
+
- phy-names
88
+
- "#sound-dai-cells"
89
+
- power-domains
90
+
- ports
91
+
92
+
additionalProperties: false
93
+
94
+
examples:
95
+
- |
96
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
97
+
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
98
+
#include <dt-bindings/power/qcom-aoss-qmp.h>
99
+
#include <dt-bindings/power/qcom-rpmpd.h>
100
+
101
+
displayport-controller@ae90000 {
102
+
compatible = "qcom,sc7180-dp";
103
+
reg = <0xae90000 0x1400>;
104
+
interrupt-parent = <&mdss>;
105
+
interrupts = <12>;
106
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
107
+
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
108
+
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
109
+
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
110
+
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
111
+
clock-names = "core_iface", "core_aux",
112
+
"ctrl_link",
113
+
"ctrl_link_iface", "stream_pixel";
114
+
115
+
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
116
+
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
117
+
118
+
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
119
+
120
+
phys = <&dp_phy>;
121
+
phy-names = "dp";
122
+
123
+
#sound-dai-cells = <0>;
124
+
125
+
power-domains = <&rpmhpd SC7180_CX>;
126
+
127
+
ports {
128
+
#address-cells = <1>;
129
+
#size-cells = <0>;
130
+
131
+
port@0 {
132
+
reg = <0>;
133
+
endpoint {
134
+
remote-endpoint = <&dpu_intf0_out>;
135
+
};
136
+
};
137
+
138
+
port@1 {
139
+
reg = <1>;
140
+
endpoint {
141
+
remote-endpoint = <&typec>;
142
+
};
143
+
};
144
+
};
145
+
};
146
+
...
+228
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+228
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DPU dt properties for SC7180 target
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
description: |
13
+
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14
+
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15
+
bindings of MDSS and DPU are mentioned for SC7180 target.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- const: qcom,sc7180-mdss
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
reg-names:
26
+
const: mdss
27
+
28
+
power-domains:
29
+
maxItems: 1
30
+
31
+
clocks:
32
+
items:
33
+
- description: Display AHB clock from gcc
34
+
- description: Display AHB clock from dispcc
35
+
- description: Display core clock
36
+
37
+
clock-names:
38
+
items:
39
+
- const: iface
40
+
- const: ahb
41
+
- const: core
42
+
43
+
interrupts:
44
+
maxItems: 1
45
+
46
+
interrupt-controller: true
47
+
48
+
"#address-cells": true
49
+
50
+
"#size-cells": true
51
+
52
+
"#interrupt-cells":
53
+
const: 1
54
+
55
+
iommus:
56
+
items:
57
+
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58
+
59
+
ranges: true
60
+
61
+
interconnects:
62
+
items:
63
+
- description: Interconnect path specifying the port ids for data bus
64
+
65
+
interconnect-names:
66
+
const: mdp0-mem
67
+
68
+
patternProperties:
69
+
"^display-controller@[0-9a-f]+$":
70
+
type: object
71
+
description: Node containing the properties of DPU.
72
+
73
+
properties:
74
+
compatible:
75
+
items:
76
+
- const: qcom,sc7180-dpu
77
+
78
+
reg:
79
+
items:
80
+
- description: Address offset and size for mdp register set
81
+
- description: Address offset and size for vbif register set
82
+
83
+
reg-names:
84
+
items:
85
+
- const: mdp
86
+
- const: vbif
87
+
88
+
clocks:
89
+
items:
90
+
- description: Display hf axi clock
91
+
- description: Display ahb clock
92
+
- description: Display rotator clock
93
+
- description: Display lut clock
94
+
- description: Display core clock
95
+
- description: Display vsync clock
96
+
97
+
clock-names:
98
+
items:
99
+
- const: bus
100
+
- const: iface
101
+
- const: rot
102
+
- const: lut
103
+
- const: core
104
+
- const: vsync
105
+
106
+
interrupts:
107
+
maxItems: 1
108
+
109
+
power-domains:
110
+
maxItems: 1
111
+
112
+
operating-points-v2: true
113
+
114
+
ports:
115
+
$ref: /schemas/graph.yaml#/properties/ports
116
+
description: |
117
+
Contains the list of output ports from DPU device. These ports
118
+
connect to interfaces that are external to the DPU hardware,
119
+
such as DSI, DP etc. Each output port contains an endpoint that
120
+
describes how it is connected to an external interface.
121
+
122
+
properties:
123
+
port@0:
124
+
$ref: /schemas/graph.yaml#/properties/port
125
+
description: DPU_INTF1 (DSI1)
126
+
127
+
port@2:
128
+
$ref: /schemas/graph.yaml#/properties/port
129
+
description: DPU_INTF0 (DP)
130
+
131
+
required:
132
+
- port@0
133
+
134
+
required:
135
+
- compatible
136
+
- reg
137
+
- reg-names
138
+
- clocks
139
+
- interrupts
140
+
- power-domains
141
+
- operating-points-v2
142
+
- ports
143
+
144
+
required:
145
+
- compatible
146
+
- reg
147
+
- reg-names
148
+
- power-domains
149
+
- clocks
150
+
- interrupts
151
+
- interrupt-controller
152
+
- iommus
153
+
- ranges
154
+
155
+
additionalProperties: false
156
+
157
+
examples:
158
+
- |
159
+
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
160
+
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
161
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
162
+
#include <dt-bindings/interconnect/qcom,sdm845.h>
163
+
#include <dt-bindings/power/qcom-rpmpd.h>
164
+
165
+
display-subsystem@ae00000 {
166
+
#address-cells = <1>;
167
+
#size-cells = <1>;
168
+
compatible = "qcom,sc7180-mdss";
169
+
reg = <0xae00000 0x1000>;
170
+
reg-names = "mdss";
171
+
power-domains = <&dispcc MDSS_GDSC>;
172
+
clocks = <&gcc GCC_DISP_AHB_CLK>,
173
+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
174
+
<&dispcc DISP_CC_MDSS_MDP_CLK>;
175
+
clock-names = "iface", "ahb", "core";
176
+
177
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
178
+
interrupt-controller;
179
+
#interrupt-cells = <1>;
180
+
181
+
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
182
+
interconnect-names = "mdp0-mem";
183
+
184
+
iommus = <&apps_smmu 0x800 0x2>;
185
+
ranges;
186
+
187
+
display-controller@ae01000 {
188
+
compatible = "qcom,sc7180-dpu";
189
+
reg = <0x0ae01000 0x8f000>,
190
+
<0x0aeb0000 0x2008>;
191
+
192
+
reg-names = "mdp", "vbif";
193
+
194
+
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
195
+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
196
+
<&dispcc DISP_CC_MDSS_ROT_CLK>,
197
+
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
198
+
<&dispcc DISP_CC_MDSS_MDP_CLK>,
199
+
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
200
+
clock-names = "bus", "iface", "rot", "lut", "core",
201
+
"vsync";
202
+
203
+
interrupt-parent = <&mdss>;
204
+
interrupts = <0>;
205
+
power-domains = <&rpmhpd SC7180_CX>;
206
+
operating-points-v2 = <&mdp_opp_table>;
207
+
208
+
ports {
209
+
#address-cells = <1>;
210
+
#size-cells = <0>;
211
+
212
+
port@0 {
213
+
reg = <0>;
214
+
dpu_intf1_out: endpoint {
215
+
remote-endpoint = <&dsi0_in>;
216
+
};
217
+
};
218
+
219
+
port@2 {
220
+
reg = <2>;
221
+
dpu_intf0_out: endpoint {
222
+
remote-endpoint = <&dp_in>;
223
+
};
224
+
};
225
+
};
226
+
};
227
+
};
228
+
...
+212
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+212
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DPU dt properties for SDM845 target
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
description: |
13
+
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14
+
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15
+
bindings of MDSS and DPU are mentioned for SDM845 target.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- const: qcom,sdm845-mdss
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
reg-names:
26
+
const: mdss
27
+
28
+
power-domains:
29
+
maxItems: 1
30
+
31
+
clocks:
32
+
items:
33
+
- description: Display AHB clock from gcc
34
+
- description: Display AXI clock
35
+
- description: Display core clock
36
+
37
+
clock-names:
38
+
items:
39
+
- const: iface
40
+
- const: bus
41
+
- const: core
42
+
43
+
interrupts:
44
+
maxItems: 1
45
+
46
+
interrupt-controller: true
47
+
48
+
"#address-cells": true
49
+
50
+
"#size-cells": true
51
+
52
+
"#interrupt-cells":
53
+
const: 1
54
+
55
+
iommus:
56
+
items:
57
+
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58
+
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
59
+
60
+
ranges: true
61
+
62
+
patternProperties:
63
+
"^display-controller@[0-9a-f]+$":
64
+
type: object
65
+
description: Node containing the properties of DPU.
66
+
67
+
properties:
68
+
compatible:
69
+
items:
70
+
- const: qcom,sdm845-dpu
71
+
72
+
reg:
73
+
items:
74
+
- description: Address offset and size for mdp register set
75
+
- description: Address offset and size for vbif register set
76
+
77
+
reg-names:
78
+
items:
79
+
- const: mdp
80
+
- const: vbif
81
+
82
+
clocks:
83
+
items:
84
+
- description: Display ahb clock
85
+
- description: Display axi clock
86
+
- description: Display core clock
87
+
- description: Display vsync clock
88
+
89
+
clock-names:
90
+
items:
91
+
- const: iface
92
+
- const: bus
93
+
- const: core
94
+
- const: vsync
95
+
96
+
interrupts:
97
+
maxItems: 1
98
+
99
+
power-domains:
100
+
maxItems: 1
101
+
102
+
operating-points-v2: true
103
+
ports:
104
+
$ref: /schemas/graph.yaml#/properties/ports
105
+
description: |
106
+
Contains the list of output ports from DPU device. These ports
107
+
connect to interfaces that are external to the DPU hardware,
108
+
such as DSI, DP etc. Each output port contains an endpoint that
109
+
describes how it is connected to an external interface.
110
+
111
+
properties:
112
+
port@0:
113
+
$ref: /schemas/graph.yaml#/properties/port
114
+
description: DPU_INTF1 (DSI1)
115
+
116
+
port@1:
117
+
$ref: /schemas/graph.yaml#/properties/port
118
+
description: DPU_INTF2 (DSI2)
119
+
120
+
required:
121
+
- port@0
122
+
- port@1
123
+
124
+
required:
125
+
- compatible
126
+
- reg
127
+
- reg-names
128
+
- clocks
129
+
- interrupts
130
+
- power-domains
131
+
- operating-points-v2
132
+
- ports
133
+
134
+
required:
135
+
- compatible
136
+
- reg
137
+
- reg-names
138
+
- power-domains
139
+
- clocks
140
+
- interrupts
141
+
- interrupt-controller
142
+
- iommus
143
+
- ranges
144
+
145
+
additionalProperties: false
146
+
147
+
examples:
148
+
- |
149
+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
150
+
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
151
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
152
+
#include <dt-bindings/power/qcom-rpmpd.h>
153
+
154
+
display-subsystem@ae00000 {
155
+
#address-cells = <1>;
156
+
#size-cells = <1>;
157
+
compatible = "qcom,sdm845-mdss";
158
+
reg = <0x0ae00000 0x1000>;
159
+
reg-names = "mdss";
160
+
power-domains = <&dispcc MDSS_GDSC>;
161
+
162
+
clocks = <&gcc GCC_DISP_AHB_CLK>,
163
+
<&gcc GCC_DISP_AXI_CLK>,
164
+
<&dispcc DISP_CC_MDSS_MDP_CLK>;
165
+
clock-names = "iface", "bus", "core";
166
+
167
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
168
+
interrupt-controller;
169
+
#interrupt-cells = <1>;
170
+
171
+
iommus = <&apps_smmu 0x880 0x8>,
172
+
<&apps_smmu 0xc80 0x8>;
173
+
ranges;
174
+
175
+
display-controller@ae01000 {
176
+
compatible = "qcom,sdm845-dpu";
177
+
reg = <0x0ae01000 0x8f000>,
178
+
<0x0aeb0000 0x2008>;
179
+
reg-names = "mdp", "vbif";
180
+
181
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
182
+
<&dispcc DISP_CC_MDSS_AXI_CLK>,
183
+
<&dispcc DISP_CC_MDSS_MDP_CLK>,
184
+
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
185
+
clock-names = "iface", "bus", "core", "vsync";
186
+
187
+
interrupt-parent = <&mdss>;
188
+
interrupts = <0>;
189
+
power-domains = <&rpmhpd SDM845_CX>;
190
+
operating-points-v2 = <&mdp_opp_table>;
191
+
192
+
ports {
193
+
#address-cells = <1>;
194
+
#size-cells = <0>;
195
+
196
+
port@0 {
197
+
reg = <0>;
198
+
dpu_intf1_out: endpoint {
199
+
remote-endpoint = <&dsi0_in>;
200
+
};
201
+
};
202
+
203
+
port@1 {
204
+
reg = <1>;
205
+
dpu_intf2_out: endpoint {
206
+
remote-endpoint = <&dsi1_in>;
207
+
};
208
+
};
209
+
};
210
+
};
211
+
};
212
+
...
-141
Documentation/devicetree/bindings/display/msm/dpu.txt
-141
Documentation/devicetree/bindings/display/msm/dpu.txt
···
1
-
Qualcomm Technologies, Inc. DPU KMS
2
-
3
-
Description:
4
-
5
-
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
6
-
sub-blocks like DPU display controller, DSI and DP interfaces etc.
7
-
The DPU display controller is found in SDM845 SoC.
8
-
9
-
MDSS:
10
-
Required properties:
11
-
- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12
-
- reg: physical base address and length of controller's registers.
13
-
- reg-names: register region names. The following region is required:
14
-
* "mdss"
15
-
- power-domains: a power domain consumer specifier according to
16
-
Documentation/devicetree/bindings/power/power_domain.txt
17
-
- clocks: list of clock specifiers for clocks needed by the device.
18
-
- clock-names: device clock names, must be in same order as clocks property.
19
-
The following clocks are required:
20
-
* "iface"
21
-
* "bus"
22
-
* "core"
23
-
- interrupts: interrupt signal from MDSS.
24
-
- interrupt-controller: identifies the node as an interrupt controller.
25
-
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
26
-
source, should be 1.
27
-
- iommus: phandle of iommu device node.
28
-
- #address-cells: number of address cells for the MDSS children. Should be 1.
29
-
- #size-cells: Should be 1.
30
-
- ranges: parent bus address space is the same as the child bus address space.
31
-
- interconnects : interconnect path specifier for MDSS according to
32
-
Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
33
-
2 paths corresponding to 2 AXI ports.
34
-
- interconnect-names : MDSS will have 2 port names to differentiate between the
35
-
2 interconnect paths defined with interconnect specifier.
36
-
37
-
Optional properties:
38
-
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
39
-
- assigned-clock-rates: list of clock frequencies sorted in the same order as
40
-
the assigned-clocks property.
41
-
42
-
MDP:
43
-
Required properties:
44
-
- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
45
-
- reg: physical base address and length of controller's registers.
46
-
- reg-names : register region names. The following region is required:
47
-
* "mdp"
48
-
* "vbif"
49
-
- clocks: list of clock specifiers for clocks needed by the device.
50
-
- clock-names: device clock names, must be in same order as clocks property.
51
-
The following clocks are required.
52
-
* "bus"
53
-
* "iface"
54
-
* "core"
55
-
* "vsync"
56
-
- interrupts: interrupt line from DPU to MDSS.
57
-
- ports: contains the list of output ports from DPU device. These ports connect
58
-
to interfaces that are external to the DPU hardware, such as DSI, DP etc.
59
-
60
-
Each output port contains an endpoint that describes how it is connected to an
61
-
external interface. These are described by the standard properties documented
62
-
here:
63
-
Documentation/devicetree/bindings/graph.txt
64
-
Documentation/devicetree/bindings/media/video-interfaces.txt
65
-
66
-
Port 0 -> DPU_INTF1 (DSI1)
67
-
Port 1 -> DPU_INTF2 (DSI2)
68
-
69
-
Optional properties:
70
-
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
71
-
- assigned-clock-rates: list of clock frequencies sorted in the same order as
72
-
the assigned-clocks property.
73
-
74
-
Example:
75
-
76
-
mdss: mdss@ae00000 {
77
-
compatible = "qcom,sdm845-mdss";
78
-
reg = <0xae00000 0x1000>;
79
-
reg-names = "mdss";
80
-
81
-
power-domains = <&clock_dispcc 0>;
82
-
83
-
clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
84
-
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
85
-
clock-names = "iface", "bus", "core";
86
-
87
-
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88
-
assigned-clock-rates = <300000000>;
89
-
90
-
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
91
-
interrupt-controller;
92
-
#interrupt-cells = <1>;
93
-
94
-
interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
95
-
<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
96
-
97
-
interconnect-names = "mdp0-mem", "mdp1-mem";
98
-
99
-
iommus = <&apps_iommu 0>;
100
-
101
-
#address-cells = <2>;
102
-
#size-cells = <1>;
103
-
ranges = <0 0 0xae00000 0xb2008>;
104
-
105
-
mdss_mdp: mdp@ae01000 {
106
-
compatible = "qcom,sdm845-dpu";
107
-
reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
108
-
reg-names = "mdp", "vbif";
109
-
110
-
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
111
-
<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
112
-
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
113
-
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
114
-
clock-names = "iface", "bus", "core", "vsync";
115
-
116
-
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
117
-
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
118
-
assigned-clock-rates = <0 0 300000000 19200000>;
119
-
120
-
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
121
-
122
-
ports {
123
-
#address-cells = <1>;
124
-
#size-cells = <0>;
125
-
126
-
port@0 {
127
-
reg = <0>;
128
-
dpu_intf1_out: endpoint {
129
-
remote-endpoint = <&dsi0_in>;
130
-
};
131
-
};
132
-
133
-
port@1 {
134
-
reg = <1>;
135
-
dpu_intf2_out: endpoint {
136
-
remote-endpoint = <&dsi1_in>;
137
-
};
138
-
};
139
-
};
140
-
};
141
-
};
+185
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+185
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DSI controller
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
allOf:
13
+
- $ref: "../dsi-controller.yaml#"
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- const: qcom,mdss-dsi-ctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
reg-names:
24
+
const: dsi_ctrl
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: Display byte clock
32
+
- description: Display byte interface clock
33
+
- description: Display pixel clock
34
+
- description: Display escape clock
35
+
- description: Display AHB clock
36
+
- description: Display AXI clock
37
+
38
+
clock-names:
39
+
items:
40
+
- const: byte
41
+
- const: byte_intf
42
+
- const: pixel
43
+
- const: core
44
+
- const: iface
45
+
- const: bus
46
+
47
+
phys:
48
+
maxItems: 1
49
+
50
+
phy-names:
51
+
const: dsi
52
+
53
+
"#address-cells": true
54
+
55
+
"#size-cells": true
56
+
57
+
syscon-sfpb:
58
+
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
59
+
$ref: "/schemas/types.yaml#/definitions/phandle"
60
+
61
+
qcom,dual-dsi-mode:
62
+
type: boolean
63
+
description: |
64
+
Indicates if the DSI controller is driving a panel which needs
65
+
2 DSI links.
66
+
67
+
power-domains:
68
+
maxItems: 1
69
+
70
+
operating-points-v2: true
71
+
72
+
ports:
73
+
$ref: "/schemas/graph.yaml#/properties/ports"
74
+
description: |
75
+
Contains DSI controller input and output ports as children, each
76
+
containing one endpoint subnode.
77
+
78
+
properties:
79
+
port@0:
80
+
$ref: "/schemas/graph.yaml#/properties/port"
81
+
description: |
82
+
Input endpoints of the controller.
83
+
properties:
84
+
endpoint:
85
+
$ref: /schemas/media/video-interfaces.yaml#
86
+
unevaluatedProperties: false
87
+
properties:
88
+
data-lanes:
89
+
maxItems: 4
90
+
minItems: 4
91
+
items:
92
+
enum: [ 0, 1, 2, 3 ]
93
+
94
+
port@1:
95
+
$ref: "/schemas/graph.yaml#/properties/port"
96
+
description: |
97
+
Output endpoints of the controller.
98
+
properties:
99
+
endpoint:
100
+
$ref: /schemas/media/video-interfaces.yaml#
101
+
unevaluatedProperties: false
102
+
properties:
103
+
data-lanes:
104
+
maxItems: 4
105
+
minItems: 4
106
+
items:
107
+
enum: [ 0, 1, 2, 3 ]
108
+
109
+
required:
110
+
- port@0
111
+
- port@1
112
+
113
+
required:
114
+
- compatible
115
+
- reg
116
+
- reg-names
117
+
- interrupts
118
+
- clocks
119
+
- clock-names
120
+
- phys
121
+
- phy-names
122
+
- power-domains
123
+
- operating-points-v2
124
+
- ports
125
+
126
+
additionalProperties: false
127
+
128
+
examples:
129
+
- |
130
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
131
+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
132
+
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
133
+
#include <dt-bindings/power/qcom-rpmpd.h>
134
+
135
+
dsi@ae94000 {
136
+
compatible = "qcom,mdss-dsi-ctrl";
137
+
reg = <0x0ae94000 0x400>;
138
+
reg-names = "dsi_ctrl";
139
+
140
+
#address-cells = <1>;
141
+
#size-cells = <0>;
142
+
143
+
interrupt-parent = <&mdss>;
144
+
interrupts = <4>;
145
+
146
+
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
147
+
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
148
+
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
149
+
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
150
+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
151
+
<&dispcc DISP_CC_MDSS_AXI_CLK>;
152
+
clock-names = "byte",
153
+
"byte_intf",
154
+
"pixel",
155
+
"core",
156
+
"iface",
157
+
"bus";
158
+
159
+
phys = <&dsi0_phy>;
160
+
phy-names = "dsi";
161
+
162
+
power-domains = <&rpmhpd SC7180_CX>;
163
+
operating-points-v2 = <&dsi_opp_table>;
164
+
165
+
ports {
166
+
#address-cells = <1>;
167
+
#size-cells = <0>;
168
+
169
+
port@0 {
170
+
reg = <0>;
171
+
dsi0_in: endpoint {
172
+
remote-endpoint = <&dpu_intf1_out>;
173
+
};
174
+
};
175
+
176
+
port@1 {
177
+
reg = <1>;
178
+
dsi0_out: endpoint {
179
+
remote-endpoint = <&sn65dsi86_in>;
180
+
data-lanes = <0 1 2 3>;
181
+
};
182
+
};
183
+
};
184
+
};
185
+
...
+68
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
+68
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DSI 10nm PHY
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
allOf:
13
+
- $ref: dsi-phy-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- const: qcom,dsi-phy-10nm
19
+
- const: qcom,dsi-phy-10nm-8998
20
+
21
+
reg:
22
+
items:
23
+
- description: dsi phy register set
24
+
- description: dsi phy lane register set
25
+
- description: dsi pll register set
26
+
27
+
reg-names:
28
+
items:
29
+
- const: dsi_phy
30
+
- const: dsi_phy_lane
31
+
- const: dsi_pll
32
+
33
+
vdds-supply:
34
+
description: |
35
+
Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
36
+
connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- reg-names
42
+
- vdds-supply
43
+
44
+
unevaluatedProperties: false
45
+
46
+
examples:
47
+
- |
48
+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
49
+
#include <dt-bindings/clock/qcom,rpmh.h>
50
+
51
+
dsi-phy@ae94400 {
52
+
compatible = "qcom,dsi-phy-10nm";
53
+
reg = <0x0ae94400 0x200>,
54
+
<0x0ae94600 0x280>,
55
+
<0x0ae94a00 0x1e0>;
56
+
reg-names = "dsi_phy",
57
+
"dsi_phy_lane",
58
+
"dsi_pll";
59
+
60
+
#clock-cells = <1>;
61
+
#phy-cells = <0>;
62
+
63
+
vdds-supply = <&vdda_mipi_dsi0_pll>;
64
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
65
+
<&rpmhcc RPMH_CXO_CLK>;
66
+
clock-names = "iface", "ref";
67
+
};
68
+
...
+66
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+66
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DSI 14nm PHY
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
allOf:
13
+
- $ref: dsi-phy-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- const: qcom,dsi-phy-14nm
19
+
- const: qcom,dsi-phy-14nm-660
20
+
21
+
reg:
22
+
items:
23
+
- description: dsi phy register set
24
+
- description: dsi phy lane register set
25
+
- description: dsi pll register set
26
+
27
+
reg-names:
28
+
items:
29
+
- const: dsi_phy
30
+
- const: dsi_phy_lane
31
+
- const: dsi_pll
32
+
33
+
vcca-supply:
34
+
description: Phandle to vcca regulator device node.
35
+
36
+
required:
37
+
- compatible
38
+
- reg
39
+
- reg-names
40
+
- vcca-supply
41
+
42
+
unevaluatedProperties: false
43
+
44
+
examples:
45
+
- |
46
+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
47
+
#include <dt-bindings/clock/qcom,rpmh.h>
48
+
49
+
dsi-phy@ae94400 {
50
+
compatible = "qcom,dsi-phy-14nm";
51
+
reg = <0x0ae94400 0x200>,
52
+
<0x0ae94600 0x280>,
53
+
<0x0ae94a00 0x1e0>;
54
+
reg-names = "dsi_phy",
55
+
"dsi_phy_lane",
56
+
"dsi_pll";
57
+
58
+
#clock-cells = <1>;
59
+
#phy-cells = <0>;
60
+
61
+
vcca-supply = <&vcca_reg>;
62
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
63
+
<&rpmhcc RPMH_CXO_CLK>;
64
+
clock-names = "iface", "ref";
65
+
};
66
+
...
+71
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
+71
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DSI 20nm PHY
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
allOf:
13
+
- $ref: dsi-phy-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- const: qcom,dsi-phy-20nm
19
+
20
+
reg:
21
+
items:
22
+
- description: dsi pll register set
23
+
- description: dsi phy register set
24
+
- description: dsi phy regulator register set
25
+
26
+
reg-names:
27
+
items:
28
+
- const: dsi_pll
29
+
- const: dsi_phy
30
+
- const: dsi_phy_regulator
31
+
32
+
vcca-supply:
33
+
description: Phandle to vcca regulator device node.
34
+
35
+
vddio-supply:
36
+
description: Phandle to vdd-io regulator device node.
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- reg-names
42
+
- vddio-supply
43
+
- vcca-supply
44
+
45
+
unevaluatedProperties: false
46
+
47
+
examples:
48
+
- |
49
+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
50
+
#include <dt-bindings/clock/qcom,rpmh.h>
51
+
52
+
dsi-phy@fd922a00 {
53
+
compatible = "qcom,dsi-phy-20nm";
54
+
reg = <0xfd922a00 0xd4>,
55
+
<0xfd922b00 0x2b0>,
56
+
<0xfd922d80 0x7b>;
57
+
reg-names = "dsi_pll",
58
+
"dsi_phy",
59
+
"dsi_phy_regulator";
60
+
61
+
#clock-cells = <1>;
62
+
#phy-cells = <0>;
63
+
64
+
vcca-supply = <&vcca_reg>;
65
+
vddio-supply = <&vddio_reg>;
66
+
67
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
68
+
<&rpmhcc RPMH_CXO_CLK>;
69
+
clock-names = "iface", "ref";
70
+
};
71
+
...
+68
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
+68
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display DSI 28nm PHY
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
allOf:
13
+
- $ref: dsi-phy-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- const: qcom,dsi-phy-28nm-hpm
19
+
- const: qcom,dsi-phy-28nm-lp
20
+
- const: qcom,dsi-phy-28nm-8960
21
+
22
+
reg:
23
+
items:
24
+
- description: dsi pll register set
25
+
- description: dsi phy register set
26
+
- description: dsi phy regulator register set
27
+
28
+
reg-names:
29
+
items:
30
+
- const: dsi_pll
31
+
- const: dsi_phy
32
+
- const: dsi_phy_regulator
33
+
34
+
vddio-supply:
35
+
description: Phandle to vdd-io regulator device node.
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- reg-names
41
+
- vddio-supply
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
48
+
#include <dt-bindings/clock/qcom,rpmh.h>
49
+
50
+
dsi-phy@fd922a00 {
51
+
compatible = "qcom,dsi-phy-28nm-lp";
52
+
reg = <0xfd922a00 0xd4>,
53
+
<0xfd922b00 0x2b0>,
54
+
<0xfd922d80 0x7b>;
55
+
reg-names = "dsi_pll",
56
+
"dsi_phy",
57
+
"dsi_phy_regulator";
58
+
59
+
#clock-cells = <1>;
60
+
#phy-cells = <0>;
61
+
62
+
vddio-supply = <&vddio_reg>;
63
+
64
+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
65
+
<&rpmhcc RPMH_CXO_CLK>;
66
+
clock-names = "iface", "ref";
67
+
};
68
+
...
+40
Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
+40
Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Description of Qualcomm Display DSI PHY common dt properties
8
+
9
+
maintainers:
10
+
- Krishna Manikandan <mkrishn@codeaurora.org>
11
+
12
+
description: |
13
+
This defines the DSI PHY dt properties which are common for all
14
+
dsi phy versions.
15
+
16
+
properties:
17
+
"#clock-cells":
18
+
const: 1
19
+
20
+
"#phy-cells":
21
+
const: 0
22
+
23
+
clocks:
24
+
items:
25
+
- description: Display AHB clock
26
+
- description: Board XO source
27
+
28
+
clock-names:
29
+
items:
30
+
- const: iface
31
+
- const: ref
32
+
33
+
required:
34
+
- clocks
35
+
- clock-names
36
+
- "#clock-cells"
37
+
- "#phy-cells"
38
+
39
+
additionalProperties: true
40
+
...
-249
Documentation/devicetree/bindings/display/msm/dsi.txt
-249
Documentation/devicetree/bindings/display/msm/dsi.txt
···
1
-
Qualcomm Technologies Inc. adreno/snapdragon DSI output
2
-
3
-
DSI Controller:
4
-
Required properties:
5
-
- compatible:
6
-
* "qcom,mdss-dsi-ctrl"
7
-
- reg: Physical base address and length of the registers of controller
8
-
- reg-names: The names of register regions. The following regions are required:
9
-
* "dsi_ctrl"
10
-
- interrupts: The interrupt signal from the DSI block.
11
-
- power-domains: Should be <&mmcc MDSS_GDSC>.
12
-
- clocks: Phandles to device clocks.
13
-
- clock-names: the following clocks are required:
14
-
* "mdp_core"
15
-
* "iface"
16
-
* "bus"
17
-
* "core_mmss"
18
-
* "byte"
19
-
* "pixel"
20
-
* "core"
21
-
For DSIv2, we need an additional clock:
22
-
* "src"
23
-
For DSI6G v2.0 onwards, we need also need the clock:
24
-
* "byte_intf"
25
-
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26
-
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27
-
by a DSI PHY block. See [1] for details on clock bindings.
28
-
- vdd-supply: phandle to vdd regulator device node
29
-
- vddio-supply: phandle to vdd-io regulator device node
30
-
- vdda-supply: phandle to vdda regulator device node
31
-
- phys: phandle to DSI PHY device node
32
-
- phy-names: the name of the corresponding PHY device
33
-
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34
-
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
35
-
an endpoint subnode as defined in [2] and [3].
36
-
37
-
Optional properties:
38
-
- panel@0: Node of panel connected to this DSI controller.
39
-
See files in [4] for each supported panel.
40
-
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41
-
driving a panel which needs 2 DSI links.
42
-
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43
-
the master link of the 2-DSI panel.
44
-
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45
-
driving a 2-DSI panel whose 2 links need receive command simultaneously.
46
-
- pinctrl-names: the pin control state names; should contain "default"
47
-
- pinctrl-0: the default pinctrl state (active)
48
-
- pinctrl-n: the "sleep" pinctrl state
49
-
- ports: contains DSI controller input and output ports as children, each
50
-
containing one endpoint subnode.
51
-
52
-
DSI Endpoint properties:
53
-
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
54
-
input endpoint. For port@1, set to the MDP interface output. See [2] for
55
-
device graph info.
56
-
57
-
- data-lanes: this describes how the physical DSI data lanes are mapped
58
-
to the logical lanes on the given platform. The value contained in
59
-
index n describes what physical lane is mapped to the logical lane n
60
-
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
61
-
and can't be changed. Hence, they aren't a part of the DT bindings. See
62
-
[3] for more info on the data-lanes property.
63
-
64
-
For example:
65
-
66
-
data-lanes = <3 0 1 2>;
67
-
68
-
The above mapping describes that the logical data lane DATA0 is mapped to
69
-
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
70
-
to phys DATA1 and logic DATA3 to phys DATA2.
71
-
72
-
There are only a limited number of physical to logical mappings possible:
73
-
<0 1 2 3>
74
-
<1 2 3 0>
75
-
<2 3 0 1>
76
-
<3 0 1 2>
77
-
<0 3 2 1>
78
-
<1 0 3 2>
79
-
<2 1 0 3>
80
-
<3 2 1 0>
81
-
82
-
DSI PHY:
83
-
Required properties:
84
-
- compatible: Could be the following
85
-
* "qcom,dsi-phy-28nm-hpm"
86
-
* "qcom,dsi-phy-28nm-lp"
87
-
* "qcom,dsi-phy-20nm"
88
-
* "qcom,dsi-phy-28nm-8960"
89
-
* "qcom,dsi-phy-14nm"
90
-
* "qcom,dsi-phy-14nm-660"
91
-
* "qcom,dsi-phy-10nm"
92
-
* "qcom,dsi-phy-10nm-8998"
93
-
* "qcom,dsi-phy-7nm"
94
-
* "qcom,dsi-phy-7nm-8150"
95
-
- reg: Physical base address and length of the registers of PLL, PHY. Some
96
-
revisions require the PHY regulator base address, whereas others require the
97
-
PHY lane base address. See below for each PHY revision.
98
-
- reg-names: The names of register regions. The following regions are required:
99
-
For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
100
-
* "dsi_pll"
101
-
* "dsi_phy"
102
-
* "dsi_phy_regulator"
103
-
For DSI 14nm, 10nm and 7nm PHYs:
104
-
* "dsi_pll"
105
-
* "dsi_phy"
106
-
* "dsi_phy_lane"
107
-
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
108
-
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
109
-
- power-domains: Should be <&mmcc MDSS_GDSC>.
110
-
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
111
-
- clock-names: the following clocks are required:
112
-
* "iface"
113
-
* "ref" (only required for new DTS files/entries)
114
-
For 28nm HPM/LP, 28nm 8960 PHYs:
115
-
- vddio-supply: phandle to vdd-io regulator device node
116
-
For 20nm PHY:
117
-
- vddio-supply: phandle to vdd-io regulator device node
118
-
- vcca-supply: phandle to vcca regulator device node
119
-
For 14nm PHY:
120
-
- vcca-supply: phandle to vcca regulator device node
121
-
For 10nm and 7nm PHY:
122
-
- vdds-supply: phandle to vdds regulator device node
123
-
124
-
Optional properties:
125
-
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
126
-
regulator is wanted.
127
-
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
128
-
panels in microseconds. Driver uses this number to adjust
129
-
the clock rate according to the expected transfer time.
130
-
Increasing this value would slow down the mdp processing
131
-
and can result in slower performance.
132
-
Decreasing this value can speed up the mdp processing,
133
-
but this can also impact power consumption.
134
-
As a rule this time should not be higher than the time
135
-
that would be expected with the processing at the
136
-
dsi link rate since anyways this would be the maximum
137
-
transfer time that could be achieved.
138
-
If ping pong split is enabled, this time should not be higher
139
-
than two times the dsi link rate time.
140
-
If the property is not specified, then the default value is 14000 us.
141
-
142
-
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
143
-
[2] Documentation/devicetree/bindings/graph.txt
144
-
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
145
-
[4] Documentation/devicetree/bindings/display/panel/
146
-
147
-
Example:
148
-
dsi0: dsi@fd922800 {
149
-
compatible = "qcom,mdss-dsi-ctrl";
150
-
qcom,dsi-host-index = <0>;
151
-
interrupt-parent = <&mdp>;
152
-
interrupts = <4 0>;
153
-
reg-names = "dsi_ctrl";
154
-
reg = <0xfd922800 0x200>;
155
-
power-domains = <&mmcc MDSS_GDSC>;
156
-
clock-names =
157
-
"bus",
158
-
"byte",
159
-
"core",
160
-
"core_mmss",
161
-
"iface",
162
-
"mdp_core",
163
-
"pixel";
164
-
clocks =
165
-
<&mmcc MDSS_AXI_CLK>,
166
-
<&mmcc MDSS_BYTE0_CLK>,
167
-
<&mmcc MDSS_ESC0_CLK>,
168
-
<&mmcc MMSS_MISC_AHB_CLK>,
169
-
<&mmcc MDSS_AHB_CLK>,
170
-
<&mmcc MDSS_MDP_CLK>,
171
-
<&mmcc MDSS_PCLK0_CLK>;
172
-
173
-
assigned-clocks =
174
-
<&mmcc BYTE0_CLK_SRC>,
175
-
<&mmcc PCLK0_CLK_SRC>;
176
-
assigned-clock-parents =
177
-
<&dsi_phy0 0>,
178
-
<&dsi_phy0 1>;
179
-
180
-
vdda-supply = <&pma8084_l2>;
181
-
vdd-supply = <&pma8084_l22>;
182
-
vddio-supply = <&pma8084_l12>;
183
-
184
-
phys = <&dsi_phy0>;
185
-
phy-names ="dsi-phy";
186
-
187
-
qcom,dual-dsi-mode;
188
-
qcom,master-dsi;
189
-
qcom,sync-dual-dsi;
190
-
191
-
qcom,mdss-mdp-transfer-time-us = <12000>;
192
-
193
-
pinctrl-names = "default", "sleep";
194
-
pinctrl-0 = <&dsi_active>;
195
-
pinctrl-1 = <&dsi_suspend>;
196
-
197
-
ports {
198
-
#address-cells = <1>;
199
-
#size-cells = <0>;
200
-
201
-
port@0 {
202
-
reg = <0>;
203
-
dsi0_in: endpoint {
204
-
remote-endpoint = <&mdp_intf1_out>;
205
-
};
206
-
};
207
-
208
-
port@1 {
209
-
reg = <1>;
210
-
dsi0_out: endpoint {
211
-
remote-endpoint = <&panel_in>;
212
-
data-lanes = <0 1 2 3>;
213
-
};
214
-
};
215
-
};
216
-
217
-
panel: panel@0 {
218
-
compatible = "sharp,lq101r1sx01";
219
-
reg = <0>;
220
-
link2 = <&secondary>;
221
-
222
-
power-supply = <...>;
223
-
backlight = <...>;
224
-
225
-
port {
226
-
panel_in: endpoint {
227
-
remote-endpoint = <&dsi0_out>;
228
-
};
229
-
};
230
-
};
231
-
};
232
-
233
-
dsi_phy0: dsi-phy@fd922a00 {
234
-
compatible = "qcom,dsi-phy-28nm-hpm";
235
-
qcom,dsi-phy-index = <0>;
236
-
reg-names =
237
-
"dsi_pll",
238
-
"dsi_phy",
239
-
"dsi_phy_regulator";
240
-
reg = <0xfd922a00 0xd4>,
241
-
<0xfd922b00 0x2b0>,
242
-
<0xfd922d80 0x7b>;
243
-
clock-names = "iface";
244
-
clocks = <&mmcc MDSS_AHB_CLK>;
245
-
#clock-cells = <1>;
246
-
vddio-supply = <&pma8084_l12>;
247
-
248
-
qcom,dsi-phy-regulator-ldo-mode;
249
-
};
+23
-5
drivers/gpu/drm/drm_atomic.c
+23
-5
drivers/gpu/drm/drm_atomic.c
···
1
1
/*
2
2
* Copyright (C) 2014 Red Hat
3
3
* Copyright (C) 2014 Intel Corp.
4
+
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4
5
*
5
6
* Permission is hereby granted, free of charge, to any person obtaining a
6
7
* copy of this software and associated documentation files (the "Software"),
···
1610
1609
}
1611
1610
EXPORT_SYMBOL(__drm_atomic_helper_set_config);
1612
1611
1613
-
void drm_atomic_print_state(const struct drm_atomic_state *state)
1612
+
/**
1613
+
* drm_atomic_print_new_state - prints drm atomic state
1614
+
* @state: atomic configuration to check
1615
+
* @p: drm printer
1616
+
*
1617
+
* This functions prints the drm atomic state snapshot using the drm printer
1618
+
* which is passed to it. This snapshot can be used for debugging purposes.
1619
+
*
1620
+
* Note that this function looks into the new state objects and hence its not
1621
+
* safe to be used after the call to drm_atomic_helper_commit_hw_done().
1622
+
*/
1623
+
void drm_atomic_print_new_state(const struct drm_atomic_state *state,
1624
+
struct drm_printer *p)
1614
1625
{
1615
-
struct drm_printer p = drm_info_printer(state->dev->dev);
1616
1626
struct drm_plane *plane;
1617
1627
struct drm_plane_state *plane_state;
1618
1628
struct drm_crtc *crtc;
···
1632
1620
struct drm_connector_state *connector_state;
1633
1621
int i;
1634
1622
1623
+
if (!p) {
1624
+
DRM_ERROR("invalid drm printer\n");
1625
+
return;
1626
+
}
1627
+
1635
1628
DRM_DEBUG_ATOMIC("checking %p\n", state);
1636
1629
1637
1630
for_each_new_plane_in_state(state, plane, plane_state, i)
1638
-
drm_atomic_plane_print_state(&p, plane_state);
1631
+
drm_atomic_plane_print_state(p, plane_state);
1639
1632
1640
1633
for_each_new_crtc_in_state(state, crtc, crtc_state, i)
1641
-
drm_atomic_crtc_print_state(&p, crtc_state);
1634
+
drm_atomic_crtc_print_state(p, crtc_state);
1642
1635
1643
1636
for_each_new_connector_in_state(state, connector, connector_state, i)
1644
-
drm_atomic_connector_print_state(&p, connector_state);
1637
+
drm_atomic_connector_print_state(p, connector_state);
1645
1638
}
1639
+
EXPORT_SYMBOL(drm_atomic_print_new_state);
1646
1640
1647
1641
static void __drm_state_dump(struct drm_device *dev, struct drm_printer *p,
1648
1642
bool take_locks)
+3
-1
drivers/gpu/drm/drm_atomic_uapi.c
+3
-1
drivers/gpu/drm/drm_atomic_uapi.c
···
2
2
* Copyright (C) 2014 Red Hat
3
3
* Copyright (C) 2014 Intel Corp.
4
4
* Copyright (C) 2018 Intel Corp.
5
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
5
6
*
6
7
* Permission is hereby granted, free of charge, to any person obtaining a
7
8
* copy of this software and associated documentation files (the "Software"),
···
1322
1321
struct drm_out_fence_state *fence_state;
1323
1322
int ret = 0;
1324
1323
unsigned int i, j, num_fences;
1324
+
struct drm_printer p = drm_info_printer(dev->dev);
1325
1325
1326
1326
/* disallow for drivers not supporting atomic: */
1327
1327
if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
···
1455
1453
ret = drm_atomic_nonblocking_commit(state);
1456
1454
} else {
1457
1455
if (drm_debug_enabled(DRM_UT_STATE))
1458
-
drm_atomic_print_state(state);
1456
+
drm_atomic_print_new_state(state, &p);
1459
1457
1460
1458
ret = drm_atomic_commit(state);
1461
1459
}
+3
-1
drivers/gpu/drm/drm_crtc_internal.h
+3
-1
drivers/gpu/drm/drm_crtc_internal.h
···
5
5
* Jesse Barnes <jesse.barnes@intel.com>
6
6
* Copyright © 2014 Intel Corporation
7
7
* Daniel Vetter <daniel.vetter@ffwll.ch>
8
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
8
9
*
9
10
* Permission is hereby granted, free of charge, to any person obtaining a
10
11
* copy of this software and associated documentation files (the "Software"),
···
237
236
int __drm_atomic_helper_set_config(struct drm_mode_set *set,
238
237
struct drm_atomic_state *state);
239
238
240
-
void drm_atomic_print_state(const struct drm_atomic_state *state);
239
+
void drm_atomic_print_new_state(const struct drm_atomic_state *state,
240
+
struct drm_printer *p);
241
241
242
242
/* drm_atomic_uapi.c */
243
243
int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state,
+2
-1
drivers/gpu/drm/msm/Makefile
+2
-1
drivers/gpu/drm/msm/Makefile
···
58
58
disp/dpu1/dpu_encoder_phys_cmd.o \
59
59
disp/dpu1/dpu_encoder_phys_vid.o \
60
60
disp/dpu1/dpu_formats.o \
61
-
disp/dpu1/dpu_hw_blk.o \
62
61
disp/dpu1/dpu_hw_catalog.o \
63
62
disp/dpu1/dpu_hw_ctl.o \
64
63
disp/dpu1/dpu_hw_interrupts.o \
···
76
77
disp/dpu1/dpu_plane.o \
77
78
disp/dpu1/dpu_rm.o \
78
79
disp/dpu1/dpu_vbif.o \
80
+
disp/msm_disp_snapshot.o \
81
+
disp/msm_disp_snapshot_util.o \
79
82
msm_atomic.o \
80
83
msm_atomic_tracepoints.o \
81
84
msm_debugfs.o \
+41
-17
drivers/gpu/drm/msm/adreno/a2xx.xml.h
+41
-17
drivers/gpu/drm/msm/adreno/a2xx.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
1258
1258
1259
1259
#define REG_A2XX_NQWAIT_UNTIL 0x00000394
1260
1260
1261
-
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
1261
+
#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395
1262
1262
1263
-
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
1263
+
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396
1264
1264
1265
-
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
1265
+
#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397
1266
+
1267
+
#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398
1268
+
1269
+
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399
1270
+
1271
+
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a
1266
1272
1267
1273
#define REG_A2XX_RBBM_DEBUG 0x0000039b
1268
1274
···
2928
2922
2929
2923
#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
2930
2924
2925
+
#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05
2926
+
2927
+
#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06
2928
+
2929
+
#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07
2930
+
2931
2931
#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
2932
2932
2933
2933
#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
2934
+
2935
+
#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a
2936
+
2937
+
#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b
2938
+
2939
+
#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c
2940
+
2941
+
#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d
2942
+
2943
+
#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e
2944
+
2945
+
#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f
2934
2946
2935
2947
#define REG_A2XX_SQ_TEX_0 0x00000000
2936
2948
#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
+19
-19
drivers/gpu/drm/msm/adreno/a3xx.xml.h
+19
-19
drivers/gpu/drm/msm/adreno/a3xx.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
1215
1215
#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
1216
1216
static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
1217
1217
{
1218
-
return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1218
+
return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1219
1219
}
1220
1220
1221
1221
static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
···
1328
1328
#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
1329
1329
static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
1330
1330
{
1331
-
return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1331
+
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1332
1332
}
1333
1333
1334
1334
#define REG_A3XX_RB_BLEND_GREEN 0x000020e5
···
1342
1342
#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1343
1343
static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
1344
1344
{
1345
-
return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1345
+
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1346
1346
}
1347
1347
1348
1348
#define REG_A3XX_RB_BLEND_BLUE 0x000020e6
···
1356
1356
#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1357
1357
static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
1358
1358
{
1359
-
return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1359
+
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1360
1360
}
1361
1361
1362
1362
#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
···
1370
1370
#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1371
1371
static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
1372
1372
{
1373
-
return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1373
+
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1374
1374
}
1375
1375
1376
1376
#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
+18
-18
drivers/gpu/drm/msm/adreno/a4xx.xml.h
+18
-18
drivers/gpu/drm/msm/adreno/a4xx.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
1085
1085
#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1086
1086
static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1087
1087
{
1088
-
return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1088
+
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1089
1089
}
1090
1090
1091
1091
#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
···
1113
1113
#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1114
1114
static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1115
1115
{
1116
-
return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1116
+
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1117
1117
}
1118
1118
1119
1119
#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
···
1141
1141
#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1142
1142
static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1143
1143
{
1144
-
return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1144
+
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1145
1145
}
1146
1146
1147
1147
#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
···
1169
1169
#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1170
1170
static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1171
1171
{
1172
-
return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1172
+
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1173
1173
}
1174
1174
1175
1175
#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
+69
-24
drivers/gpu/drm/msm/adreno/a5xx.xml.h
+69
-24
drivers/gpu/drm/msm/adreno/a5xx.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
2021
2021
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
2022
2022
2023
2023
#define REG_A5XX_RBBM_STATUS3 0x00000530
2024
+
#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
2024
2025
2025
2026
#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
2026
2027
···
2352
2351
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2353
2352
2354
2353
#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2354
+
#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
2355
2355
2356
2356
#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2357
2357
···
2810
2808
#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2811
2809
#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2812
2810
2813
-
#define REG_A5XX_UNKNOWN_E001 0x0000e001
2811
+
#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
2812
+
#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2813
+
#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
2814
+
static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2815
+
{
2816
+
return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2817
+
}
2818
+
#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2819
+
#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
2820
+
static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2821
+
{
2822
+
return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2823
+
}
2814
2824
2815
2825
#define REG_A5XX_UNKNOWN_E004 0x0000e004
2816
2826
···
3359
3345
#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3360
3346
static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3361
3347
{
3362
-
return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3348
+
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3363
3349
}
3364
3350
3365
3351
#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
···
3387
3373
#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3388
3374
static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3389
3375
{
3390
-
return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3376
+
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3391
3377
}
3392
3378
3393
3379
#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
···
3415
3401
#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3416
3402
static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3417
3403
{
3418
-
return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3404
+
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3419
3405
}
3420
3406
3421
3407
#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
···
3443
3429
#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3444
3430
static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3445
3431
{
3446
-
return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3432
+
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3447
3433
}
3448
3434
3449
3435
#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
···
3820
3806
3821
3807
#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3822
3808
3823
-
#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
3809
+
#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
3810
+
#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3811
+
#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3812
+
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3813
+
{
3814
+
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
3815
+
}
3816
+
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
3817
+
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
3818
+
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
3819
+
{
3820
+
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
3821
+
}
3822
+
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
3823
+
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
3824
+
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
3825
+
{
3826
+
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
3827
+
}
3824
3828
3825
3829
#define REG_A5XX_VPC_PACK 0x0000e29d
3826
3830
#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
···
3942
3910
}
3943
3911
#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3944
3912
3945
-
#define REG_A5XX_UNKNOWN_E389 0x0000e389
3913
+
#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
3914
+
#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3915
+
#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3916
+
static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3917
+
{
3918
+
return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
3919
+
}
3946
3920
3947
3921
#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3948
3922
···
4340
4302
#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4341
4303
4342
4304
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4343
-
#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
4305
+
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
4306
+
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
4307
+
static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
4308
+
{
4309
+
return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
4310
+
}
4344
4311
#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4345
4312
#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4346
4313
···
5235
5192
}
5236
5193
5237
5194
#define REG_A5XX_TEX_SAMP_2 0x00000002
5238
-
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
5239
-
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
5195
+
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
5196
+
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
5240
5197
static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5241
5198
{
5242
5199
return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
···
5316
5273
}
5317
5274
5318
5275
#define REG_A5XX_TEX_CONST_2 0x00000002
5276
+
#define A5XX_TEX_CONST_2_UNK4 0x00000010
5319
5277
#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
5320
5278
#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
5321
5279
static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
···
5335
5291
{
5336
5292
return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5337
5293
}
5294
+
#define A5XX_TEX_CONST_2_UNK31 0x80000000
5338
5295
5339
5296
#define REG_A5XX_TEX_CONST_3 0x00000003
5340
5297
#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
+22
-7
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+22
-7
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
···
902
902
if (!a5xx_gpu->shadow_bo) {
903
903
a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
904
904
sizeof(u32) * gpu->nr_rings,
905
-
MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
905
+
MSM_BO_WC | MSM_BO_MAP_PRIV,
906
906
gpu->aspace, &a5xx_gpu->shadow_bo,
907
907
&a5xx_gpu->shadow_iova);
908
908
···
1075
1075
return true;
1076
1076
}
1077
1077
1078
-
static int a5xx_fault_handler(void *arg, unsigned long iova, int flags)
1078
+
static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
1079
1079
{
1080
1080
struct msm_gpu *gpu = arg;
1081
1081
pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
···
1085
1085
gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),
1086
1086
gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));
1087
1087
1088
-
return -EFAULT;
1088
+
return 0;
1089
1089
}
1090
1090
1091
1091
static void a5xx_cp_err_irq(struct msm_gpu *gpu)
···
1199
1199
{
1200
1200
struct drm_device *dev = gpu->dev;
1201
1201
struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1202
+
1203
+
/*
1204
+
* If stalled on SMMU fault, we could trip the GPU's hang detection,
1205
+
* but the fault handler will trigger the devcore dump, and we want
1206
+
* to otherwise resume normally rather than killing the submit, so
1207
+
* just bail.
1208
+
*/
1209
+
if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24))
1210
+
return;
1202
1211
1203
1212
DRM_DEV_ERROR(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1204
1213
ring ? ring->id : -1, ring ? ring->seqno : 0,
···
1416
1407
struct a5xx_crashdumper *dumper)
1417
1408
{
1418
1409
dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
1419
-
SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
1410
+
SZ_1M, MSM_BO_WC, gpu->aspace,
1420
1411
&dumper->bo, &dumper->iova);
1421
1412
1422
1413
if (!IS_ERR(dumper->ptr))
···
1532
1523
{
1533
1524
struct a5xx_gpu_state *a5xx_state = kzalloc(sizeof(*a5xx_state),
1534
1525
GFP_KERNEL);
1526
+
bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24));
1535
1527
1536
1528
if (!a5xx_state)
1537
1529
return ERR_PTR(-ENOMEM);
···
1545
1535
1546
1536
a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);
1547
1537
1548
-
/* Get the HLSQ regs with the help of the crashdumper */
1549
-
a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
1538
+
/*
1539
+
* Get the HLSQ regs with the help of the crashdumper, but only if
1540
+
* we are not stalled in an iommu fault (in which case the crashdumper
1541
+
* would not have access to memory)
1542
+
*/
1543
+
if (!stalled)
1544
+
a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
1550
1545
1551
1546
a5xx_set_hwcg(gpu, true);
1552
1547
···
1720
1705
nvmem_cell_put(cell);
1721
1706
}
1722
1707
1723
-
dev_pm_opp_set_supported_hw(dev, &val, 1);
1708
+
devm_pm_opp_set_supported_hw(dev, &val, 1);
1724
1709
}
1725
1710
1726
1711
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
+1
-1
drivers/gpu/drm/msm/adreno/a5xx_power.c
+1
-1
drivers/gpu/drm/msm/adreno/a5xx_power.c
···
363
363
bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
364
364
365
365
ptr = msm_gem_kernel_new_locked(drm, bosize,
366
-
MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace,
366
+
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace,
367
367
&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);
368
368
if (IS_ERR(ptr))
369
369
return;
+2
-2
drivers/gpu/drm/msm/adreno/a5xx_preempt.c
+2
-2
drivers/gpu/drm/msm/adreno/a5xx_preempt.c
···
230
230
231
231
ptr = msm_gem_kernel_new(gpu->dev,
232
232
A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,
233
-
MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
233
+
MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
234
234
235
235
if (IS_ERR(ptr))
236
236
return PTR_ERR(ptr);
···
238
238
/* The buffer to store counters needs to be unprivileged */
239
239
counters = msm_gem_kernel_new(gpu->dev,
240
240
A5XX_PREEMPT_COUNTER_SIZE,
241
-
MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova);
241
+
MSM_BO_WC, gpu->aspace, &counters_bo, &counters_iova);
242
242
if (IS_ERR(counters)) {
243
243
msm_gem_kernel_put(bo, gpu->aspace, true);
244
244
return PTR_ERR(counters);
+1031
-1114
drivers/gpu/drm/msm/adreno/a6xx.xml.h
+1031
-1114
drivers/gpu/drm/msm/adreno/a6xx.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
168
168
FMT6_ASTC_10x10 = 204,
169
169
FMT6_ASTC_12x10 = 205,
170
170
FMT6_ASTC_12x12 = 206,
171
-
FMT6_S8Z24_UINT = 234,
171
+
FMT6_Z24_UINT_S8_UINT = 234,
172
172
FMT6_NONE = 255,
173
173
};
174
174
···
907
907
TESS_CCW_TRIS = 3,
908
908
};
909
909
910
+
enum a6xx_threadsize {
911
+
THREAD64 = 0,
912
+
THREAD128 = 1,
913
+
};
914
+
910
915
enum a6xx_tex_filter {
911
916
A6XX_TEX_NEAREST = 0,
912
917
A6XX_TEX_LINEAR = 1,
···
1012
1007
1013
1008
#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1014
1009
1015
-
#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
1016
-
1017
-
#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
1010
+
#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
1018
1011
1019
1012
#define REG_A6XX_CP_MISC_CNTL 0x00000840
1020
1013
···
1107
1104
1108
1105
#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1109
1106
1110
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
1111
-
1112
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
1113
-
1114
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
1115
-
1116
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
1117
-
1118
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
1119
-
1120
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
1121
-
1122
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
1123
-
1124
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
1125
-
1126
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
1127
-
1128
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
1129
-
1130
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
1131
-
1132
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
1133
-
1134
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
1135
-
1136
-
#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
1107
+
static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1137
1108
1138
1109
#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1139
1110
···
1153
1176
1154
1177
#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1155
1178
1156
-
#define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e
1179
+
#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
1157
1180
1158
-
#define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931
1181
+
#define REG_A6XX_CP_MRB_BASE 0x00000931
1159
1182
1160
-
#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932
1183
+
#define REG_A6XX_CP_MRB_BASE_HI 0x00000932
1161
1184
1162
-
#define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934
1185
+
#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
1163
1186
1164
-
#define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935
1187
+
#define REG_A6XX_CP_VSD_BASE 0x00000934
1188
+
1189
+
#define REG_A6XX_CP_VSD_BASE_HI 0x00000935
1190
+
1191
+
#define REG_A6XX_CP_MRB_DWORDS 0x00000946
1192
+
1193
+
#define REG_A6XX_CP_VSD_DWORDS 0x00000947
1165
1194
1166
1195
#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1167
1196
#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
···
1185
1202
return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1186
1203
}
1187
1204
1205
+
#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
1206
+
#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
1207
+
#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
1208
+
static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
1209
+
{
1210
+
return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
1211
+
}
1212
+
1188
1213
#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1189
1214
1190
1215
#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
···
1202
1211
#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1203
1212
1204
1213
#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1214
+
1215
+
#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
1216
+
1217
+
#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
1205
1218
1206
1219
#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1207
1220
···
1242
1247
1243
1248
#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1244
1249
1245
-
#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
1250
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1246
1251
1247
-
#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
1252
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1248
1253
1249
-
#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
1254
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1250
1255
1251
-
#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
1256
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1252
1257
1253
-
#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
1258
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1254
1259
1255
-
#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
1260
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1256
1261
1257
-
#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
1262
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1258
1263
1259
-
#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
1264
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1260
1265
1261
-
#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
1266
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1262
1267
1263
-
#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
1268
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1264
1269
1265
-
#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
1270
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1266
1271
1267
-
#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
1272
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1268
1273
1269
-
#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
1274
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1270
1275
1271
-
#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
1276
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1272
1277
1273
-
#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
1278
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1274
1279
1275
-
#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
1276
-
1277
-
#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
1278
-
1279
-
#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
1280
-
1281
-
#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
1282
-
1283
-
#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
1284
-
1285
-
#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
1286
-
1287
-
#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
1288
-
1289
-
#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
1290
-
1291
-
#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
1292
-
1293
-
#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
1294
-
1295
-
#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
1296
-
1297
-
#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
1298
-
1299
-
#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
1300
-
1301
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
1302
-
1303
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
1304
-
1305
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
1306
-
1307
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
1308
-
1309
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
1310
-
1311
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
1312
-
1313
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
1314
-
1315
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
1316
-
1317
-
#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
1318
-
1319
-
#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
1320
-
1321
-
#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
1322
-
1323
-
#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
1324
-
1325
-
#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
1326
-
1327
-
#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
1328
-
1329
-
#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
1330
-
1331
-
#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
1332
-
1333
-
#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
1334
-
1335
-
#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
1336
-
1337
-
#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
1338
-
1339
-
#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
1340
-
1341
-
#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
1342
-
1343
-
#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
1344
-
1345
-
#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
1346
-
1347
-
#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
1348
-
1349
-
#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
1350
-
1351
-
#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
1352
-
1353
-
#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
1354
-
1355
-
#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
1356
-
1357
-
#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
1358
-
1359
-
#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
1360
-
1361
-
#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
1362
-
1363
-
#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
1364
-
1365
-
#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
1366
-
1367
-
#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
1368
-
1369
-
#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
1370
-
1371
-
#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
1372
-
1373
-
#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
1374
-
1375
-
#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
1376
-
1377
-
#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
1378
-
1379
-
#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
1380
-
1381
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
1382
-
1383
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
1384
-
1385
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
1386
-
1387
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
1388
-
1389
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
1390
-
1391
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
1392
-
1393
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
1394
-
1395
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
1396
-
1397
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
1398
-
1399
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
1400
-
1401
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
1402
-
1403
-
#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
1404
-
1405
-
#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
1406
-
1407
-
#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
1408
-
1409
-
#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
1410
-
1411
-
#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
1412
-
1413
-
#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
1414
-
1415
-
#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
1416
-
1417
-
#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
1418
-
1419
-
#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
1420
-
1421
-
#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
1422
-
1423
-
#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
1424
-
1425
-
#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
1426
-
1427
-
#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
1428
-
1429
-
#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
1430
-
1431
-
#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
1432
-
1433
-
#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
1434
-
1435
-
#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
1436
-
1437
-
#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
1438
-
1439
-
#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
1440
-
1441
-
#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
1442
-
1443
-
#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
1444
-
1445
-
#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
1446
-
1447
-
#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
1448
-
1449
-
#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
1450
-
1451
-
#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
1452
-
1453
-
#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
1454
-
1455
-
#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
1456
-
1457
-
#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
1458
-
1459
-
#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
1460
-
1461
-
#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
1462
-
1463
-
#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
1464
-
1465
-
#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
1466
-
1467
-
#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
1468
-
1469
-
#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
1470
-
1471
-
#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
1472
-
1473
-
#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
1474
-
1475
-
#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
1476
-
1477
-
#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
1478
-
1479
-
#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
1480
-
1481
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
1482
-
1483
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
1484
-
1485
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
1486
-
1487
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
1488
-
1489
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
1490
-
1491
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
1492
-
1493
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
1494
-
1495
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
1496
-
1497
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
1498
-
1499
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
1500
-
1501
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
1502
-
1503
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
1504
-
1505
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
1506
-
1507
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
1508
-
1509
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
1510
-
1511
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
1512
-
1513
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
1514
-
1515
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
1516
-
1517
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
1518
-
1519
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
1520
-
1521
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
1522
-
1523
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
1524
-
1525
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
1526
-
1527
-
#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
1528
-
1529
-
#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
1530
-
1531
-
#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
1532
-
1533
-
#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
1534
-
1535
-
#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
1536
-
1537
-
#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
1538
-
1539
-
#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
1540
-
1541
-
#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
1542
-
1543
-
#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
1544
-
1545
-
#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
1546
-
1547
-
#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
1548
-
1549
-
#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
1550
-
1551
-
#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
1552
-
1553
-
#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
1554
-
1555
-
#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
1556
-
1557
-
#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
1558
-
1559
-
#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
1560
-
1561
-
#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
1562
-
1563
-
#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
1564
-
1565
-
#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
1566
-
1567
-
#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
1568
-
1569
-
#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
1570
-
1571
-
#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
1572
-
1573
-
#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
1574
-
1575
-
#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
1576
-
1577
-
#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
1578
-
1579
-
#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
1580
-
1581
-
#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
1582
-
1583
-
#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
1584
-
1585
-
#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
1586
-
1587
-
#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
1588
-
1589
-
#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
1590
-
1591
-
#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
1592
-
1593
-
#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
1594
-
1595
-
#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
1596
-
1597
-
#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
1598
-
1599
-
#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
1600
-
1601
-
#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
1602
-
1603
-
#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
1604
-
1605
-
#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
1606
-
1607
-
#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
1608
-
1609
-
#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
1610
-
1611
-
#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
1612
-
1613
-
#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
1614
-
1615
-
#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
1616
-
1617
-
#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
1618
-
1619
-
#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
1620
-
1621
-
#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
1622
-
1623
-
#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
1624
-
1625
-
#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
1626
-
1627
-
#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
1628
-
1629
-
#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
1630
-
1631
-
#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
1632
-
1633
-
#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
1634
-
1635
-
#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
1636
-
1637
-
#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
1638
-
1639
-
#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
1640
-
1641
-
#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
1642
-
1643
-
#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
1644
-
1645
-
#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
1646
-
1647
-
#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
1648
-
1649
-
#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
1650
-
1651
-
#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
1652
-
1653
-
#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
1654
-
1655
-
#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
1656
-
1657
-
#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
1658
-
1659
-
#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
1660
-
1661
-
#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
1662
-
1663
-
#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
1664
-
1665
-
#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
1666
-
1667
-
#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
1668
-
1669
-
#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
1670
-
1671
-
#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
1672
-
1673
-
#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
1674
-
1675
-
#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
1676
-
1677
-
#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
1678
-
1679
-
#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
1680
-
1681
-
#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
1682
-
1683
-
#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
1684
-
1685
-
#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
1686
-
1687
-
#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
1688
-
1689
-
#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
1690
-
1691
-
#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
1692
-
1693
-
#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
1694
-
1695
-
#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1696
-
1697
-
#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1698
-
1699
-
#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1700
-
1701
-
#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1702
-
1703
-
#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1704
-
1705
-
#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1706
-
1707
-
#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1708
-
1709
-
#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1710
-
1711
-
#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1712
-
1713
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1714
-
1715
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1716
-
1717
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1718
-
1719
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1720
-
1721
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1722
-
1723
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1724
-
1725
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1726
-
1727
-
#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1728
-
1729
-
#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1730
-
1731
-
#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1732
-
1733
-
#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1734
-
1735
-
#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1736
-
1737
-
#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1738
-
1739
-
#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1740
-
1741
-
#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1742
-
1743
-
#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1280
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1744
1281
1745
1282
#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1746
1283
···
1288
1761
1289
1762
#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1290
1763
1291
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
1292
-
1293
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1294
-
1295
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1296
-
1297
-
#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1764
+
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1298
1765
1299
1766
#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1300
1767
···
1761
2240
1762
2241
#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
1763
2242
1764
-
#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
1765
-
1766
-
#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
1767
-
1768
-
#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
1769
-
1770
-
#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
1771
-
1772
-
#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
1773
-
1774
-
#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
1775
-
1776
-
#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
1777
-
1778
-
#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
1779
-
1780
-
#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
2243
+
static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
1781
2244
1782
2245
#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
1783
2246
1784
2247
#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
1785
-
1786
-
#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
1787
-
1788
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
1789
-
1790
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
1791
-
1792
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
1793
-
1794
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
1795
-
1796
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
1797
-
1798
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
1799
-
1800
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
1801
-
1802
-
#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
1803
2248
1804
2249
#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
1805
2250
···
1803
2316
return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1804
2317
}
1805
2318
1806
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
2319
+
static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
1807
2320
1808
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
1809
-
1810
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
1811
-
1812
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
1813
-
1814
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
1815
-
1816
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
1817
-
1818
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
1819
-
1820
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
1821
-
1822
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
1823
-
1824
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
1825
-
1826
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
1827
-
1828
-
#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
1829
-
1830
-
#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
1831
-
1832
-
#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
1833
-
1834
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
1835
-
1836
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
1837
-
1838
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
1839
-
1840
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
1841
-
1842
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
1843
-
1844
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
1845
-
1846
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
1847
-
1848
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
1849
-
1850
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
1851
-
1852
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
1853
-
1854
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
1855
-
1856
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
1857
-
1858
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
1859
-
1860
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
1861
-
1862
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
1863
-
1864
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
1865
-
1866
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
1867
-
1868
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
1869
-
1870
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
1871
-
1872
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
1873
-
1874
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
1875
-
1876
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
1877
-
1878
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
1879
-
1880
-
#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
1881
-
1882
-
#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
1883
-
1884
-
#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
1885
-
1886
-
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
1887
-
1888
-
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
1889
-
1890
-
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
1891
-
1892
-
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
1893
-
1894
-
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
1895
-
1896
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
1897
-
1898
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
1899
-
1900
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
1901
-
1902
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
1903
-
1904
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
1905
-
1906
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
1907
-
1908
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
1909
-
1910
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
1911
-
1912
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
1913
-
1914
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
1915
-
1916
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
1917
-
1918
-
#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
2321
+
#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
1919
2322
1920
2323
#define REG_A6XX_VBIF_VERSION 0x00003000
1921
2324
···
1884
2507
1885
2508
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1886
2509
2510
+
#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
2511
+
1887
2512
#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
1888
2513
1889
2514
#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
···
1934
2555
1935
2556
#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
1936
2557
1937
-
#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
1938
-
#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1939
-
#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
1940
-
#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
1941
-
static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
1942
-
{
1943
-
return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
1944
-
}
1945
-
#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
1946
-
#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
1947
-
static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
1948
-
{
1949
-
return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
1950
-
}
1951
-
1952
-
#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
1953
-
#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1954
-
#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
1955
-
#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
1956
-
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
1957
-
{
1958
-
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
1959
-
}
1960
-
#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
1961
-
#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
1962
-
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
1963
-
{
1964
-
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
1965
-
}
1966
-
1967
2558
#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
1968
2559
#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1969
2560
#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
···
1947
2598
{
1948
2599
return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
1949
2600
}
1950
-
1951
-
#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03
1952
-
1953
-
#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04
1954
2601
1955
2602
#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
1956
2603
···
1992
2647
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
1993
2648
}
1994
2649
1995
-
#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30
1996
-
1997
-
#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31
1998
-
1999
2650
#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
2000
2651
2001
2652
#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
2002
2653
2003
2654
#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2004
-
2005
-
#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34
2006
-
2007
-
#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35
2008
2655
2009
2656
#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2010
2657
···
2186
2849
return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2187
2850
}
2188
2851
#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2189
-
#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000
2852
+
#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
2190
2853
#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
2191
2854
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2192
2855
{
2193
2856
return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2857
+
}
2858
+
#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
2859
+
#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
2860
+
#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
2861
+
#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
2862
+
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2863
+
{
2864
+
return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2194
2865
}
2195
2866
2196
2867
#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
···
2550
3205
#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2551
3206
#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
2552
3207
#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
2553
-
#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0
2554
-
#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5
2555
-
static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)
3208
+
#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
3209
+
#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
3210
+
#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
3211
+
static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
2556
3212
{
2557
-
return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;
3213
+
return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
2558
3214
}
2559
3215
2560
3216
#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
···
2567
3221
{
2568
3222
return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2569
3223
}
2570
-
2571
-
#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
2572
-
2573
-
#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
2574
3224
2575
3225
#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
2576
3226
#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
···
2589
3247
{
2590
3248
return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2591
3249
}
2592
-
2593
-
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
2594
-
2595
-
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
2596
3250
2597
3251
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
2598
3252
#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
···
2744
3406
2745
3407
#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
2746
3408
2747
-
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
3409
+
static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
2748
3410
2749
-
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
3411
+
static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
2750
3412
2751
-
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
2752
-
2753
-
#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
2754
-
2755
-
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
2756
-
2757
-
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
2758
-
2759
-
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
2760
-
2761
-
#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
2762
-
2763
-
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
2764
-
2765
-
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
2766
-
2767
-
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
2768
-
2769
-
#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
3413
+
static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
2770
3414
2771
3415
#define REG_A6XX_RB_BIN_CONTROL 0x00008800
2772
3416
#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
···
3209
3889
return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3210
3890
}
3211
3891
3212
-
static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3213
-
3214
-
static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3215
-
3216
3892
static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3217
3893
#define A6XX_RB_MRT_BASE__MASK 0xffffffff
3218
3894
#define A6XX_RB_MRT_BASE__SHIFT 0
···
3341
4025
return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3342
4026
}
3343
4027
3344
-
#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
3345
-
3346
-
#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
3347
-
3348
4028
#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
3349
4029
#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
3350
4030
#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
···
3445
4133
{
3446
4134
return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3447
4135
}
3448
-
3449
-
#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
3450
-
3451
-
#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
3452
4136
3453
4137
#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
3454
4138
#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
···
3663
4355
return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
3664
4356
}
3665
4357
3666
-
#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
3667
-
3668
-
#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
3669
-
3670
4358
#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
3671
4359
#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
3672
4360
#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
···
3686
4382
{
3687
4383
return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
3688
4384
}
3689
-
3690
-
#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
3691
-
3692
-
#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
3693
4385
3694
4386
#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
3695
4387
#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
···
3712
4412
#define REG_A6XX_RB_BLIT_INFO 0x000088e3
3713
4413
#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
3714
4414
#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
3715
-
#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
4415
+
#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
3716
4416
#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
3717
4417
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
3718
4418
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
···
3759
4459
3760
4460
#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
3761
4461
3762
-
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
3763
-
3764
-
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
3765
-
3766
4462
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
3767
4463
#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
3768
4464
#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
···
3789
4493
3790
4494
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3791
4495
3792
-
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3793
-
3794
-
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
3795
-
3796
4496
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3797
4497
#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
3798
4498
#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
···
3810
4518
{
3811
4519
return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3812
4520
}
3813
-
3814
-
#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
3815
-
3816
-
#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
3817
4521
3818
4522
#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
3819
4523
#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
···
3896
4608
return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
3897
4609
}
3898
4610
#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
4611
+
#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
3899
4612
#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
4613
+
#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
3900
4614
#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
4615
+
#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
3901
4616
#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
3902
-
3903
-
#define REG_A6XX_RB_2D_DST_LO 0x00008c18
3904
-
3905
-
#define REG_A6XX_RB_2D_DST_HI 0x00008c19
4617
+
#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
4618
+
#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
4619
+
static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
4620
+
{
4621
+
return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
4622
+
}
4623
+
#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
3906
4624
3907
4625
#define REG_A6XX_RB_2D_DST 0x00008c18
3908
4626
#define A6XX_RB_2D_DST__MASK 0xffffffff
···
3949
4655
{
3950
4656
return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
3951
4657
}
3952
-
3953
-
#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
3954
-
3955
-
#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
3956
4658
3957
4659
#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
3958
4660
#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
···
4030
4740
return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4031
4741
}
4032
4742
4033
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
4743
+
static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4034
4744
4035
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
4036
-
4037
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
4038
-
4039
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
4040
-
4041
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
4042
-
4043
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
4044
-
4045
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
4046
-
4047
-
#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
4048
-
4049
-
#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
4050
-
4051
-
#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
4052
-
4053
-
#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
4054
-
4055
-
#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
4056
-
4057
-
#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
4745
+
static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4058
4746
4059
4747
#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4060
4748
4061
-
#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
4062
-
4063
-
#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
4064
-
4065
-
#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
4066
-
4067
-
#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
4749
+
static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4068
4750
4069
4751
#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4070
4752
···
4157
4895
}
4158
4896
4159
4897
#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4898
+
#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
4899
+
#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
4160
4900
4161
4901
#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4162
4902
#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
···
4185
4921
static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4186
4922
4187
4923
#define REG_A6XX_VPC_SO_CNTL 0x00009216
4188
-
#define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff
4189
-
#define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0
4190
-
static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)
4924
+
#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4925
+
#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
4926
+
static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4191
4927
{
4192
-
return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;
4928
+
return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4193
4929
}
4194
-
#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
4930
+
#define A6XX_VPC_SO_CNTL_RESET 0x00010000
4195
4931
4196
4932
#define REG_A6XX_VPC_SO_PROG 0x00009217
4197
4933
#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
···
4221
4957
}
4222
4958
#define A6XX_VPC_SO_PROG_B_EN 0x00800000
4223
4959
4224
-
#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218
4225
-
4226
-
#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219
4227
-
4228
4960
#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4229
4961
#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4230
4962
#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
···
4238
4978
{
4239
4979
return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4240
4980
}
4241
-
4242
-
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4243
-
4244
-
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
4245
4981
4246
4982
static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4247
4983
#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
···
4265
5009
return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
4266
5010
}
4267
5011
4268
-
static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4269
-
4270
-
static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
4271
-
4272
5012
#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
4273
5013
#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
4274
5014
···
4289
5037
{
4290
5038
return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
4291
5039
}
4292
-
#define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000
4293
-
#define A6XX_VPC_VS_PACK_UNK24__SHIFT 24
4294
-
static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)
5040
+
#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
5041
+
#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
5042
+
static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
4295
5043
{
4296
-
return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;
5044
+
return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
4297
5045
}
4298
5046
4299
5047
#define REG_A6XX_VPC_GS_PACK 0x00009302
···
4315
5063
{
4316
5064
return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
4317
5065
}
4318
-
#define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000
4319
-
#define A6XX_VPC_GS_PACK_UNK24__SHIFT 24
4320
-
static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)
5066
+
#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
5067
+
#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
5068
+
static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
4321
5069
{
4322
-
return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;
5070
+
return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
4323
5071
}
4324
5072
4325
5073
#define REG_A6XX_VPC_DS_PACK 0x00009303
···
4341
5089
{
4342
5090
return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
4343
5091
}
4344
-
#define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000
4345
-
#define A6XX_VPC_DS_PACK_UNK24__SHIFT 24
4346
-
static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)
5092
+
#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
5093
+
#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
5094
+
static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
4347
5095
{
4348
-
return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;
5096
+
return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
4349
5097
}
4350
5098
4351
5099
#define REG_A6XX_VPC_CNTL_0 0x00009304
···
4362
5110
return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
4363
5111
}
4364
5112
#define A6XX_VPC_CNTL_0_VARYING 0x00010000
4365
-
#define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000
4366
-
#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24
4367
-
static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
5113
+
#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
5114
+
#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
5115
+
static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
4368
5116
{
4369
-
return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
5117
+
return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
4370
5118
}
4371
5119
4372
-
#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
4373
-
#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
4374
-
#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
4375
-
#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
4376
-
#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
4377
-
#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
4378
-
#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000
4379
-
#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16
4380
-
static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)
5120
+
#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
5121
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
5122
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
5123
+
static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
4381
5124
{
4382
-
return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;
5125
+
return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
5126
+
}
5127
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
5128
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
5129
+
static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
5130
+
{
5131
+
return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
5132
+
}
5133
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
5134
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
5135
+
static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
5136
+
{
5137
+
return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
5138
+
}
5139
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
5140
+
#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
5141
+
static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
5142
+
{
5143
+
return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
5144
+
}
5145
+
#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
5146
+
#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
5147
+
static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
5148
+
{
5149
+
return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4383
5150
}
4384
5151
4385
5152
#define REG_A6XX_VPC_SO_DISABLE 0x00009306
···
4412
5141
4413
5142
#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
4414
5143
4415
-
#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
4416
-
4417
-
#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
4418
-
4419
-
#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
4420
-
4421
-
#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
4422
-
4423
-
#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
4424
-
4425
-
#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
5144
+
static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
4426
5145
4427
5146
#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
4428
5147
4429
-
#define REG_A6XX_PC_UNKNOWN_9801 0x00009801
4430
-
#define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff
4431
-
#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0
4432
-
static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)
5148
+
#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
5149
+
#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
5150
+
#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
5151
+
static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
4433
5152
{
4434
-
return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;
5153
+
return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
4435
5154
}
4436
-
#define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000
4437
-
#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13
4438
-
static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)
5155
+
#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
5156
+
#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
5157
+
static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
4439
5158
{
4440
-
return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;
5159
+
return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
4441
5160
}
4442
5161
4443
5162
#define REG_A6XX_PC_TESS_CNTL 0x00009802
···
4482
5221
return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
4483
5222
}
4484
5223
5224
+
#define REG_A6XX_PC_MARKER 0x00009880
5225
+
4485
5226
#define REG_A6XX_PC_POLYGON_MODE 0x00009981
4486
5227
#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
4487
5228
#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
···
4492
5229
return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
4493
5230
}
4494
5231
4495
-
#define REG_A6XX_PC_UNKNOWN_9980 0x00009980
5232
+
#define REG_A6XX_PC_RASTER_CNTL 0x00009980
5233
+
#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
5234
+
#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
5235
+
static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
5236
+
{
5237
+
return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
5238
+
}
5239
+
#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
4496
5240
4497
5241
#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
4498
5242
#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
···
4597
5327
return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
4598
5328
}
4599
5329
4600
-
#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
5330
+
#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
5331
+
#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
5332
+
#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
5333
+
#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
5334
+
#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
5335
+
static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
5336
+
{
5337
+
return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
5338
+
}
4601
5339
4602
-
#define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08
5340
+
#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
4603
5341
4604
5342
#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
4605
5343
#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
···
4627
5349
4628
5350
#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
4629
5351
4630
-
#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
5352
+
#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
4631
5353
4632
-
#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
5354
+
#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
5355
+
5356
+
#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
4633
5357
4634
5358
#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
4635
5359
#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
···
4640
5360
{
4641
5361
return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
4642
5362
}
5363
+
5364
+
#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
5365
+
#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
5366
+
#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
5367
+
static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
5368
+
{
5369
+
return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
5370
+
}
5371
+
#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
5372
+
#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
5373
+
static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
5374
+
{
5375
+
return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
5376
+
}
5377
+
#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
5378
+
#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
5379
+
static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
5380
+
{
5381
+
return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
5382
+
}
5383
+
#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
5384
+
#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
5385
+
static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
5386
+
{
5387
+
return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
5388
+
}
5389
+
#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
5390
+
#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
5391
+
static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
5392
+
{
5393
+
return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
5394
+
}
5395
+
#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
5396
+
#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
5397
+
5398
+
#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
5399
+
5400
+
#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
4643
5401
4644
5402
#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
4645
5403
#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
···
4715
5397
return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
4716
5398
}
4717
5399
4718
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
5400
+
#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
5401
+
#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
4719
5402
4720
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
4721
-
4722
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
4723
-
4724
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
4725
-
4726
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
4727
-
4728
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
4729
-
4730
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
4731
-
4732
-
#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
5403
+
static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
4733
5404
4734
5405
#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
4735
5406
···
4755
5448
{
4756
5449
return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4757
5450
}
5451
+
#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
5452
+
#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
5453
+
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
5454
+
{
5455
+
return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
5456
+
}
4758
5457
4759
5458
#define REG_A6XX_VFD_CONTROL_2 0x0000a002
4760
5459
#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
···
4777
5464
}
4778
5465
4779
5466
#define REG_A6XX_VFD_CONTROL_3 0x0000a003
5467
+
#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff
5468
+
#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0
5469
+
static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val)
5470
+
{
5471
+
return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK;
5472
+
}
4780
5473
#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
4781
5474
#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
4782
5475
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
···
4803
5484
}
4804
5485
4805
5486
#define REG_A6XX_VFD_CONTROL_4 0x0000a004
5487
+
#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
5488
+
#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
5489
+
static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
5490
+
{
5491
+
return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
5492
+
}
4806
5493
4807
5494
#define REG_A6XX_VFD_CONTROL_5 0x0000a005
4808
5495
#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
···
4817
5492
{
4818
5493
return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
4819
5494
}
5495
+
#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
5496
+
#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
5497
+
static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
5498
+
{
5499
+
return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
5500
+
}
4820
5501
4821
5502
#define REG_A6XX_VFD_CONTROL_6 0x0000a006
4822
5503
#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
4823
5504
4824
5505
#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
4825
5506
#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
5507
+
#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002
5508
+
#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004
4826
5509
4827
-
#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
5510
+
#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
5511
+
#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
5512
+
#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
5513
+
#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
5514
+
#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
5515
+
static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
5516
+
{
5517
+
return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
5518
+
}
4828
5519
4829
5520
#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
4830
5521
#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
···
4853
5512
static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4854
5513
4855
5514
static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4856
-
4857
-
static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4858
-
4859
-
static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
5515
+
#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
5516
+
#define A6XX_VFD_FETCH_BASE__SHIFT 0
5517
+
static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
5518
+
{
5519
+
return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
5520
+
}
4860
5521
4861
5522
static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
4862
5523
···
4915
5572
4916
5573
#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
4917
5574
5575
+
#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
5576
+
5577
+
static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
5578
+
4918
5579
#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
5580
+
#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
5581
+
#define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000
5582
+
#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
5583
+
#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
5584
+
static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5585
+
{
5586
+
return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
5587
+
}
4919
5588
#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4920
5589
#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4921
5590
static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
···
4940
5585
{
4941
5586
return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4942
5587
}
5588
+
#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
4943
5589
#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4944
5590
#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4945
5591
static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4946
5592
{
4947
5593
return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4948
5594
}
4949
-
#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
4950
-
#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
4951
-
static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4952
-
{
4953
-
return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4954
-
}
4955
-
#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
4956
-
#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000
4957
-
#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
4958
-
#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
4959
5595
4960
5596
#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
4961
5597
···
4956
5610
static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
4957
5611
{
4958
5612
return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5613
+
}
5614
+
#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5615
+
#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
5616
+
static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5617
+
{
5618
+
return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
4959
5619
}
4960
5620
4961
5621
static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
···
5020
5668
return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5021
5669
}
5022
5670
5023
-
#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
5671
+
#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
5024
5672
5025
-
#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
5673
+
#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
5674
+
#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
5675
+
#define A6XX_SP_VS_OBJ_START__SHIFT 0
5676
+
static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5677
+
{
5678
+
return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5679
+
}
5026
5680
5027
-
#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
5681
+
#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
5682
+
#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5683
+
#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5684
+
static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5685
+
{
5686
+
return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5687
+
}
5688
+
#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5689
+
#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5690
+
static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5691
+
{
5692
+
return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5693
+
}
5694
+
5695
+
#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
5696
+
#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
5697
+
#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
5698
+
static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5699
+
{
5700
+
return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5701
+
}
5702
+
5703
+
#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
5704
+
#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5705
+
#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5706
+
static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5707
+
{
5708
+
return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5709
+
}
5710
+
#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5028
5711
5029
5712
#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5030
5713
···
5081
5694
{
5082
5695
return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5083
5696
}
5084
-
#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000
5697
+
#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
5085
5698
#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
5086
5699
static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5087
5700
{
···
5090
5703
5091
5704
#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5092
5705
5706
+
#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
5707
+
#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5708
+
#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5709
+
static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5710
+
{
5711
+
return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK;
5712
+
}
5713
+
5093
5714
#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5715
+
#define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000
5716
+
#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
5717
+
#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
5718
+
static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5719
+
{
5720
+
return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5721
+
}
5094
5722
#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5095
5723
#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5096
5724
static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
···
5118
5716
{
5119
5717
return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5120
5718
}
5719
+
#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
5121
5720
#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5122
5721
#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5123
5722
static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5124
5723
{
5125
5724
return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5126
5725
}
5127
-
#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5128
-
#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
5129
-
static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5726
+
5727
+
#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5728
+
5729
+
#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
5730
+
5731
+
#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
5732
+
5733
+
#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
5734
+
#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
5735
+
#define A6XX_SP_HS_OBJ_START__SHIFT 0
5736
+
static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5130
5737
{
5131
-
return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
5738
+
return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5132
5739
}
5133
-
#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
5134
-
#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000
5135
-
#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
5136
-
#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
5137
5740
5138
-
#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
5741
+
#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5742
+
#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5743
+
#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5744
+
static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5745
+
{
5746
+
return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5747
+
}
5748
+
#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5749
+
#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5750
+
static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5751
+
{
5752
+
return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5753
+
}
5139
5754
5140
-
#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
5755
+
#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
5756
+
#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
5757
+
#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
5758
+
static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5759
+
{
5760
+
return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5761
+
}
5141
5762
5142
-
#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
5143
-
5144
-
#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
5763
+
#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
5764
+
#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5765
+
#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5766
+
static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5767
+
{
5768
+
return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5769
+
}
5770
+
#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5145
5771
5146
5772
#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5147
5773
···
5191
5761
{
5192
5762
return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5193
5763
}
5194
-
#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000
5764
+
#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
5195
5765
#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
5196
5766
static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5197
5767
{
···
5200
5770
5201
5771
#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5202
5772
5773
+
#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
5774
+
#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5775
+
#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5776
+
static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5777
+
{
5778
+
return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK;
5779
+
}
5780
+
5203
5781
#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5782
+
#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000
5783
+
#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
5784
+
#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
5785
+
static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5786
+
{
5787
+
return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5788
+
}
5204
5789
#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5205
5790
#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5206
5791
static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
···
5228
5783
{
5229
5784
return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5230
5785
}
5786
+
#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
5231
5787
#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5232
5788
#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5233
5789
static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5234
5790
{
5235
5791
return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5236
5792
}
5237
-
#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5238
-
#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
5239
-
static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5240
-
{
5241
-
return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
5242
-
}
5243
-
#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
5244
-
#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000
5245
-
#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
5246
-
#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
5793
+
5794
+
#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
5247
5795
5248
5796
#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5249
5797
#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
···
5244
5806
static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5245
5807
{
5246
5808
return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5809
+
}
5810
+
#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5811
+
#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
5812
+
static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5813
+
{
5814
+
return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5247
5815
}
5248
5816
5249
5817
static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
···
5308
5864
return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5309
5865
}
5310
5866
5311
-
#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
5867
+
#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
5312
5868
5313
-
#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
5869
+
#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
5870
+
#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
5871
+
#define A6XX_SP_DS_OBJ_START__SHIFT 0
5872
+
static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5873
+
{
5874
+
return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5875
+
}
5314
5876
5315
-
#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
5877
+
#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
5878
+
#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5879
+
#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5880
+
static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5881
+
{
5882
+
return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5883
+
}
5884
+
#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5885
+
#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5886
+
static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5887
+
{
5888
+
return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5889
+
}
5890
+
5891
+
#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
5892
+
#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
5893
+
#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
5894
+
static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5895
+
{
5896
+
return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5897
+
}
5898
+
5899
+
#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
5900
+
#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5901
+
#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5902
+
static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5903
+
{
5904
+
return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5905
+
}
5906
+
#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5316
5907
5317
5908
#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5318
5909
···
5369
5890
{
5370
5891
return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5371
5892
}
5372
-
#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000
5893
+
#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
5373
5894
#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
5374
5895
static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5375
5896
{
···
5378
5899
5379
5900
#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5380
5901
5902
+
#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
5903
+
#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5904
+
#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5905
+
static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5906
+
{
5907
+
return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK;
5908
+
}
5909
+
5381
5910
#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5911
+
#define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000
5912
+
#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
5913
+
#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
5914
+
static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5915
+
{
5916
+
return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5917
+
}
5382
5918
#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5383
5919
#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5384
5920
static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
···
5406
5912
{
5407
5913
return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5408
5914
}
5915
+
#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
5409
5916
#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5410
5917
#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5411
5918
static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5412
5919
{
5413
5920
return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5414
5921
}
5415
-
#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5416
-
#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
5417
-
static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5418
-
{
5419
-
return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
5420
-
}
5421
-
#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
5422
-
#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000
5423
-
#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
5424
-
#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
5425
5922
5426
5923
#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5427
5924
···
5488
6003
return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
5489
6004
}
5490
6005
5491
-
#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
6006
+
#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
5492
6007
5493
-
#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
6008
+
#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
6009
+
#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
6010
+
#define A6XX_SP_GS_OBJ_START__SHIFT 0
6011
+
static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
6012
+
{
6013
+
return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
6014
+
}
6015
+
6016
+
#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
6017
+
#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6018
+
#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
6019
+
static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6020
+
{
6021
+
return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6022
+
}
6023
+
#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6024
+
#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
6025
+
static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6026
+
{
6027
+
return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6028
+
}
6029
+
6030
+
#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
6031
+
#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
6032
+
#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
6033
+
static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
6034
+
{
6035
+
return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
6036
+
}
6037
+
6038
+
#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
6039
+
#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6040
+
#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
6041
+
static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6042
+
{
6043
+
return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6044
+
}
6045
+
#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5494
6046
5495
6047
#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
5496
6048
···
5549
6027
{
5550
6028
return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
5551
6029
}
5552
-
#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000
6030
+
#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
5553
6031
#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
5554
6032
static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
5555
6033
{
···
5558
6036
5559
6037
#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
5560
6038
5561
-
#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
6039
+
#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
6040
+
#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6041
+
#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6042
+
static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6043
+
{
6044
+
return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK;
6045
+
}
5562
6046
5563
-
#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
6047
+
#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
6048
+
#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
6049
+
#define A6XX_SP_VS_TEX_SAMP__SHIFT 0
6050
+
static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
6051
+
{
6052
+
return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
6053
+
}
5564
6054
5565
-
#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
6055
+
#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
6056
+
#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
6057
+
#define A6XX_SP_HS_TEX_SAMP__SHIFT 0
6058
+
static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
6059
+
{
6060
+
return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
6061
+
}
5566
6062
5567
-
#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
6063
+
#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
6064
+
#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
6065
+
#define A6XX_SP_DS_TEX_SAMP__SHIFT 0
6066
+
static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
6067
+
{
6068
+
return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
6069
+
}
5568
6070
5569
-
#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
6071
+
#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
6072
+
#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
6073
+
#define A6XX_SP_GS_TEX_SAMP__SHIFT 0
6074
+
static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
6075
+
{
6076
+
return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
6077
+
}
5570
6078
5571
-
#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
6079
+
#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
6080
+
#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
6081
+
#define A6XX_SP_VS_TEX_CONST__SHIFT 0
6082
+
static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
6083
+
{
6084
+
return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
6085
+
}
5572
6086
5573
-
#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
6087
+
#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
6088
+
#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
6089
+
#define A6XX_SP_HS_TEX_CONST__SHIFT 0
6090
+
static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
6091
+
{
6092
+
return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
6093
+
}
5574
6094
5575
-
#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
6095
+
#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
6096
+
#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
6097
+
#define A6XX_SP_DS_TEX_CONST__SHIFT 0
6098
+
static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
6099
+
{
6100
+
return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
6101
+
}
5576
6102
5577
-
#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
5578
-
5579
-
#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
5580
-
5581
-
#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
5582
-
5583
-
#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
5584
-
5585
-
#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
5586
-
5587
-
#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
5588
-
5589
-
#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
5590
-
5591
-
#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
6103
+
#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
6104
+
#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
6105
+
#define A6XX_SP_GS_TEX_CONST__SHIFT 0
6106
+
static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
6107
+
{
6108
+
return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
6109
+
}
5592
6110
5593
6111
#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
6112
+
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6113
+
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
6114
+
static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6115
+
{
6116
+
return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
6117
+
}
6118
+
#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
6119
+
#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
6120
+
#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
6121
+
#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
6122
+
#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
6123
+
#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
6124
+
#define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000
6125
+
#define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27
6126
+
static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
6127
+
{
6128
+
return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
6129
+
}
6130
+
#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
6131
+
#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
6132
+
#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
6133
+
static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
6134
+
{
6135
+
return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
6136
+
}
5594
6137
#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5595
6138
#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5596
6139
static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
···
5668
6081
{
5669
6082
return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5670
6083
}
6084
+
#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
5671
6085
#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5672
6086
#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5673
6087
static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5674
6088
{
5675
6089
return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
5676
6090
}
5677
-
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5678
-
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
5679
-
static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5680
-
{
5681
-
return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
5682
-
}
5683
-
#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
5684
-
#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
5685
-
#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
5686
-
#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
5687
6091
5688
6092
#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
5689
6093
5690
-
#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
6094
+
#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
5691
6095
5692
-
#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
6096
+
#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
6097
+
#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
6098
+
#define A6XX_SP_FS_OBJ_START__SHIFT 0
6099
+
static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
6100
+
{
6101
+
return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
6102
+
}
5693
6103
5694
-
#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
6104
+
#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
6105
+
#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6106
+
#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
6107
+
static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6108
+
{
6109
+
return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6110
+
}
6111
+
#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6112
+
#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
6113
+
static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6114
+
{
6115
+
return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6116
+
}
6117
+
6118
+
#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
6119
+
#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
6120
+
#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
6121
+
static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
6122
+
{
6123
+
return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
6124
+
}
6125
+
6126
+
#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
6127
+
#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6128
+
#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
6129
+
static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6130
+
{
6131
+
return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6132
+
}
6133
+
#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5695
6134
5696
6135
#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
5697
-
#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
6136
+
#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
6137
+
#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
6138
+
static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
6139
+
{
6140
+
return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
6141
+
}
5698
6142
#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
5699
6143
#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
5700
6144
#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
···
5819
6201
return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
5820
6202
}
5821
6203
6204
+
static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6205
+
6206
+
static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6207
+
#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6208
+
#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
6209
+
static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
6210
+
{
6211
+
return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
6212
+
}
6213
+
#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6214
+
5822
6215
static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
5823
6216
5824
6217
static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
···
5841
6212
}
5842
6213
#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
5843
6214
#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
6215
+
#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
5844
6216
5845
6217
#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
5846
6218
#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
···
5856
6226
static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
5857
6227
{
5858
6228
return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6229
+
}
6230
+
#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000
6231
+
#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12
6232
+
static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
6233
+
{
6234
+
return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
5859
6235
}
5860
6236
5861
6237
static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
···
5908
6272
static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
5909
6273
5910
6274
static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
5911
-
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff
6275
+
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
5912
6276
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
5913
6277
static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
5914
6278
{
5915
6279
return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
5916
6280
}
5917
-
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000
6281
+
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
5918
6282
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
5919
6283
static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
5920
6284
{
···
5925
6289
5926
6290
#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
5927
6291
5928
-
#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
5929
-
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001
5930
-
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0
5931
-
static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)
6292
+
#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
6293
+
#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6294
+
#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6295
+
static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5932
6296
{
5933
-
return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;
6297
+
return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK;
5934
6298
}
5935
-
5936
-
#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3
5937
-
5938
-
#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
5939
-
5940
-
#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
5941
-
5942
-
#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
5943
-
5944
-
#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
5945
-
5946
-
#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
5947
-
5948
-
#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
5949
-
5950
-
#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
5951
-
5952
-
#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
5953
-
5954
-
#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
5955
-
5956
-
static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
5957
-
5958
-
static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
5959
-
5960
-
static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5961
-
5962
-
static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5963
-
#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
5964
-
#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
5965
-
static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
5966
-
{
5967
-
return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
5968
-
}
5969
-
#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
5970
6299
5971
6300
#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
6301
+
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6302
+
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
6303
+
static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6304
+
{
6305
+
return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6306
+
}
6307
+
#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
6308
+
#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
6309
+
#define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000
6310
+
#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
6311
+
#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
6312
+
#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
6313
+
static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
6314
+
{
6315
+
return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
6316
+
}
5972
6317
#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5973
6318
#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5974
6319
static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
···
5962
6345
{
5963
6346
return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5964
6347
}
6348
+
#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
5965
6349
#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5966
6350
#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5967
6351
static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5968
6352
{
5969
6353
return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
5970
6354
}
5971
-
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5972
-
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
5973
-
static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
6355
+
6356
+
#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6357
+
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
6358
+
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
6359
+
static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
5974
6360
{
5975
-
return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6361
+
return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
5976
6362
}
5977
-
#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
5978
-
#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000
5979
-
#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
5980
-
#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
6363
+
#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
6364
+
#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
5981
6365
5982
-
#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
6366
+
#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
5983
6367
5984
-
#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
6368
+
#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
6369
+
6370
+
#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
6371
+
#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
6372
+
#define A6XX_SP_CS_OBJ_START__SHIFT 0
6373
+
static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
6374
+
{
6375
+
return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
6376
+
}
6377
+
6378
+
#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
6379
+
#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6380
+
#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
6381
+
static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6382
+
{
6383
+
return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6384
+
}
6385
+
#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6386
+
#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
6387
+
static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6388
+
{
6389
+
return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6390
+
}
6391
+
6392
+
#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
6393
+
#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
6394
+
#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
6395
+
static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6396
+
{
6397
+
return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6398
+
}
6399
+
6400
+
#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
6401
+
#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6402
+
#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
6403
+
static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6404
+
{
6405
+
return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6406
+
}
6407
+
#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6408
+
6409
+
#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
5985
6410
5986
6411
#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
5987
6412
#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
···
6043
6384
{
6044
6385
return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6045
6386
}
6046
-
#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000
6387
+
#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
6047
6388
#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
6048
6389
static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6049
6390
{
···
6052
6393
6053
6394
#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6054
6395
6055
-
#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2
6396
+
#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
6397
+
#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6398
+
#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6399
+
static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6400
+
{
6401
+
return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK;
6402
+
}
6056
6403
6057
-
#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3
6404
+
#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
6405
+
#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
6406
+
#define A6XX_SP_FS_TEX_SAMP__SHIFT 0
6407
+
static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6408
+
{
6409
+
return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6410
+
}
6411
+
6412
+
#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
6413
+
#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
6414
+
#define A6XX_SP_CS_TEX_SAMP__SHIFT 0
6415
+
static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6416
+
{
6417
+
return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6418
+
}
6419
+
6420
+
#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
6421
+
#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
6422
+
#define A6XX_SP_FS_TEX_CONST__SHIFT 0
6423
+
static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6424
+
{
6425
+
return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6426
+
}
6427
+
6428
+
#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
6429
+
#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
6430
+
#define A6XX_SP_CS_TEX_CONST__SHIFT 0
6431
+
static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6432
+
{
6433
+
return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6434
+
}
6435
+
6436
+
static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6437
+
6438
+
static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6439
+
6440
+
#define REG_A6XX_SP_CS_IBO 0x0000a9f2
6441
+
#define A6XX_SP_CS_IBO__MASK 0xffffffff
6442
+
#define A6XX_SP_CS_IBO__SHIFT 0
6443
+
static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6444
+
{
6445
+
return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6446
+
}
6058
6447
6059
6448
#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6060
6449
6061
-
#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
6450
+
#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
6451
+
#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
6452
+
#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002
6453
+
#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004
6454
+
#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
6062
6455
6063
6456
#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6064
6457
#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
···
6130
6419
{
6131
6420
return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6132
6421
}
6133
-
#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000
6422
+
#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
6134
6423
#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
6135
6424
static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6136
6425
{
···
6143
6432
6144
6433
static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6145
6434
6146
-
#define REG_A6XX_SP_IBO_LO 0x0000ab1a
6147
-
6148
-
#define REG_A6XX_SP_IBO_HI 0x0000ab1b
6435
+
#define REG_A6XX_SP_IBO 0x0000ab1a
6436
+
#define A6XX_SP_IBO__MASK 0xffffffff
6437
+
#define A6XX_SP_IBO__SHIFT 0
6438
+
static inline uint32_t A6XX_SP_IBO(uint32_t val)
6439
+
{
6440
+
return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6441
+
}
6149
6442
6150
6443
#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6151
6444
···
6173
6458
6174
6459
#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6175
6460
6461
+
#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
6462
+
6463
+
#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
6464
+
6176
6465
#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
6177
6466
6178
-
#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
6467
+
#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
6468
+
#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
6179
6469
6180
-
#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
6470
+
#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
6471
+
#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
6472
+
#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
6473
+
#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
6474
+
#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
6475
+
#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
6476
+
#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
6477
+
6478
+
static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6181
6479
6182
6480
#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6481
+
#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6482
+
#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6483
+
static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6484
+
{
6485
+
return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6486
+
}
6183
6487
6184
6488
#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6185
6489
6186
6490
#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6491
+
6492
+
#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
6493
+
6494
+
#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
6187
6495
6188
6496
#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6189
6497
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
···
6214
6476
static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6215
6477
{
6216
6478
return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6479
+
}
6480
+
#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
6481
+
#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
6482
+
static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6483
+
{
6484
+
return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6217
6485
}
6218
6486
6219
6487
#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
···
6232
6488
#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6233
6489
6234
6490
#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6235
-
6236
-
#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
6237
-
6238
-
#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
6491
+
#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6492
+
#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6493
+
static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6494
+
{
6495
+
return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6496
+
}
6239
6497
6240
6498
#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6241
6499
#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
···
6343
6597
return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6344
6598
}
6345
6599
6600
+
#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
6601
+
#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
6602
+
#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
6603
+
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6604
+
{
6605
+
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6606
+
}
6607
+
#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6608
+
#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
6609
+
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6610
+
{
6611
+
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6612
+
}
6613
+
6346
6614
#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
6347
6615
6348
6616
#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
···
6387
6627
return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6388
6628
}
6389
6629
#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6630
+
#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
6390
6631
#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6632
+
#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
6391
6633
#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6634
+
#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
6392
6635
#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6636
+
#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
6637
+
#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
6638
+
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6639
+
{
6640
+
return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
6641
+
}
6642
+
#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
6393
6643
6394
6644
#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6395
6645
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
···
6415
6645
return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6416
6646
}
6417
6647
6418
-
#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
6419
-
6420
-
#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
6421
-
6422
6648
#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6649
+
#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
6650
+
#define A6XX_SP_PS_2D_SRC__SHIFT 0
6651
+
static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
6652
+
{
6653
+
return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
6654
+
}
6423
6655
6424
6656
#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6425
-
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
6657
+
#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
6658
+
#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
6659
+
static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
6660
+
{
6661
+
return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
6662
+
}
6663
+
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
6426
6664
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
6427
6665
static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6428
6666
{
6429
6667
return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6430
6668
}
6431
6669
6432
-
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
6670
+
#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
6671
+
#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
6672
+
#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
6673
+
static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
6674
+
{
6675
+
return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
6676
+
}
6433
6677
6434
-
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
6678
+
#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
6679
+
#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
6680
+
#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
6681
+
static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
6682
+
{
6683
+
return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
6684
+
}
6685
+
6686
+
#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
6687
+
#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
6688
+
#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
6689
+
static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
6690
+
{
6691
+
return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
6692
+
}
6435
6693
6436
6694
#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6695
+
#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
6696
+
#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
6697
+
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
6698
+
{
6699
+
return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
6700
+
}
6437
6701
6438
6702
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6439
-
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
6440
-
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
6441
-
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
6703
+
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
6704
+
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
6705
+
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
6442
6706
{
6443
-
return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
6444
-
}
6445
-
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
6446
-
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
6447
-
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
6448
-
{
6449
-
return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
6707
+
return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
6450
6708
}
6451
6709
6452
-
#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
6710
+
#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
6453
6711
6454
-
#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
6712
+
#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
6713
+
6714
+
#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
6715
+
6716
+
#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
6717
+
6718
+
#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
6719
+
#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
6720
+
#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
6721
+
static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
6722
+
{
6723
+
return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
6724
+
}
6725
+
#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6726
+
#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
6727
+
static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
6728
+
{
6729
+
return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
6730
+
}
6731
+
6732
+
#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600
6733
+
6734
+
#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
6735
+
6736
+
#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
6737
+
6738
+
#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
6739
+
#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
6740
+
#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
6741
+
#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
6742
+
static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
6743
+
{
6744
+
return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
6745
+
}
6746
+
#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
6747
+
#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
6748
+
#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
6749
+
static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
6750
+
{
6751
+
return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
6752
+
}
6753
+
#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
6754
+
#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
6755
+
static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
6756
+
{
6757
+
return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
6758
+
}
6759
+
6760
+
#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
6761
+
6762
+
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
6763
+
6764
+
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
6765
+
6766
+
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
6767
+
6768
+
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
6769
+
6770
+
#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
6771
+
6772
+
static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
6455
6773
6456
6774
#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6457
6775
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
···
6580
6722
#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6581
6723
6582
6724
#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6725
+
#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
6726
+
#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
6727
+
static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
6728
+
{
6729
+
return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
6730
+
}
6583
6731
6584
6732
#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6585
6733
6586
-
#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
6734
+
#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
6735
+
#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
6736
+
#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
6737
+
static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
6738
+
{
6739
+
return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
6740
+
}
6741
+
#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
6742
+
#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
6743
+
#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
6744
+
static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
6745
+
{
6746
+
return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
6747
+
}
6748
+
6749
+
#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
6587
6750
6588
6751
#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6589
6752
···
6687
6808
}
6688
6809
6689
6810
#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6811
+
#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff
6812
+
#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0
6813
+
static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val)
6814
+
{
6815
+
return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK;
6816
+
}
6817
+
#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00
6818
+
#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8
6819
+
static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val)
6820
+
{
6821
+
return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK;
6822
+
}
6690
6823
6691
6824
#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6692
6825
#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
···
6790
6899
{
6791
6900
return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
6792
6901
}
6793
-
#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
6794
-
#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
6795
-
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
6902
+
#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6903
+
#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
6904
+
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6796
6905
{
6797
-
return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
6906
+
return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
6798
6907
}
6799
-
#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
6800
-
#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
6801
-
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
6908
+
#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6909
+
#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
6910
+
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6802
6911
{
6803
-
return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
6912
+
return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6804
6913
}
6805
6914
#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6806
6915
#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
···
6809
6918
return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
6810
6919
}
6811
6920
6812
-
#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998
6921
+
#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
6922
+
#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
6923
+
#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
6924
+
static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6925
+
{
6926
+
return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6927
+
}
6928
+
#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
6929
+
#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
6930
+
#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
6931
+
static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6932
+
{
6933
+
return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
6934
+
}
6935
+
#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
6813
6936
6814
6937
#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
6815
6938
···
6834
6929
#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
6835
6930
6836
6931
#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
6932
+
#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
6933
+
#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
6934
+
static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
6935
+
{
6936
+
return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
6937
+
}
6837
6938
6838
6939
#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
6839
6940
···
6936
7025
#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
6937
7026
6938
7027
#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
7028
+
7029
+
#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
7030
+
7031
+
#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
7032
+
7033
+
static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
6939
7034
6940
7035
#define REG_A6XX_CP_EVENT_START 0x0000d600
6941
7036
#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
···
7052
7135
return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7053
7136
}
7054
7137
#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7055
-
#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
7056
-
#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
7057
-
static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
7138
+
#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7139
+
#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
7140
+
static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7058
7141
{
7059
-
return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
7142
+
return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7060
7143
}
7061
7144
7062
7145
#define REG_A6XX_TEX_SAMP_3 0x00000003
+42
-13
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+42
-13
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
512
512
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
513
513
struct platform_device *pdev = to_platform_device(gmu->dev);
514
514
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
515
-
void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
515
+
void __iomem *seqptr;
516
516
uint32_t pdc_address_offset;
517
+
bool pdc_in_aop = false;
517
518
518
-
if (!pdcptr || !seqptr)
519
+
if (!pdcptr)
519
520
goto err;
520
521
521
-
if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
522
+
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
523
+
pdc_in_aop = true;
524
+
else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
522
525
pdc_address_offset = 0x30090;
523
-
else if (adreno_is_a650(adreno_gpu))
524
-
pdc_address_offset = 0x300a0;
525
526
else
526
527
pdc_address_offset = 0x30080;
528
+
529
+
if (!pdc_in_aop) {
530
+
seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
531
+
if (!seqptr)
532
+
goto err;
533
+
}
527
534
528
535
/* Disable SDE clock gating */
529
536
gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
···
549
542
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
550
543
551
544
/* Load RSC sequencer uCode for sleep and wakeup */
552
-
if (adreno_is_a650(adreno_gpu)) {
545
+
if (adreno_is_a650_family(adreno_gpu)) {
553
546
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
554
547
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
555
548
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
···
562
555
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
563
556
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
564
557
}
558
+
559
+
if (pdc_in_aop)
560
+
goto setup_pdc;
565
561
566
562
/* Load PDC sequencer uCode for power up and power down sequence */
567
563
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
···
597
587
598
588
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
599
589
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
600
-
if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
590
+
if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
601
591
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
602
592
else
603
593
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
···
606
596
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
607
597
608
598
/* Setup GPU PDC */
599
+
setup_pdc:
609
600
pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
610
601
pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
611
602
···
698
687
u32 itcm_base = 0x00000000;
699
688
u32 dtcm_base = 0x00040000;
700
689
701
-
if (adreno_is_a650(adreno_gpu))
690
+
if (adreno_is_a650_family(adreno_gpu))
702
691
dtcm_base = 0x10004000;
703
692
704
693
if (gmu->legacy) {
···
751
740
int ret;
752
741
u32 chipid;
753
742
754
-
if (adreno_is_a650(adreno_gpu))
743
+
if (adreno_is_a650_family(adreno_gpu)) {
744
+
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
755
745
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
746
+
}
756
747
757
748
if (state == GMU_WARM_BOOT) {
758
749
ret = a6xx_rpmh_start(gmu);
···
1359
1346
* The GMU handles its own frequency switching so build a list of
1360
1347
* available frequencies to send during initialization
1361
1348
*/
1362
-
ret = dev_pm_opp_of_add_table(gmu->dev);
1349
+
ret = devm_pm_opp_of_add_table(gmu->dev);
1363
1350
if (ret) {
1364
1351
DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1365
1352
return ret;
···
1496
1483
if (ret)
1497
1484
goto err_put_device;
1498
1485
1486
+
1487
+
/* A660 now requires handling "prealloc requests" in GMU firmware
1488
+
* For now just hardcode allocations based on the known firmware.
1489
+
* note: there is no indication that these correspond to "dummy" or
1490
+
* "debug" regions, but this "guess" allows reusing these BOs which
1491
+
* are otherwise unused by a660.
1492
+
*/
1493
+
gmu->dummy.size = SZ_4K;
1494
+
if (adreno_is_a660(adreno_gpu)) {
1495
+
ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
1496
+
if (ret)
1497
+
goto err_memory;
1498
+
1499
+
gmu->dummy.size = SZ_8K;
1500
+
}
1501
+
1499
1502
/* Allocate memory for the GMU dummy page */
1500
-
ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
1503
+
ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
1501
1504
if (ret)
1502
1505
goto err_memory;
1503
1506
1504
-
if (adreno_is_a650(adreno_gpu)) {
1507
+
if (adreno_is_a650_family(adreno_gpu)) {
1505
1508
ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1506
1509
SZ_16M - SZ_16K, 0x04000);
1507
1510
if (ret)
···
1559
1530
goto err_memory;
1560
1531
}
1561
1532
1562
-
if (adreno_is_a650(adreno_gpu)) {
1533
+
if (adreno_is_a650_family(adreno_gpu)) {
1563
1534
gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1564
1535
if (IS_ERR(gmu->rscc))
1565
1536
goto err_mmio;
+18
-14
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+18
-14
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
292
292
293
293
#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
294
294
295
+
#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
296
+
295
297
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
296
298
297
299
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
···
440
438
#define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03
441
439
442
440
#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
441
+
442
+
#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
443
443
444
444
#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
445
445
+258
-47
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+258
-47
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
149
149
150
150
a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
151
151
152
-
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
152
+
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
153
153
rbmemptr_stats(ring, index, cpcycles_start));
154
154
155
155
/*
···
185
185
}
186
186
}
187
187
188
-
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
188
+
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
189
189
rbmemptr_stats(ring, index, cpcycles_end));
190
190
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191
191
rbmemptr_stats(ring, index, alwayson_end));
···
427
427
{},
428
428
};
429
429
430
+
const struct adreno_reglist a660_hwcg[] = {
431
+
{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
432
+
{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
433
+
{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
434
+
{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
435
+
{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
436
+
{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
437
+
{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
438
+
{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
439
+
{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
440
+
{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
441
+
{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
442
+
{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
443
+
{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
444
+
{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
445
+
{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
446
+
{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
447
+
{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
448
+
{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
449
+
{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
450
+
{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
451
+
{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
452
+
{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
453
+
{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
454
+
{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
455
+
{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
456
+
{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
457
+
{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
458
+
{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
459
+
{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
460
+
{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
461
+
{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
462
+
{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
463
+
{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
464
+
{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
465
+
{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
466
+
{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
467
+
{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
468
+
{REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
469
+
{REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
470
+
{REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
471
+
{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
472
+
{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
473
+
{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
474
+
{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
475
+
{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
476
+
{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
477
+
{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
478
+
{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
479
+
{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
480
+
{},
481
+
};
482
+
430
483
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
431
484
{
432
485
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
···
594
541
A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
595
542
};
596
543
544
+
/* These are for a635 and a660 */
545
+
static const u32 a660_protect[] = {
546
+
A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
547
+
A6XX_PROTECT_RDONLY(0x00501, 0x0005),
548
+
A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
549
+
A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
550
+
A6XX_PROTECT_NORDWR(0x00510, 0x0000),
551
+
A6XX_PROTECT_NORDWR(0x00534, 0x0000),
552
+
A6XX_PROTECT_NORDWR(0x00800, 0x0082),
553
+
A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
554
+
A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
555
+
A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
556
+
A6XX_PROTECT_NORDWR(0x00900, 0x004d),
557
+
A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
558
+
A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
559
+
A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
560
+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
561
+
A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
562
+
A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
563
+
A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
564
+
A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
565
+
A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
566
+
A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
567
+
A6XX_PROTECT_NORDWR(0x09624, 0x01db),
568
+
A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
569
+
A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
570
+
A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
571
+
A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
572
+
A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
573
+
A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
574
+
A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
575
+
A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
576
+
A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
577
+
A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
578
+
A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
579
+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
580
+
A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
581
+
A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
582
+
A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
583
+
A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
584
+
A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
585
+
A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
586
+
A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
587
+
};
588
+
597
589
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
598
590
{
599
591
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
···
651
553
if (adreno_is_a650(adreno_gpu)) {
652
554
regs = a650_protect;
653
555
count = ARRAY_SIZE(a650_protect);
556
+
count_max = 48;
557
+
} else if (adreno_is_a660(adreno_gpu)) {
558
+
regs = a660_protect;
559
+
count = ARRAY_SIZE(a660_protect);
654
560
count_max = 48;
655
561
}
656
562
···
686
584
if (adreno_is_a640(adreno_gpu))
687
585
amsbc = 1;
688
586
689
-
if (adreno_is_a650(adreno_gpu)) {
587
+
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
690
588
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
691
589
lower_bit = 3;
692
590
amsbc = 1;
···
750
648
* Targets up to a640 (a618, a630 and a640) need to check for a
751
649
* microcode version that is patched to support the whereami opcode or
752
650
* one that is new enough to include it by default.
651
+
*
652
+
* a650 tier targets don't need whereami but still need to be
653
+
* equal to or newer than 0.95 for other security fixes
654
+
*
655
+
* a660 targets have all the critical security fixes from the start
753
656
*/
754
657
if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
755
658
adreno_is_a640(adreno_gpu)) {
···
778
671
DRM_DEV_ERROR(&gpu->pdev->dev,
779
672
"a630 SQE ucode is too old. Have version %x need at least %x\n",
780
673
buf[0] & 0xfff, 0x190);
781
-
} else {
782
-
/*
783
-
* a650 tier targets don't need whereami but still need to be
784
-
* equal to or newer than 0.95 for other security fixes
785
-
*/
786
-
if (adreno_is_a650(adreno_gpu)) {
787
-
if ((buf[0] & 0xfff) >= 0x095) {
788
-
ret = true;
789
-
goto out;
790
-
}
791
-
792
-
DRM_DEV_ERROR(&gpu->pdev->dev,
793
-
"a650 SQE ucode is too old. Have version %x need at least %x\n",
794
-
buf[0] & 0xfff, 0x095);
674
+
} else if (adreno_is_a650(adreno_gpu)) {
675
+
if ((buf[0] & 0xfff) >= 0x095) {
676
+
ret = true;
677
+
goto out;
795
678
}
796
679
797
-
/*
798
-
* When a660 is added those targets should return true here
799
-
* since those have all the critical security fixes built in
800
-
* from the start
801
-
*/
680
+
DRM_DEV_ERROR(&gpu->pdev->dev,
681
+
"a650 SQE ucode is too old. Have version %x need at least %x\n",
682
+
buf[0] & 0xfff, 0x095);
683
+
} else if (adreno_is_a660(adreno_gpu)) {
684
+
ret = true;
685
+
} else {
686
+
DRM_DEV_ERROR(&gpu->pdev->dev,
687
+
"unknown GPU, add it to a6xx_ucode_check_version()!!\n");
802
688
}
803
689
out:
804
690
msm_gem_put_vaddr(obj);
···
827
727
}
828
728
}
829
729
830
-
gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
831
-
REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
730
+
gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
731
+
REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
832
732
833
733
return 0;
834
734
}
···
897
797
a6xx_set_hwcg(gpu, true);
898
798
899
799
/* VBIF/GBIF start*/
900
-
if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
800
+
if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {
901
801
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
902
802
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
903
803
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
···
922
822
gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
923
823
gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
924
824
925
-
if (!adreno_is_a650(adreno_gpu)) {
825
+
if (!adreno_is_a650_family(adreno_gpu)) {
926
826
/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
927
827
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
928
828
REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
···
935
835
gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
936
836
gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
937
837
938
-
if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
838
+
if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
939
839
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
940
840
else
941
841
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
942
842
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
943
843
844
+
if (adreno_is_a660(adreno_gpu))
845
+
gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
846
+
944
847
/* Setting the mem pool size */
945
848
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
946
849
947
-
/* Setting the primFifo thresholds default values */
948
-
if (adreno_is_a650(adreno_gpu))
949
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
850
+
/* Setting the primFifo thresholds default values,
851
+
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
852
+
*/
853
+
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
854
+
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
950
855
else if (adreno_is_a640(adreno_gpu))
951
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
856
+
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
952
857
else
953
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
858
+
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
954
859
955
860
/* Set the AHB default slave response to "ERROR" */
956
861
gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
···
964
859
gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
965
860
966
861
/* Select CP0 to always count cycles */
967
-
gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
862
+
gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
968
863
969
864
a6xx_set_ubwc_config(gpu);
970
865
···
975
870
gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
976
871
977
872
/* Set weights for bicubic filtering */
978
-
if (adreno_is_a650(adreno_gpu)) {
873
+
if (adreno_is_a650_family(adreno_gpu)) {
979
874
gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
980
875
gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
981
876
0x3fe05ff4);
···
989
884
990
885
/* Protect registers from the CP */
991
886
a6xx_set_cp_protect(gpu);
887
+
888
+
if (adreno_is_a660(adreno_gpu)) {
889
+
gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
890
+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
891
+
/* Set dualQ + disable afull for A660 GPU but not for A635 */
892
+
gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
893
+
}
992
894
993
895
/* Enable expanded apriv for targets that support it */
994
896
if (gpu->hw_apriv) {
···
1037
925
if (!a6xx_gpu->shadow_bo) {
1038
926
a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
1039
927
sizeof(u32) * gpu->nr_rings,
1040
-
MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
928
+
MSM_BO_WC | MSM_BO_MAP_PRIV,
1041
929
gpu->aspace, &a6xx_gpu->shadow_bo,
1042
930
&a6xx_gpu->shadow_iova);
1043
931
···
1144
1032
msm_gpu_hw_init(gpu);
1145
1033
}
1146
1034
1147
-
static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
1035
+
static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
1036
+
{
1037
+
static const char *uche_clients[7] = {
1038
+
"VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
1039
+
};
1040
+
u32 val;
1041
+
1042
+
if (mid < 1 || mid > 3)
1043
+
return "UNKNOWN";
1044
+
1045
+
/*
1046
+
* The source of the data depends on the mid ID read from FSYNR1.
1047
+
* and the client ID read from the UCHE block
1048
+
*/
1049
+
val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
1050
+
1051
+
/* mid = 3 is most precise and refers to only one block per client */
1052
+
if (mid == 3)
1053
+
return uche_clients[val & 7];
1054
+
1055
+
/* For mid=2 the source is TP or VFD except when the client id is 0 */
1056
+
if (mid == 2)
1057
+
return ((val & 7) == 0) ? "TP" : "TP|VFD";
1058
+
1059
+
/* For mid=1 just return "UCHE" as a catchall for everything else */
1060
+
return "UCHE";
1061
+
}
1062
+
1063
+
static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
1064
+
{
1065
+
if (id == 0)
1066
+
return "CP";
1067
+
else if (id == 4)
1068
+
return "CCU";
1069
+
else if (id == 6)
1070
+
return "CDP Prefetch";
1071
+
1072
+
return a6xx_uche_fault_block(gpu, id);
1073
+
}
1074
+
1075
+
#define ARM_SMMU_FSR_TF BIT(1)
1076
+
#define ARM_SMMU_FSR_PF BIT(3)
1077
+
#define ARM_SMMU_FSR_EF BIT(4)
1078
+
1079
+
static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
1148
1080
{
1149
1081
struct msm_gpu *gpu = arg;
1082
+
struct adreno_smmu_fault_info *info = data;
1083
+
const char *type = "UNKNOWN";
1084
+
const char *block;
1085
+
bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
1150
1086
1151
-
pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
1087
+
/*
1088
+
* If we aren't going to be resuming later from fault_worker, then do
1089
+
* it now.
1090
+
*/
1091
+
if (!do_devcoredump) {
1092
+
gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
1093
+
}
1094
+
1095
+
/*
1096
+
* Print a default message if we couldn't get the data from the
1097
+
* adreno-smmu-priv
1098
+
*/
1099
+
if (!info) {
1100
+
pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
1152
1101
iova, flags,
1153
1102
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1154
1103
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1155
1104
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1156
1105
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1157
1106
1158
-
return -EFAULT;
1107
+
return 0;
1108
+
}
1109
+
1110
+
if (info->fsr & ARM_SMMU_FSR_TF)
1111
+
type = "TRANSLATION";
1112
+
else if (info->fsr & ARM_SMMU_FSR_PF)
1113
+
type = "PERMISSION";
1114
+
else if (info->fsr & ARM_SMMU_FSR_EF)
1115
+
type = "EXTERNAL";
1116
+
1117
+
block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
1118
+
1119
+
pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
1120
+
info->ttbr0, iova,
1121
+
flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
1122
+
type, block,
1123
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1124
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1125
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1126
+
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1127
+
1128
+
if (do_devcoredump) {
1129
+
/* Turn off the hangcheck timer to keep it from bothering us */
1130
+
del_timer(&gpu->hangcheck_timer);
1131
+
1132
+
gpu->fault_info.ttbr0 = info->ttbr0;
1133
+
gpu->fault_info.iova = iova;
1134
+
gpu->fault_info.flags = flags;
1135
+
gpu->fault_info.type = type;
1136
+
gpu->fault_info.block = block;
1137
+
1138
+
kthread_queue_work(gpu->worker, &gpu->fault_work);
1139
+
}
1140
+
1141
+
return 0;
1159
1142
}
1160
1143
1161
1144
static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
···
1300
1093
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1301
1094
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1302
1095
struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1096
+
1097
+
/*
1098
+
* If stalled on SMMU fault, we could trip the GPU's hang detection,
1099
+
* but the fault handler will trigger the devcore dump, and we want
1100
+
* to otherwise resume normally rather than killing the submit, so
1101
+
* just bail.
1102
+
*/
1103
+
if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
1104
+
return;
1303
1105
1304
1106
/*
1305
1107
* Force the GPU to stay on until after we finish
···
1555
1339
1556
1340
adreno_gpu_cleanup(adreno_gpu);
1557
1341
1558
-
if (a6xx_gpu->opp_table)
1559
-
dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
1560
-
1561
1342
kfree(a6xx_gpu);
1562
1343
}
1563
1344
···
1687
1474
static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
1688
1475
u32 revn)
1689
1476
{
1690
-
struct opp_table *opp_table;
1691
1477
u32 supp_hw = UINT_MAX;
1692
1478
u16 speedbin;
1693
1479
int ret;
···
1709
1497
supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
1710
1498
1711
1499
done:
1712
-
opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1713
-
if (IS_ERR(opp_table))
1714
-
return PTR_ERR(opp_table);
1500
+
ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1501
+
if (ret)
1502
+
return ret;
1715
1503
1716
-
a6xx_gpu->opp_table = opp_table;
1717
1504
return 0;
1718
1505
}
1719
1506
···
1772
1561
*/
1773
1562
info = adreno_info(config->rev);
1774
1563
1775
-
if (info && info->revn == 650)
1564
+
if (info && (info->revn == 650 || info->revn == 660))
1776
1565
adreno_gpu->base.hw_apriv = true;
1777
1566
1778
1567
a6xx_llc_slices_init(pdev, a6xx_gpu);
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+35
-9
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+35
-9
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
113
113
struct a6xx_crashdumper *dumper)
114
114
{
115
115
dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
116
-
SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
116
+
SZ_1M, MSM_BO_WC, gpu->aspace,
117
117
&dumper->bo, &dumper->iova);
118
118
119
119
if (!IS_ERR(dumper->ptr))
···
832
832
a6xx_get_ahb_gpu_registers(gpu,
833
833
a6xx_state, &a6xx_vbif_reglist,
834
834
&a6xx_state->registers[index++]);
835
+
if (!dumper) {
836
+
/*
837
+
* We can't use the crashdumper when the SMMU is stalled,
838
+
* because the GPU has no memory access until we resume
839
+
* translation (but we don't want to do that until after
840
+
* we have captured as much useful GPU state as possible).
841
+
* So instead collect registers via the CPU:
842
+
*/
843
+
for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
844
+
a6xx_get_ahb_gpu_registers(gpu,
845
+
a6xx_state, &a6xx_reglist[i],
846
+
&a6xx_state->registers[index++]);
847
+
return;
848
+
}
835
849
836
850
for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
837
851
a6xx_get_crashdumper_registers(gpu,
···
919
905
920
906
struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
921
907
{
922
-
struct a6xx_crashdumper dumper = { 0 };
908
+
struct a6xx_crashdumper _dumper = { 0 }, *dumper = NULL;
923
909
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
924
910
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
925
911
struct a6xx_gpu_state *a6xx_state = kzalloc(sizeof(*a6xx_state),
926
912
GFP_KERNEL);
913
+
bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) &
914
+
A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT);
927
915
928
916
if (!a6xx_state)
929
917
return ERR_PTR(-ENOMEM);
···
944
928
/* Get the banks of indexed registers */
945
929
a6xx_get_indexed_registers(gpu, a6xx_state);
946
930
947
-
/* Try to initialize the crashdumper */
948
-
if (!a6xx_crashdumper_init(gpu, &dumper)) {
949
-
a6xx_get_registers(gpu, a6xx_state, &dumper);
950
-
a6xx_get_shaders(gpu, a6xx_state, &dumper);
951
-
a6xx_get_clusters(gpu, a6xx_state, &dumper);
952
-
a6xx_get_dbgahb_clusters(gpu, a6xx_state, &dumper);
931
+
/*
932
+
* Try to initialize the crashdumper, if we are not dumping state
933
+
* with the SMMU stalled. The crashdumper needs memory access to
934
+
* write out GPU state, so we need to skip this when the SMMU is
935
+
* stalled in response to an iova fault
936
+
*/
937
+
if (!stalled && !a6xx_crashdumper_init(gpu, &_dumper)) {
938
+
dumper = &_dumper;
939
+
}
953
940
954
-
msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
941
+
a6xx_get_registers(gpu, a6xx_state, dumper);
942
+
943
+
if (dumper) {
944
+
a6xx_get_shaders(gpu, a6xx_state, dumper);
945
+
a6xx_get_clusters(gpu, a6xx_state, dumper);
946
+
a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
947
+
948
+
msm_gem_kernel_put(dumper->bo, gpu->aspace, true);
955
949
}
956
950
957
951
if (snapshot_debugbus)
+33
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+33
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
···
351
351
msg->cnoc_cmds_data[1][0] = 0x60000001;
352
352
}
353
353
354
+
static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
355
+
{
356
+
/*
357
+
* Send a single "off" entry just to get things running
358
+
* TODO: bus scaling
359
+
*/
360
+
msg->bw_level_num = 1;
361
+
362
+
msg->ddr_cmds_num = 3;
363
+
msg->ddr_wait_bitmask = 0x01;
364
+
365
+
msg->ddr_cmds_addrs[0] = 0x50004;
366
+
msg->ddr_cmds_addrs[1] = 0x500a0;
367
+
msg->ddr_cmds_addrs[2] = 0x50000;
368
+
369
+
msg->ddr_cmds_data[0][0] = 0x40000000;
370
+
msg->ddr_cmds_data[0][1] = 0x40000000;
371
+
msg->ddr_cmds_data[0][2] = 0x40000000;
372
+
373
+
/*
374
+
* These are the CX (CNOC) votes - these are used by the GMU but the
375
+
* votes are known and fixed for the target
376
+
*/
377
+
msg->cnoc_cmds_num = 1;
378
+
msg->cnoc_wait_bitmask = 0x01;
379
+
380
+
msg->cnoc_cmds_addrs[0] = 0x50070;
381
+
msg->cnoc_cmds_data[0][0] = 0x40000000;
382
+
msg->cnoc_cmds_data[1][0] = 0x60000001;
383
+
}
384
+
354
385
static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
355
386
{
356
387
/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
···
432
401
a640_build_bw_table(&msg);
433
402
else if (adreno_is_a650(adreno_gpu))
434
403
a650_build_bw_table(&msg);
404
+
else if (adreno_is_a660(adreno_gpu))
405
+
a660_build_bw_table(&msg);
435
406
else
436
407
a6xx_build_bw_table(&msg);
437
408
+14
-14
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+14
-14
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
+14
drivers/gpu/drm/msm/adreno/adreno_device.c
+14
drivers/gpu/drm/msm/adreno/adreno_device.c
···
287
287
.init = a6xx_gpu_init,
288
288
.zapfw = "a650_zap.mdt",
289
289
.hwcg = a650_hwcg,
290
+
}, {
291
+
.rev = ADRENO_REV(6, 6, 0, ANY_ID),
292
+
.revn = 660,
293
+
.name = "A660",
294
+
.fw = {
295
+
[ADRENO_FW_SQE] = "a660_sqe.fw",
296
+
[ADRENO_FW_GMU] = "a660_gmu.bin",
297
+
},
298
+
.gmem = SZ_1M + SZ_512K,
299
+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
300
+
.init = a6xx_gpu_init,
301
+
.zapfw = "a660_zap.mdt",
302
+
.hwcg = a660_hwcg,
290
303
},
291
304
};
292
305
···
479
466
config.rev.minor, config.rev.patchid);
480
467
481
468
priv->is_a2xx = config.rev.core == 2;
469
+
priv->has_cached_coherent = config.rev.core >= 6;
482
470
483
471
gpu = info->init(drm);
484
472
if (IS_ERR(gpu)) {
+19
-7
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+19
-7
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
239
239
*value = adreno_gpu->gmem;
240
240
return 0;
241
241
case MSM_PARAM_GMEM_BASE:
242
-
*value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0;
242
+
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
243
243
return 0;
244
244
case MSM_PARAM_CHIP_ID:
245
245
*value = adreno_gpu->rev.patchid |
···
391
391
void *ptr;
392
392
393
393
ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
394
-
MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
394
+
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
395
395
396
396
if (IS_ERR(ptr))
397
397
return ERR_CAST(ptr);
···
408
408
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
409
409
int ret, i;
410
410
411
-
DBG("%s", gpu->name);
411
+
VERB("%s", gpu->name);
412
412
413
413
ret = adreno_load_fw(adreno_gpu);
414
414
if (ret)
···
684
684
adreno_gpu->info->revn, adreno_gpu->rev.core,
685
685
adreno_gpu->rev.major, adreno_gpu->rev.minor,
686
686
adreno_gpu->rev.patchid);
687
+
/*
688
+
* If this is state collected due to iova fault, so fault related info
689
+
*
690
+
* TTBR0 would not be zero, so this is a good way to distinguish
691
+
*/
692
+
if (state->fault_info.ttbr0) {
693
+
const struct msm_gpu_fault_info *info = &state->fault_info;
694
+
695
+
drm_puts(p, "fault-info:\n");
696
+
drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0);
697
+
drm_printf(p, " - iova=%.16lx\n", info->iova);
698
+
drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
699
+
drm_printf(p, " - type=%s\n", info->type);
700
+
drm_printf(p, " - source=%s\n", info->block);
701
+
}
687
702
688
703
drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
689
704
···
856
841
if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
857
842
ret = adreno_get_legacy_pwrlevels(dev);
858
843
else {
859
-
ret = dev_pm_opp_of_add_table(dev);
844
+
ret = devm_pm_opp_of_add_table(dev);
860
845
if (ret)
861
846
DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
862
847
}
···
961
946
pm_runtime_disable(&priv->gpu_pdev->dev);
962
947
963
948
msm_gpu_cleanup(&adreno_gpu->base);
964
-
965
-
icc_put(gpu->icc_path);
966
-
icc_put(gpu->ocmem_icc_path);
967
949
}
+12
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+12
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
55
55
u32 value;
56
56
};
57
57
58
-
extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
58
+
extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
59
59
60
60
struct adreno_info {
61
61
struct adreno_rev rev;
···
245
245
static inline int adreno_is_a650(struct adreno_gpu *gpu)
246
246
{
247
247
return gpu->revn == 650;
248
+
}
249
+
250
+
static inline int adreno_is_a660(struct adreno_gpu *gpu)
251
+
{
252
+
return gpu->revn == 660;
253
+
}
254
+
255
+
/* check for a650, a660, or any derivatives */
256
+
static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
257
+
{
258
+
return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 660;
248
259
}
249
260
250
261
int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
+81
-42
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+81
-42
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25
-
Copyright (C) 2013-2020 by the following authors:
25
+
Copyright (C) 2013-2021 by the following authors:
26
26
- Rob Clark <robdclark@gmail.com> (robclark)
27
27
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
28
···
247
247
CP_DRAW_INDX_INDIRECT = 41,
248
248
CP_DRAW_INDIRECT_MULTI = 42,
249
249
CP_DRAW_AUTO = 36,
250
-
CP_UNKNOWN_19 = 25,
251
-
CP_UNKNOWN_1A = 26,
252
-
CP_UNKNOWN_4E = 78,
250
+
CP_DRAW_PRED_ENABLE_GLOBAL = 25,
251
+
CP_DRAW_PRED_ENABLE_LOCAL = 26,
252
+
CP_DRAW_PRED_SET = 78,
253
253
CP_WIDE_REG_WRITE = 116,
254
254
CP_SCRATCH_TO_REG = 77,
255
255
CP_REG_TO_SCRATCH = 74,
···
267
267
CP_SKIP_IB2_ENABLE_GLOBAL = 29,
268
268
CP_SKIP_IB2_ENABLE_LOCAL = 35,
269
269
CP_SET_SUBDRAW_SIZE = 53,
270
+
CP_WHERE_AM_I = 98,
270
271
CP_SET_VISIBILITY_OVERRIDE = 100,
271
272
CP_PREEMPT_ENABLE_GLOBAL = 105,
272
273
CP_PREEMPT_ENABLE_LOCAL = 106,
···
299
298
CP_SET_BIN_DATA5_OFFSET = 46,
300
299
CP_SET_CTXSWITCH_IB = 85,
301
300
CP_REG_WRITE = 109,
302
-
CP_WHERE_AM_I = 98,
303
301
};
304
302
305
303
enum adreno_state_block {
···
400
400
enum a6xx_draw_indirect_opcode {
401
401
INDIRECT_OP_NORMAL = 2,
402
402
INDIRECT_OP_INDEXED = 4,
403
+
INDIRECT_OP_INDIRECT_COUNT = 6,
404
+
INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
405
+
};
406
+
407
+
enum cp_draw_pred_src {
408
+
PRED_SRC_MEM = 5,
409
+
};
410
+
411
+
enum cp_draw_pred_test {
412
+
NE_0_PASS = 0,
413
+
EQ_0_PASS = 1,
403
414
};
404
415
405
416
enum cp_cond_function {
···
1051
1040
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1052
1041
}
1053
1042
1054
-
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002
1055
-
#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff
1056
-
#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0
1057
-
static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val)
1043
+
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
1044
+
1045
+
1046
+
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1047
+
1048
+
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
1049
+
1050
+
1051
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
1052
+
1053
+
#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
1054
+
1055
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
1056
+
1057
+
#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
1058
+
1059
+
1060
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
1061
+
1062
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
1063
+
1064
+
#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
1065
+
1066
+
1067
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
1068
+
1069
+
#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
1070
+
1071
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
1072
+
1073
+
#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
1074
+
1075
+
#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
1076
+
1077
+
#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
1078
+
#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
1079
+
1080
+
#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
1081
+
#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
1082
+
1083
+
#define REG_CP_DRAW_PRED_SET_0 0x00000000
1084
+
#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
1085
+
#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4
1086
+
static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
1058
1087
{
1059
-
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK;
1088
+
return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
1089
+
}
1090
+
#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
1091
+
#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8
1092
+
static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
1093
+
{
1094
+
return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
1060
1095
}
1061
1096
1062
-
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003
1063
-
1064
-
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005
1065
-
#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff
1066
-
#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0
1067
-
static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val)
1068
-
{
1069
-
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK;
1070
-
}
1071
-
1072
-
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
1073
-
1074
-
#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008
1075
-
#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff
1076
-
#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0
1077
-
static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val)
1078
-
{
1079
-
return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK;
1080
-
}
1097
+
#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
1081
1098
1082
1099
static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1083
1100
+42
-188
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+42
-188
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
···
22
22
struct dpu_kms *dpu_kms = arg;
23
23
struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
24
24
struct dpu_irq_callback *cb;
25
-
unsigned long irq_flags;
26
25
27
-
pr_debug("irq_idx=%d\n", irq_idx);
26
+
VERB("irq_idx=%d\n", irq_idx);
28
27
29
-
if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
30
-
DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
31
-
atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
32
-
}
28
+
if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
29
+
DRM_ERROR("no registered cb, idx:%d\n", irq_idx);
33
30
34
31
atomic_inc(&irq_obj->irq_counts[irq_idx]);
35
32
36
33
/*
37
34
* Perform registered function callback
38
35
*/
39
-
spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
40
36
list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list)
41
37
if (cb->func)
42
38
cb->func(cb->arg, irq_idx);
43
-
spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
44
-
45
-
/*
46
-
* Clear pending interrupt status in HW.
47
-
* NOTE: dpu_core_irq_callback_handler is protected by top-level
48
-
* spinlock, so it is safe to clear any interrupt status here.
49
-
*/
50
-
dpu_kms->hw_intr->ops.clear_intr_status_nolock(
51
-
dpu_kms->hw_intr,
52
-
irq_idx);
53
-
}
54
-
55
-
int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
56
-
enum dpu_intr_type intr_type, u32 instance_idx)
57
-
{
58
-
if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup)
59
-
return -EINVAL;
60
-
61
-
return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr,
62
-
intr_type, instance_idx);
63
-
}
64
-
65
-
/**
66
-
* _dpu_core_irq_enable - enable core interrupt given by the index
67
-
* @dpu_kms: Pointer to dpu kms context
68
-
* @irq_idx: interrupt index
69
-
*/
70
-
static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
71
-
{
72
-
unsigned long irq_flags;
73
-
int ret = 0, enable_count;
74
-
75
-
if (!dpu_kms->hw_intr ||
76
-
!dpu_kms->irq_obj.enable_counts ||
77
-
!dpu_kms->irq_obj.irq_counts) {
78
-
DPU_ERROR("invalid params\n");
79
-
return -EINVAL;
80
-
}
81
-
82
-
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
83
-
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
84
-
return -EINVAL;
85
-
}
86
-
87
-
enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
88
-
DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
89
-
trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
90
-
91
-
if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
92
-
ret = dpu_kms->hw_intr->ops.enable_irq(
93
-
dpu_kms->hw_intr,
94
-
irq_idx);
95
-
if (ret)
96
-
DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
97
-
irq_idx);
98
-
99
-
DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
100
-
101
-
spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
102
-
/* empty callback list but interrupt is enabled */
103
-
if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]))
104
-
DPU_ERROR("irq_idx=%d enabled with no callback\n",
105
-
irq_idx);
106
-
spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
107
-
}
108
-
109
-
return ret;
110
-
}
111
-
112
-
int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
113
-
{
114
-
int i, ret = 0, counts;
115
-
116
-
if (!irq_idxs || !irq_count) {
117
-
DPU_ERROR("invalid params\n");
118
-
return -EINVAL;
119
-
}
120
-
121
-
counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
122
-
if (counts)
123
-
DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
124
-
125
-
for (i = 0; (i < irq_count) && !ret; i++)
126
-
ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
127
-
128
-
return ret;
129
-
}
130
-
131
-
/**
132
-
* _dpu_core_irq_disable - disable core interrupt given by the index
133
-
* @dpu_kms: Pointer to dpu kms context
134
-
* @irq_idx: interrupt index
135
-
*/
136
-
static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
137
-
{
138
-
int ret = 0, enable_count;
139
-
140
-
if (!dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
141
-
DPU_ERROR("invalid params\n");
142
-
return -EINVAL;
143
-
}
144
-
145
-
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
146
-
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
147
-
return -EINVAL;
148
-
}
149
-
150
-
enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
151
-
DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
152
-
trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
153
-
154
-
if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
155
-
ret = dpu_kms->hw_intr->ops.disable_irq(
156
-
dpu_kms->hw_intr,
157
-
irq_idx);
158
-
if (ret)
159
-
DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
160
-
irq_idx);
161
-
DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
162
-
}
163
-
164
-
return ret;
165
-
}
166
-
167
-
int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
168
-
{
169
-
int i, ret = 0, counts;
170
-
171
-
if (!irq_idxs || !irq_count) {
172
-
DPU_ERROR("invalid params\n");
173
-
return -EINVAL;
174
-
}
175
-
176
-
counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
177
-
if (counts == 2)
178
-
DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
179
-
180
-
for (i = 0; (i < irq_count) && !ret; i++)
181
-
ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
182
-
183
-
return ret;
184
39
}
185
40
186
41
u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
···
72
217
return -EINVAL;
73
218
}
74
219
75
-
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
220
+
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
76
221
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
77
222
return -EINVAL;
78
223
}
79
224
80
-
DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
225
+
VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
81
226
82
-
spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
227
+
irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
83
228
trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb);
84
229
list_del_init(®ister_irq_cb->list);
85
230
list_add_tail(®ister_irq_cb->list,
86
231
&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
87
-
spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
232
+
if (list_is_first(®ister_irq_cb->list,
233
+
&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
234
+
int ret = dpu_kms->hw_intr->ops.enable_irq_locked(
235
+
dpu_kms->hw_intr,
236
+
irq_idx);
237
+
if (ret)
238
+
DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
239
+
irq_idx);
240
+
}
241
+
dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
88
242
89
243
return 0;
90
244
}
···
116
252
return -EINVAL;
117
253
}
118
254
119
-
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
255
+
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
120
256
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
121
257
return -EINVAL;
122
258
}
123
259
124
-
DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
260
+
VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
125
261
126
-
spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
262
+
irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
127
263
trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
128
264
list_del_init(®ister_irq_cb->list);
129
265
/* empty callback list but interrupt is still enabled */
130
-
if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) &&
131
-
atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]))
132
-
DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx);
133
-
spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
266
+
if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
267
+
int ret = dpu_kms->hw_intr->ops.disable_irq_locked(
268
+
dpu_kms->hw_intr,
269
+
irq_idx);
270
+
if (ret)
271
+
DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
272
+
irq_idx);
273
+
VERB("irq_idx=%d ret=%d\n", irq_idx, ret);
274
+
}
275
+
dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
134
276
135
277
return 0;
136
278
}
···
160
290
#ifdef CONFIG_DEBUG_FS
161
291
static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
162
292
{
163
-
struct dpu_irq *irq_obj = s->private;
293
+
struct dpu_kms *dpu_kms = s->private;
294
+
struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
164
295
struct dpu_irq_callback *cb;
165
296
unsigned long irq_flags;
166
-
int i, irq_count, enable_count, cb_count;
297
+
int i, irq_count, cb_count;
167
298
168
-
if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl))
299
+
if (WARN_ON(!irq_obj->irq_cb_tbl))
169
300
return 0;
170
301
171
302
for (i = 0; i < irq_obj->total_irqs; i++) {
172
-
spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);
303
+
irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
173
304
cb_count = 0;
174
305
irq_count = atomic_read(&irq_obj->irq_counts[i]);
175
-
enable_count = atomic_read(&irq_obj->enable_counts[i]);
176
306
list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
177
307
cb_count++;
178
-
spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);
308
+
dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
179
309
180
-
if (irq_count || enable_count || cb_count)
181
-
seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n",
182
-
i, irq_count, enable_count, cb_count);
310
+
if (irq_count || cb_count)
311
+
seq_printf(s, "idx:%d irq:%d cb:%d\n",
312
+
i, irq_count, cb_count);
183
313
}
184
314
185
315
return 0;
···
190
320
void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,
191
321
struct dentry *parent)
192
322
{
193
-
debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj,
323
+
debugfs_create_file("core_irq", 0600, parent, dpu_kms,
194
324
&dpu_debugfs_core_irq_fops);
195
325
}
196
326
#endif
···
204
334
dpu_disable_all_irqs(dpu_kms);
205
335
pm_runtime_put_sync(&dpu_kms->pdev->dev);
206
336
207
-
spin_lock_init(&dpu_kms->irq_obj.cb_lock);
208
-
209
337
/* Create irq callbacks for all possible irq_idx */
210
-
dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
338
+
dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
211
339
dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
212
340
sizeof(struct list_head), GFP_KERNEL);
213
-
dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
214
-
sizeof(atomic_t), GFP_KERNEL);
215
341
dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
216
342
sizeof(atomic_t), GFP_KERNEL);
217
343
for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) {
218
344
INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]);
219
-
atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0);
220
345
atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0);
221
346
}
222
347
}
···
222
357
223
358
pm_runtime_get_sync(&dpu_kms->pdev->dev);
224
359
for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
225
-
if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) ||
226
-
!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
360
+
if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
227
361
DPU_ERROR("irq_idx=%d still enabled/registered\n", i);
228
362
229
363
dpu_clear_all_irqs(dpu_kms);
···
230
366
pm_runtime_put_sync(&dpu_kms->pdev->dev);
231
367
232
368
kfree(dpu_kms->irq_obj.irq_cb_tbl);
233
-
kfree(dpu_kms->irq_obj.enable_counts);
234
369
kfree(dpu_kms->irq_obj.irq_counts);
235
370
dpu_kms->irq_obj.irq_cb_tbl = NULL;
236
-
dpu_kms->irq_obj.enable_counts = NULL;
237
371
dpu_kms->irq_obj.irq_counts = NULL;
238
372
dpu_kms->irq_obj.total_irqs = 0;
239
373
}
···
239
377
irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
240
378
{
241
379
/*
242
-
* Read interrupt status from all sources. Interrupt status are
243
-
* stored within hw_intr.
244
-
* Function will also clear the interrupt status after reading.
245
-
* Individual interrupt status bit will only get stored if it
246
-
* is enabled.
247
-
*/
248
-
dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
249
-
250
-
/*
251
380
* Dispatch to HW driver to handle interrupt lookup that is being
252
381
* fired. When matching interrupt is located, HW driver will call to
253
382
* dpu_core_irq_callback_handler with the irq_idx from the lookup table.
254
383
* dpu_core_irq_callback_handler will perform the registered function
255
384
* callback, and do the interrupt status clearing once the registered
256
385
* callback is finished.
386
+
* Function will also clear the interrupt status after reading.
257
387
*/
258
388
dpu_kms->hw_intr->ops.dispatch_irqs(
259
389
dpu_kms->hw_intr,
-43
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
-43
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
···
30
30
irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
31
31
32
32
/**
33
-
* dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW
34
-
* interrupt mapping table.
35
-
* @dpu_kms: DPU handle
36
-
* @intr_type: DPU HW interrupt type for lookup
37
-
* @instance_idx: DPU HW block instance defined in dpu_hw_mdss.h
38
-
* @return: irq_idx or -EINVAL when fail to lookup
39
-
*/
40
-
int dpu_core_irq_idx_lookup(
41
-
struct dpu_kms *dpu_kms,
42
-
enum dpu_intr_type intr_type,
43
-
uint32_t instance_idx);
44
-
45
-
/**
46
-
* dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs
47
-
* @dpu_kms: DPU handle
48
-
* @irq_idxs: Array of irq index
49
-
* @irq_count: Number of irq_idx provided in the array
50
-
* @return: 0 for success enabling IRQ, otherwise failure
51
-
*
52
-
* This function increments count on each enable and decrements on each
53
-
* disable. Interrupts is enabled if count is 0 before increment.
54
-
*/
55
-
int dpu_core_irq_enable(
56
-
struct dpu_kms *dpu_kms,
57
-
int *irq_idxs,
58
-
uint32_t irq_count);
59
-
60
-
/**
61
-
* dpu_core_irq_disable - IRQ helper function for disabling one of more IRQs
62
-
* @dpu_kms: DPU handle
63
-
* @irq_idxs: Array of irq index
64
-
* @irq_count: Number of irq_idx provided in the array
65
-
* @return: 0 for success disabling IRQ, otherwise failure
66
-
*
67
-
* This function increments count on each enable and decrements on each
68
-
* disable. Interrupts is disabled if count is 0 after decrement.
69
-
*/
70
-
int dpu_core_irq_disable(
71
-
struct dpu_kms *dpu_kms,
72
-
int *irq_idxs,
73
-
uint32_t irq_count);
74
-
75
-
/**
76
33
* dpu_core_irq_read - IRQ helper function for reading IRQ status
77
34
* @dpu_kms: DPU handle
78
35
* @irq_idx: irq index
+11
-11
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+11
-11
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
···
132
132
perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
133
133
}
134
134
135
-
DPU_DEBUG(
135
+
DRM_DEBUG_ATOMIC(
136
136
"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
137
137
crtc->base.id, perf->core_clk_rate,
138
138
perf->max_per_pipe_ib, perf->bw_ctl);
···
178
178
struct dpu_crtc_state *tmp_cstate =
179
179
to_dpu_crtc_state(tmp_crtc->state);
180
180
181
-
DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
181
+
DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n",
182
182
tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
183
183
tmp_cstate->bw_control);
184
184
···
187
187
188
188
/* convert bandwidth to kb */
189
189
bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000);
190
-
DPU_DEBUG("calculated bandwidth=%uk\n", bw);
190
+
DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw);
191
191
192
192
threshold = kms->catalog->perf.max_bw_high;
193
193
194
-
DPU_DEBUG("final threshold bw limit = %d\n", threshold);
194
+
DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold);
195
195
196
196
if (!threshold) {
197
197
DPU_ERROR("no bandwidth limits specified\n");
···
228
228
229
229
perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
230
230
231
-
DPU_DEBUG("crtc=%d bw=%llu paths:%d\n",
231
+
DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n",
232
232
tmp_crtc->base.id,
233
233
dpu_cstate->new_perf.bw_ctl, kms->num_paths);
234
234
}
···
278
278
/* Release the bandwidth */
279
279
if (kms->perf.enable_bw_release) {
280
280
trace_dpu_cmd_release_bw(crtc->base.id);
281
-
DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id);
281
+
DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id);
282
282
dpu_crtc->cur_perf.bw_ctl = 0;
283
283
_dpu_core_perf_crtc_update_bus(kms, crtc);
284
284
}
···
314
314
if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED)
315
315
clk_rate = kms->perf.fix_core_clk_rate;
316
316
317
-
DPU_DEBUG("clk:%llu\n", clk_rate);
317
+
DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
318
318
319
319
return clk_rate;
320
320
}
···
344
344
dpu_crtc = to_dpu_crtc(crtc);
345
345
dpu_cstate = to_dpu_crtc_state(crtc->state);
346
346
347
-
DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",
347
+
DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n",
348
348
crtc->base.id, stop_req, kms->perf.core_clk_rate);
349
349
350
350
old = &dpu_crtc->cur_perf;
···
362
362
(new->max_per_pipe_ib > old->max_per_pipe_ib))) ||
363
363
(!params_changed && ((new->bw_ctl < old->bw_ctl) ||
364
364
(new->max_per_pipe_ib < old->max_per_pipe_ib)))) {
365
-
DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
365
+
DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n",
366
366
crtc->base.id, params_changed,
367
367
new->bw_ctl, old->bw_ctl);
368
368
old->bw_ctl = new->bw_ctl;
···
378
378
update_clk = true;
379
379
}
380
380
} else {
381
-
DPU_DEBUG("crtc=%d disable\n", crtc->base.id);
381
+
DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id);
382
382
memset(old, 0, sizeof(*old));
383
383
update_bus = true;
384
384
update_clk = true;
···
413
413
}
414
414
415
415
kms->perf.core_clk_rate = clk_rate;
416
-
DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
416
+
DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate);
417
417
}
418
418
return 0;
419
419
}
+20
-23
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+20
-23
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
57
57
{
58
58
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
59
59
60
-
DPU_DEBUG("\n");
61
-
62
60
if (!crtc)
63
61
return;
64
62
···
161
163
lm->ops.setup_blend_config(lm, pstate->stage,
162
164
0xFF, 0, blend_op);
163
165
164
-
DPU_DEBUG("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
166
+
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
165
167
&format->base.pixel_format, format->alpha_enable, blend_op);
166
168
}
167
169
···
218
220
219
221
dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
220
222
set_bit(dpu_plane_pipe(plane), fetch_active);
221
-
DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
223
+
224
+
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
222
225
crtc->base.id,
223
226
pstate->stage,
224
227
plane->base.id,
···
277
278
struct dpu_hw_mixer *lm;
278
279
int i;
279
280
280
-
DPU_DEBUG("%s\n", dpu_crtc->name);
281
+
DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
281
282
282
283
for (i = 0; i < cstate->num_mixers; i++) {
283
284
mixer[i].mixer_op_mode = 0;
···
304
305
/* stage config flush mask */
305
306
ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
306
307
307
-
DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
308
+
DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
308
309
mixer[i].hw_lm->idx - LM_0,
309
310
mixer[i].mixer_op_mode,
310
311
ctl->idx - CTL_0,
···
387
388
388
389
DPU_ATRACE_BEGIN("crtc_frame_event");
389
390
390
-
DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
391
+
DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
391
392
ktime_to_ns(fevent->ts));
392
393
393
394
if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
···
405
406
trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
406
407
fevent->event);
407
408
}
408
-
409
-
if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE)
410
-
dpu_core_perf_crtc_update(crtc, 0, false);
411
409
412
410
if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
413
411
| DPU_ENCODER_FRAME_EVENT_ERROR))
···
473
477
void dpu_crtc_complete_commit(struct drm_crtc *crtc)
474
478
{
475
479
trace_dpu_crtc_complete_commit(DRMID(crtc));
480
+
dpu_core_perf_crtc_update(crtc, 0, false);
476
481
_dpu_crtc_complete_flip(crtc);
477
482
}
478
483
···
555
558
/* stage config flush mask */
556
559
ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
557
560
558
-
DPU_DEBUG("lm %d, ctl %d, flush mask 0x%x\n",
561
+
DRM_DEBUG_ATOMIC("lm %d, ctl %d, flush mask 0x%x\n",
559
562
mixer[i].hw_lm->idx - DSPP_0,
560
563
ctl->idx - CTL_0,
561
564
mixer[i].flush_mask);
···
569
572
struct drm_encoder *encoder;
570
573
571
574
if (!crtc->state->enable) {
572
-
DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
575
+
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
573
576
crtc->base.id, crtc->state->enable);
574
577
return;
575
578
}
576
579
577
-
DPU_DEBUG("crtc%d\n", crtc->base.id);
580
+
DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
578
581
579
582
_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
580
583
···
614
617
struct dpu_crtc_state *cstate;
615
618
616
619
if (!crtc->state->enable) {
617
-
DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
620
+
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
618
621
crtc->base.id, crtc->state->enable);
619
622
return;
620
623
}
621
624
622
-
DPU_DEBUG("crtc%d\n", crtc->base.id);
625
+
DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
623
626
624
627
dpu_crtc = to_dpu_crtc(crtc);
625
628
cstate = to_dpu_crtc_state(crtc->state);
···
672
675
{
673
676
struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
674
677
675
-
DPU_DEBUG("crtc%d\n", crtc->base.id);
678
+
DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
676
679
677
680
__drm_atomic_helper_crtc_destroy_state(state);
678
681
···
685
688
int ret, rc = 0;
686
689
687
690
if (!atomic_read(&dpu_crtc->frame_pending)) {
688
-
DPU_DEBUG("no frames pending\n");
691
+
DRM_DEBUG_ATOMIC("no frames pending\n");
689
692
return 0;
690
693
}
691
694
···
728
731
729
732
if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
730
733
/* acquire bandwidth and other resources */
731
-
DPU_DEBUG("crtc%d first commit\n", crtc->base.id);
734
+
DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
732
735
} else
733
-
DPU_DEBUG("crtc%d commit\n", crtc->base.id);
736
+
DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
734
737
735
738
dpu_crtc->play_count++;
736
739
···
905
908
pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
906
909
907
910
if (!crtc_state->enable || !crtc_state->active) {
908
-
DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
911
+
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
909
912
crtc->base.id, crtc_state->enable,
910
913
crtc_state->active);
911
914
memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
···
913
916
}
914
917
915
918
mode = &crtc_state->adjusted_mode;
916
-
DPU_DEBUG("%s: check\n", dpu_crtc->name);
919
+
DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
917
920
918
921
/* force a full mode set if active state changed */
919
922
if (crtc_state->active_changed)
···
1021
1024
}
1022
1025
1023
1026
pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
1024
-
DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos);
1027
+
DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
1025
1028
}
1026
1029
1027
1030
for (i = 0; i < multirect_count; i++) {
···
1373
1376
/* initialize event handling */
1374
1377
spin_lock_init(&dpu_crtc->event_lock);
1375
1378
1376
-
DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
1379
+
DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
1377
1380
return crtc;
1378
1381
}
+39
-71
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+39
-71
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3
+
* Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
4
4
* Copyright (C) 2013 Red Hat
5
5
* Author: Rob Clark <robdclark@gmail.com>
6
6
*/
···
26
26
#include "dpu_crtc.h"
27
27
#include "dpu_trace.h"
28
28
#include "dpu_core_irq.h"
29
+
#include "disp/msm_disp_snapshot.h"
29
30
30
-
#define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
31
+
#define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
31
32
(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
32
33
33
34
#define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
34
35
(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
35
36
36
-
#define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
37
+
#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
37
38
(p) ? (p)->parent->base.id : -1, \
38
39
(p) ? (p)->intf_idx - INTF_0 : -1, \
39
40
(p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
···
254
253
}
255
254
256
255
static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
257
-
int32_t hw_id, struct dpu_encoder_wait_info *info);
256
+
u32 irq_idx, struct dpu_encoder_wait_info *info);
258
257
259
258
int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
260
259
enum dpu_intr_idx intr_idx,
···
274
273
275
274
/* return EWOULDBLOCK since we know the wait isn't necessary */
276
275
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
277
-
DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
278
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
276
+
DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
277
+
DRMID(phys_enc->parent), intr_idx,
279
278
irq->irq_idx);
280
279
return -EWOULDBLOCK;
281
280
}
282
281
283
282
if (irq->irq_idx < 0) {
284
-
DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
285
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
283
+
DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
284
+
DRMID(phys_enc->parent), intr_idx,
286
285
irq->name);
287
286
return 0;
288
287
}
289
288
290
-
DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
291
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
289
+
DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
290
+
DRMID(phys_enc->parent), intr_idx,
292
291
irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
293
292
atomic_read(wait_info->atomic_cnt));
294
293
295
294
ret = dpu_encoder_helper_wait_event_timeout(
296
295
DRMID(phys_enc->parent),
297
-
irq->hw_idx,
296
+
irq->irq_idx,
298
297
wait_info);
299
298
300
299
if (ret <= 0) {
···
304
303
unsigned long flags;
305
304
306
305
DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
307
-
"hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
306
+
"irq=%d, pp=%d, atomic_cnt=%d",
308
307
DRMID(phys_enc->parent), intr_idx,
309
-
irq->hw_idx, irq->irq_idx,
308
+
irq->irq_idx,
310
309
phys_enc->hw_pp->idx - PINGPONG_0,
311
310
atomic_read(wait_info->atomic_cnt));
312
311
local_irq_save(flags);
···
316
315
} else {
317
316
ret = -ETIMEDOUT;
318
317
DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
319
-
"hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
318
+
"irq=%d, pp=%d, atomic_cnt=%d",
320
319
DRMID(phys_enc->parent), intr_idx,
321
-
irq->hw_idx, irq->irq_idx,
320
+
irq->irq_idx,
322
321
phys_enc->hw_pp->idx - PINGPONG_0,
323
322
atomic_read(wait_info->atomic_cnt));
324
323
}
325
324
} else {
326
325
ret = 0;
327
326
trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
328
-
intr_idx, irq->hw_idx, irq->irq_idx,
327
+
intr_idx, irq->irq_idx,
329
328
phys_enc->hw_pp->idx - PINGPONG_0,
330
329
atomic_read(wait_info->atomic_cnt));
331
330
}
···
345
344
}
346
345
irq = &phys_enc->irq[intr_idx];
347
346
348
-
if (irq->irq_idx >= 0) {
349
-
DPU_DEBUG_PHYS(phys_enc,
350
-
"skipping already registered irq %s type %d\n",
351
-
irq->name, irq->intr_type);
352
-
return 0;
353
-
}
354
-
355
-
irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
356
-
irq->intr_type, irq->hw_idx);
357
347
if (irq->irq_idx < 0) {
358
348
DPU_ERROR_PHYS(phys_enc,
359
-
"failed to lookup IRQ index for %s type:%d\n",
360
-
irq->name, irq->intr_type);
349
+
"invalid IRQ index:%d\n", irq->irq_idx);
361
350
return -EINVAL;
362
351
}
363
352
···
361
370
return ret;
362
371
}
363
372
364
-
ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
365
-
if (ret) {
366
-
DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
367
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
368
-
irq->irq_idx);
369
-
dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
370
-
irq->irq_idx, &irq->cb);
371
-
irq->irq_idx = -EINVAL;
372
-
return ret;
373
-
}
374
-
375
373
trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
376
-
irq->hw_idx, irq->irq_idx);
374
+
irq->irq_idx);
377
375
378
376
return ret;
379
377
}
···
377
397
378
398
/* silently skip irqs that weren't registered */
379
399
if (irq->irq_idx < 0) {
380
-
DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
381
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
400
+
DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
401
+
DRMID(phys_enc->parent), intr_idx,
382
402
irq->irq_idx);
383
403
return 0;
384
-
}
385
-
386
-
ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
387
-
if (ret) {
388
-
DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
389
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
390
-
irq->irq_idx, ret);
391
404
}
392
405
393
406
ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
394
407
&irq->cb);
395
408
if (ret) {
396
-
DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
397
-
DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
409
+
DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
410
+
DRMID(phys_enc->parent), intr_idx,
398
411
irq->irq_idx, ret);
399
412
}
400
413
401
414
trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
402
-
irq->hw_idx, irq->irq_idx);
403
-
404
-
irq->irq_idx = -EINVAL;
415
+
irq->irq_idx);
405
416
406
417
return 0;
407
418
}
···
791
820
792
821
/* return if the resource control is already in ON state */
793
822
if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
794
-
DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
823
+
DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
795
824
DRMID(drm_enc), sw_event);
796
825
mutex_unlock(&dpu_enc->rc_lock);
797
826
return 0;
798
827
} else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
799
828
dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
800
-
DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
829
+
DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
801
830
DRMID(drm_enc), sw_event,
802
831
dpu_enc->rc_state);
803
832
mutex_unlock(&dpu_enc->rc_lock);
···
1307
1336
1308
1337
DPU_ATRACE_BEGIN("encoder_underrun_callback");
1309
1338
atomic_inc(&phy_enc->underrun_cnt);
1339
+
1340
+
/* trigger dump only on the first underrun */
1341
+
if (atomic_read(&phy_enc->underrun_cnt) == 1)
1342
+
msm_disp_snapshot_state(drm_enc->dev);
1343
+
1310
1344
trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1311
1345
atomic_read(&phy_enc->underrun_cnt));
1312
1346
DPU_ATRACE_END("encoder_underrun_callback");
···
1429
1453
struct dpu_encoder_virt *dpu_enc = container_of(work,
1430
1454
struct dpu_encoder_virt, delayed_off_work.work);
1431
1455
1432
-
if (!dpu_enc) {
1433
-
DPU_ERROR("invalid dpu encoder\n");
1434
-
return;
1435
-
}
1436
-
1437
1456
dpu_encoder_resource_control(&dpu_enc->base,
1438
1457
DPU_ENC_RC_EVENT_ENTER_IDLE);
1439
1458
···
1508
1537
1509
1538
static int dpu_encoder_helper_wait_event_timeout(
1510
1539
int32_t drm_id,
1511
-
int32_t hw_id,
1540
+
u32 irq_idx,
1512
1541
struct dpu_encoder_wait_info *info)
1513
1542
{
1514
1543
int rc = 0;
···
1521
1550
atomic_read(info->atomic_cnt) == 0, jiffies);
1522
1551
time = ktime_to_ms(ktime_get());
1523
1552
1524
-
trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1553
+
trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
1525
1554
expected_time,
1526
1555
atomic_read(info->atomic_cnt));
1527
1556
/* If we timed out, counter is valid and time is less, wait again */
···
1536
1565
struct dpu_encoder_virt *dpu_enc;
1537
1566
struct dpu_hw_ctl *ctl;
1538
1567
int rc;
1568
+
struct drm_encoder *drm_enc;
1539
1569
1540
1570
dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1541
1571
ctl = phys_enc->hw_ctl;
1572
+
drm_enc = phys_enc->parent;
1542
1573
1543
1574
if (!ctl->ops.reset)
1544
1575
return;
1545
1576
1546
-
DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1577
+
DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1547
1578
ctl->idx);
1548
1579
1549
1580
rc = ctl->ops.reset(ctl);
1550
-
if (rc)
1581
+
if (rc) {
1551
1582
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1583
+
msm_disp_snapshot_state(drm_enc->dev);
1584
+
}
1552
1585
1553
1586
phys_enc->enable_state = DPU_ENC_ENABLED;
1554
1587
}
···
1771
1796
struct dpu_encoder_virt *dpu_enc = container_of(work,
1772
1797
struct dpu_encoder_virt, vsync_event_work);
1773
1798
ktime_t wakeup_time;
1774
-
1775
-
if (!dpu_enc) {
1776
-
DPU_ERROR("invalid dpu encoder\n");
1777
-
return;
1778
-
}
1779
1799
1780
1800
if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1781
1801
return;
···
2037
2067
phys_params.parent = &dpu_enc->base;
2038
2068
phys_params.parent_ops = &dpu_encoder_parent_ops;
2039
2069
phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2040
-
2041
-
DPU_DEBUG("\n");
2042
2070
2043
2071
switch (disp_info->intf_type) {
2044
2072
case DRM_MODE_ENCODER_DSI:
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
···
165
165
/**
166
166
* dpu_encoder_irq - tracking structure for interrupts
167
167
* @name: string name of interrupt
168
-
* @intr_type: Encoder interrupt type
169
168
* @intr_idx: Encoder interrupt enumeration
170
-
* @hw_idx: HW Block ID
171
169
* @irq_idx: IRQ interface lookup index from DPU IRQ framework
172
170
* will be -EINVAL if IRQ is not registered
173
171
* @irq_cb: interrupt callback
174
172
*/
175
173
struct dpu_encoder_irq {
176
174
const char *name;
177
-
enum dpu_intr_type intr_type;
178
175
enum dpu_intr_idx intr_idx;
179
-
int hw_idx;
180
176
int irq_idx;
181
177
struct dpu_irq_callback cb;
182
178
};
+21
-37
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+21
-37
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
3
+
* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
4
4
*/
5
5
6
6
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
···
11
11
#include "dpu_core_irq.h"
12
12
#include "dpu_formats.h"
13
13
#include "dpu_trace.h"
14
+
#include "disp/msm_disp_snapshot.h"
14
15
15
16
#define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
16
17
(e) && (e)->base.parent ? \
···
144
143
phys_enc);
145
144
}
146
145
147
-
static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
148
-
struct dpu_encoder_phys *phys_enc)
149
-
{
150
-
struct dpu_encoder_irq *irq;
151
-
152
-
irq = &phys_enc->irq[INTR_IDX_CTL_START];
153
-
irq->hw_idx = phys_enc->hw_ctl->idx;
154
-
irq->irq_idx = -EINVAL;
155
-
156
-
irq = &phys_enc->irq[INTR_IDX_PINGPONG];
157
-
irq->hw_idx = phys_enc->hw_pp->idx;
158
-
irq->irq_idx = -EINVAL;
159
-
160
-
irq = &phys_enc->irq[INTR_IDX_RDPTR];
161
-
irq->hw_idx = phys_enc->hw_pp->idx;
162
-
irq->irq_idx = -EINVAL;
163
-
164
-
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
165
-
irq->hw_idx = phys_enc->intf_idx;
166
-
irq->irq_idx = -EINVAL;
167
-
}
168
-
169
146
static void dpu_encoder_phys_cmd_mode_set(
170
147
struct dpu_encoder_phys *phys_enc,
171
148
struct drm_display_mode *mode,
···
151
172
{
152
173
struct dpu_encoder_phys_cmd *cmd_enc =
153
174
to_dpu_encoder_phys_cmd(phys_enc);
175
+
struct dpu_encoder_irq *irq;
154
176
155
177
if (!mode || !adj_mode) {
156
178
DPU_ERROR("invalid args\n");
···
161
181
DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
162
182
drm_mode_debug_printmodeline(adj_mode);
163
183
164
-
_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
184
+
irq = &phys_enc->irq[INTR_IDX_CTL_START];
185
+
irq->irq_idx = phys_enc->hw_ctl->caps->intr_start;
186
+
187
+
irq = &phys_enc->irq[INTR_IDX_PINGPONG];
188
+
irq->irq_idx = phys_enc->hw_pp->caps->intr_done;
189
+
190
+
irq = &phys_enc->irq[INTR_IDX_RDPTR];
191
+
irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr;
192
+
193
+
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
194
+
irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
165
195
}
166
196
167
197
static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
···
181
191
to_dpu_encoder_phys_cmd(phys_enc);
182
192
u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
183
193
bool do_log = false;
194
+
struct drm_encoder *drm_enc;
184
195
185
196
if (!phys_enc->hw_pp)
186
197
return -EINVAL;
198
+
199
+
drm_enc = phys_enc->parent;
187
200
188
201
cmd_enc->pp_timeout_report_cnt++;
189
202
if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {
···
196
203
do_log = true;
197
204
}
198
205
199
-
trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
206
+
trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(drm_enc),
200
207
phys_enc->hw_pp->idx - PINGPONG_0,
201
208
cmd_enc->pp_timeout_report_cnt,
202
209
atomic_read(&phys_enc->pending_kickoff_cnt),
···
205
212
/* to avoid flooding, only log first time, and "dead" time */
206
213
if (do_log) {
207
214
DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
208
-
DRMID(phys_enc->parent),
215
+
DRMID(drm_enc),
209
216
phys_enc->hw_pp->idx - PINGPONG_0,
210
217
phys_enc->hw_ctl->idx - CTL_0,
211
218
cmd_enc->pp_timeout_report_cnt,
212
219
atomic_read(&phys_enc->pending_kickoff_cnt));
213
-
220
+
msm_disp_snapshot_state(drm_enc->dev);
214
221
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
215
222
}
216
223
···
221
228
222
229
if (phys_enc->parent_ops->handle_frame_done)
223
230
phys_enc->parent_ops->handle_frame_done(
224
-
phys_enc->parent, phys_enc, frame_event);
231
+
drm_enc, phys_enc, frame_event);
225
232
226
233
return -ETIMEDOUT;
227
234
}
···
678
685
static int dpu_encoder_phys_cmd_wait_for_commit_done(
679
686
struct dpu_encoder_phys *phys_enc)
680
687
{
681
-
struct dpu_encoder_phys_cmd *cmd_enc;
682
-
683
-
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
684
-
685
688
/* only required for master controller */
686
689
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
687
690
return 0;
···
784
795
irq = &phys_enc->irq[i];
785
796
INIT_LIST_HEAD(&irq->cb.list);
786
797
irq->irq_idx = -EINVAL;
787
-
irq->hw_idx = -EINVAL;
788
798
irq->cb.arg = phys_enc;
789
799
}
790
800
791
801
irq = &phys_enc->irq[INTR_IDX_CTL_START];
792
802
irq->name = "ctl_start";
793
-
irq->intr_type = DPU_IRQ_TYPE_CTL_START;
794
803
irq->intr_idx = INTR_IDX_CTL_START;
795
804
irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
796
805
797
806
irq = &phys_enc->irq[INTR_IDX_PINGPONG];
798
807
irq->name = "pp_done";
799
-
irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
800
808
irq->intr_idx = INTR_IDX_PINGPONG;
801
809
irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
802
810
803
811
irq = &phys_enc->irq[INTR_IDX_RDPTR];
804
812
irq->name = "pp_rd_ptr";
805
-
irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
806
813
irq->intr_idx = INTR_IDX_RDPTR;
807
814
irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
808
815
809
816
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
810
817
irq->name = "underrun";
811
-
irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
812
818
irq->intr_idx = INTR_IDX_UNDERRUN;
813
819
irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
814
820
+20
-34
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+20
-34
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
-
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
+
/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
3
3
*/
4
4
5
5
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
···
9
9
#include "dpu_core_irq.h"
10
10
#include "dpu_formats.h"
11
11
#include "dpu_trace.h"
12
+
#include "disp/msm_disp_snapshot.h"
12
13
13
14
#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
14
15
(e) && (e)->parent ? \
···
285
284
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
286
285
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
287
286
if (phys_enc->hw_pp->merge_3d)
288
-
intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
287
+
intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
289
288
290
289
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
291
290
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
···
299
298
true,
300
299
phys_enc->hw_pp->idx);
301
300
302
-
if (phys_enc->hw_pp->merge_3d) {
303
-
struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
304
-
305
-
merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
306
-
}
301
+
if (phys_enc->hw_pp->merge_3d)
302
+
phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
307
303
308
304
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
309
305
···
361
363
return phys_enc->split_role != ENC_ROLE_SOLO;
362
364
}
363
365
364
-
static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
365
-
struct dpu_encoder_phys *phys_enc)
366
-
{
367
-
struct dpu_encoder_irq *irq;
368
-
369
-
/*
370
-
* Initialize irq->hw_idx only when irq is not registered.
371
-
* Prevent invalidating irq->irq_idx as modeset may be
372
-
* called many times during dfps.
373
-
*/
374
-
375
-
irq = &phys_enc->irq[INTR_IDX_VSYNC];
376
-
if (irq->irq_idx < 0)
377
-
irq->hw_idx = phys_enc->intf_idx;
378
-
379
-
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
380
-
if (irq->irq_idx < 0)
381
-
irq->hw_idx = phys_enc->intf_idx;
382
-
}
383
-
384
366
static void dpu_encoder_phys_vid_mode_set(
385
367
struct dpu_encoder_phys *phys_enc,
386
368
struct drm_display_mode *mode,
387
369
struct drm_display_mode *adj_mode)
388
370
{
371
+
struct dpu_encoder_irq *irq;
372
+
389
373
if (adj_mode) {
390
374
phys_enc->cached_mode = *adj_mode;
391
375
drm_mode_debug_printmodeline(adj_mode);
392
376
DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
393
377
}
394
378
395
-
_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
379
+
irq = &phys_enc->irq[INTR_IDX_VSYNC];
380
+
irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync;
381
+
382
+
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
383
+
irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
396
384
}
397
385
398
386
static int dpu_encoder_phys_vid_control_vblank_irq(
···
400
416
goto end;
401
417
}
402
418
403
-
DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
419
+
DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
404
420
atomic_read(&phys_enc->vblank_refcount));
405
421
406
422
if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
···
445
461
446
462
ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
447
463
if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
448
-
ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id);
464
+
ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
449
465
450
466
skip_flush:
451
467
DPU_DEBUG_VIDENC(phys_enc,
452
468
"update pending flush ctl %d intf %d\n",
453
469
ctl->idx - CTL_0, phys_enc->hw_intf->idx);
454
470
471
+
atomic_set(&phys_enc->underrun_cnt, 0);
455
472
456
473
/* ctl_flush & timing engine enable will be triggered by framework */
457
474
if (phys_enc->enable_state == DPU_ENC_DISABLED)
···
522
537
{
523
538
struct dpu_hw_ctl *ctl;
524
539
int rc;
540
+
struct drm_encoder *drm_enc;
541
+
542
+
drm_enc = phys_enc->parent;
525
543
526
544
ctl = phys_enc->hw_ctl;
527
545
if (!ctl->ops.wait_reset_status)
···
538
550
if (rc) {
539
551
DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
540
552
ctl->idx, rc);
553
+
msm_disp_snapshot_state(drm_enc->dev);
541
554
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
542
555
}
543
556
}
···
625
636
626
637
if (enable) {
627
638
ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
628
-
if (ret)
639
+
if (WARN_ON(ret))
629
640
return;
630
641
631
642
dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
···
727
738
irq = &phys_enc->irq[i];
728
739
INIT_LIST_HEAD(&irq->cb.list);
729
740
irq->irq_idx = -EINVAL;
730
-
irq->hw_idx = -EINVAL;
731
741
irq->cb.arg = phys_enc;
732
742
}
733
743
734
744
irq = &phys_enc->irq[INTR_IDX_VSYNC];
735
745
irq->name = "vsync_irq";
736
-
irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
737
746
irq->intr_idx = INTR_IDX_VSYNC;
738
747
irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
739
748
740
749
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
741
750
irq->name = "underrun";
742
-
irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
743
751
irq->intr_idx = INTR_IDX_UNDERRUN;
744
752
irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
745
753
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+3
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
···
992
992
* Currently only support exactly zero or one modifier.
993
993
* All planes use the same modifier.
994
994
*/
995
-
DPU_DEBUG("plane format modifier 0x%llX\n", modifier);
995
+
DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
996
996
997
997
switch (modifier) {
998
998
case 0:
···
1002
1002
case DRM_FORMAT_MOD_QCOM_COMPRESSED:
1003
1003
map = dpu_format_map_ubwc;
1004
1004
map_size = ARRAY_SIZE(dpu_format_map_ubwc);
1005
-
DPU_DEBUG("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
1005
+
DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
1006
1006
(char *)&format);
1007
1007
break;
1008
1008
default:
···
1021
1021
DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
1022
1022
(char *)&format, modifier);
1023
1023
else
1024
-
DPU_DEBUG("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
1024
+
DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
1025
1025
(char *)&format, modifier,
1026
1026
DPU_FORMAT_IS_UBWC(fmt),
1027
1027
DPU_FORMAT_IS_YUV(fmt));
-139
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
-139
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
-
*/
4
-
5
-
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
6
-
7
-
#include <linux/mutex.h>
8
-
#include <linux/errno.h>
9
-
#include <linux/slab.h>
10
-
11
-
#include "dpu_hw_mdss.h"
12
-
#include "dpu_hw_blk.h"
13
-
14
-
/* Serialization lock for dpu_hw_blk_list */
15
-
static DEFINE_MUTEX(dpu_hw_blk_lock);
16
-
17
-
/* List of all hw block objects */
18
-
static LIST_HEAD(dpu_hw_blk_list);
19
-
20
-
/**
21
-
* dpu_hw_blk_init - initialize hw block object
22
-
* @hw_blk: pointer to hw block object
23
-
* @type: hw block type - enum dpu_hw_blk_type
24
-
* @id: instance id of the hw block
25
-
* @ops: Pointer to block operations
26
-
*/
27
-
void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
28
-
struct dpu_hw_blk_ops *ops)
29
-
{
30
-
INIT_LIST_HEAD(&hw_blk->list);
31
-
hw_blk->type = type;
32
-
hw_blk->id = id;
33
-
atomic_set(&hw_blk->refcount, 0);
34
-
35
-
if (ops)
36
-
hw_blk->ops = *ops;
37
-
38
-
mutex_lock(&dpu_hw_blk_lock);
39
-
list_add(&hw_blk->list, &dpu_hw_blk_list);
40
-
mutex_unlock(&dpu_hw_blk_lock);
41
-
}
42
-
43
-
/**
44
-
* dpu_hw_blk_destroy - destroy hw block object.
45
-
* @hw_blk: pointer to hw block object
46
-
* return: none
47
-
*/
48
-
void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk)
49
-
{
50
-
if (!hw_blk) {
51
-
pr_err("invalid parameters\n");
52
-
return;
53
-
}
54
-
55
-
if (atomic_read(&hw_blk->refcount))
56
-
pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type,
57
-
hw_blk->id);
58
-
59
-
mutex_lock(&dpu_hw_blk_lock);
60
-
list_del(&hw_blk->list);
61
-
mutex_unlock(&dpu_hw_blk_lock);
62
-
}
63
-
64
-
/**
65
-
* dpu_hw_blk_get - get hw_blk from free pool
66
-
* @hw_blk: if specified, increment reference count only
67
-
* @type: if hw_blk is not specified, allocate the next available of this type
68
-
* @id: if specified (>= 0), allocate the given instance of the above type
69
-
* return: pointer to hw block object
70
-
*/
71
-
struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id)
72
-
{
73
-
struct dpu_hw_blk *curr;
74
-
int rc, refcount;
75
-
76
-
if (!hw_blk) {
77
-
mutex_lock(&dpu_hw_blk_lock);
78
-
list_for_each_entry(curr, &dpu_hw_blk_list, list) {
79
-
if ((curr->type != type) ||
80
-
(id >= 0 && curr->id != id) ||
81
-
(id < 0 &&
82
-
atomic_read(&curr->refcount)))
83
-
continue;
84
-
85
-
hw_blk = curr;
86
-
break;
87
-
}
88
-
mutex_unlock(&dpu_hw_blk_lock);
89
-
}
90
-
91
-
if (!hw_blk) {
92
-
pr_debug("no hw_blk:%d\n", type);
93
-
return NULL;
94
-
}
95
-
96
-
refcount = atomic_inc_return(&hw_blk->refcount);
97
-
98
-
if (refcount == 1 && hw_blk->ops.start) {
99
-
rc = hw_blk->ops.start(hw_blk);
100
-
if (rc) {
101
-
pr_err("failed to start hw_blk:%d rc:%d\n", type, rc);
102
-
goto error_start;
103
-
}
104
-
}
105
-
106
-
pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type,
107
-
hw_blk->id, refcount);
108
-
return hw_blk;
109
-
110
-
error_start:
111
-
dpu_hw_blk_put(hw_blk);
112
-
return ERR_PTR(rc);
113
-
}
114
-
115
-
/**
116
-
* dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero
117
-
* @hw_blk: hw block to be freed
118
-
*/
119
-
void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk)
120
-
{
121
-
if (!hw_blk) {
122
-
pr_err("invalid parameters\n");
123
-
return;
124
-
}
125
-
126
-
pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id,
127
-
atomic_read(&hw_blk->refcount));
128
-
129
-
if (!atomic_read(&hw_blk->refcount)) {
130
-
pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id);
131
-
return;
132
-
}
133
-
134
-
if (atomic_dec_return(&hw_blk->refcount))
135
-
return;
136
-
137
-
if (hw_blk->ops.stop)
138
-
hw_blk->ops.stop(hw_blk);
139
-
}
+1
-21
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
+1
-21
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
···
7
7
8
8
#include <linux/types.h>
9
9
#include <linux/list.h>
10
-
#include <linux/atomic.h>
11
10
12
11
struct dpu_hw_blk;
13
12
14
-
/**
15
-
* struct dpu_hw_blk_ops - common hardware block operations
16
-
* @start: start operation on first get
17
-
* @stop: stop operation on last put
18
-
*/
19
-
struct dpu_hw_blk_ops {
20
-
int (*start)(struct dpu_hw_blk *);
21
-
void (*stop)(struct dpu_hw_blk *);
22
-
};
23
13
24
14
/**
25
15
* struct dpu_hw_blk - definition of hardware block object
···
19
29
* @refcount: reference/usage count
20
30
*/
21
31
struct dpu_hw_blk {
22
-
struct list_head list;
23
-
u32 type;
24
-
int id;
25
-
atomic_t refcount;
26
-
struct dpu_hw_blk_ops ops;
32
+
/* opaque */
27
33
};
28
34
29
-
void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
30
-
struct dpu_hw_blk_ops *ops);
31
-
void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk);
32
-
33
-
struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id);
34
-
void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk);
35
35
#endif /*_DPU_HW_BLK_H */
+136
-66
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+136
-66
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
···
7
7
#include <linux/of_address.h>
8
8
#include <linux/platform_device.h>
9
9
#include "dpu_hw_mdss.h"
10
+
#include "dpu_hw_interrupts.h"
10
11
#include "dpu_hw_catalog.h"
11
12
#include "dpu_kms.h"
12
13
···
57
56
58
57
#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
59
58
60
-
#define INTR_SC7180_MASK \
61
-
(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
62
-
BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
63
-
BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\
64
-
BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
65
-
BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
59
+
#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
60
+
BIT(MDP_SSPP_TOP0_INTR2) | \
61
+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
62
+
BIT(MDP_INTF0_INTR) | \
63
+
BIT(MDP_INTF1_INTR) | \
64
+
BIT(MDP_INTF2_INTR) | \
65
+
BIT(MDP_INTF3_INTR) | \
66
+
BIT(MDP_INTF4_INTR) | \
67
+
BIT(MDP_AD4_0_INTR) | \
68
+
BIT(MDP_AD4_1_INTR))
69
+
70
+
#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
71
+
BIT(MDP_SSPP_TOP0_INTR2) | \
72
+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
73
+
BIT(MDP_INTF0_INTR) | \
74
+
BIT(MDP_INTF1_INTR))
75
+
76
+
#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
77
+
BIT(MDP_SSPP_TOP0_INTR2) | \
78
+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
79
+
BIT(MDP_INTF0_7xxx_INTR) | \
80
+
BIT(MDP_INTF1_7xxx_INTR) | \
81
+
BIT(MDP_INTF5_7xxx_INTR))
82
+
83
+
#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
84
+
BIT(MDP_SSPP_TOP0_INTR2) | \
85
+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
86
+
BIT(MDP_INTF0_INTR) | \
87
+
BIT(MDP_INTF1_INTR) | \
88
+
BIT(MDP_INTF2_INTR) | \
89
+
BIT(MDP_INTF3_INTR) | \
90
+
BIT(MDP_INTF4_INTR))
91
+
66
92
67
93
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
68
94
#define DEFAULT_DPU_LINE_WIDTH 2048
···
343
315
{
344
316
.name = "ctl_0", .id = CTL_0,
345
317
.base = 0x1000, .len = 0xE4,
346
-
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
318
+
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
319
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
347
320
},
348
321
{
349
322
.name = "ctl_1", .id = CTL_1,
350
323
.base = 0x1200, .len = 0xE4,
351
-
.features = BIT(DPU_CTL_SPLIT_DISPLAY)
324
+
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
325
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
352
326
},
353
327
{
354
328
.name = "ctl_2", .id = CTL_2,
355
329
.base = 0x1400, .len = 0xE4,
356
-
.features = 0
330
+
.features = 0,
331
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
357
332
},
358
333
{
359
334
.name = "ctl_3", .id = CTL_3,
360
335
.base = 0x1600, .len = 0xE4,
361
-
.features = 0
336
+
.features = 0,
337
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
362
338
},
363
339
{
364
340
.name = "ctl_4", .id = CTL_4,
365
341
.base = 0x1800, .len = 0xE4,
366
-
.features = 0
342
+
.features = 0,
343
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
367
344
},
368
345
};
369
346
···
376
343
{
377
344
.name = "ctl_0", .id = CTL_0,
378
345
.base = 0x1000, .len = 0xE4,
379
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
346
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
347
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
380
348
},
381
349
{
382
350
.name = "ctl_1", .id = CTL_1,
383
351
.base = 0x1200, .len = 0xE4,
384
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
352
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
353
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
385
354
},
386
355
{
387
356
.name = "ctl_2", .id = CTL_2,
388
357
.base = 0x1400, .len = 0xE4,
389
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
358
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
359
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
390
360
},
391
361
};
392
362
···
397
361
{
398
362
.name = "ctl_0", .id = CTL_0,
399
363
.base = 0x1000, .len = 0x1e0,
400
-
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
364
+
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
365
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
401
366
},
402
367
{
403
368
.name = "ctl_1", .id = CTL_1,
404
369
.base = 0x1200, .len = 0x1e0,
405
-
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
370
+
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
371
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
406
372
},
407
373
{
408
374
.name = "ctl_2", .id = CTL_2,
409
375
.base = 0x1400, .len = 0x1e0,
410
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
376
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
377
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
411
378
},
412
379
{
413
380
.name = "ctl_3", .id = CTL_3,
414
381
.base = 0x1600, .len = 0x1e0,
415
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
382
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
383
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
416
384
},
417
385
{
418
386
.name = "ctl_4", .id = CTL_4,
419
387
.base = 0x1800, .len = 0x1e0,
420
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
388
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
389
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
421
390
},
422
391
{
423
392
.name = "ctl_5", .id = CTL_5,
424
393
.base = 0x1a00, .len = 0x1e0,
425
-
.features = BIT(DPU_CTL_ACTIVE_CFG)
394
+
.features = BIT(DPU_CTL_ACTIVE_CFG),
395
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
426
396
},
427
397
};
428
398
···
436
394
{
437
395
.name = "ctl_0", .id = CTL_0,
438
396
.base = 0x15000, .len = 0x1E8,
439
-
.features = CTL_SC7280_MASK
397
+
.features = CTL_SC7280_MASK,
398
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
440
399
},
441
400
{
442
401
.name = "ctl_1", .id = CTL_1,
443
402
.base = 0x16000, .len = 0x1E8,
444
-
.features = CTL_SC7280_MASK
403
+
.features = CTL_SC7280_MASK,
404
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
445
405
},
446
406
{
447
407
.name = "ctl_2", .id = CTL_2,
448
408
.base = 0x17000, .len = 0x1E8,
449
-
.features = CTL_SC7280_MASK
409
+
.features = CTL_SC7280_MASK,
410
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
450
411
},
451
412
{
452
413
.name = "ctl_3", .id = CTL_3,
453
414
.base = 0x18000, .len = 0x1E8,
454
-
.features = CTL_SC7280_MASK
415
+
.features = CTL_SC7280_MASK,
416
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
455
417
},
456
418
};
457
419
···
736
690
.len = 0x20, .version = 0x20000},
737
691
};
738
692
739
-
#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
693
+
#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
740
694
{\
741
695
.name = _name, .id = _id, \
742
696
.base = _base, .len = 0xd4, \
743
697
.features = PINGPONG_SDM845_SPLIT_MASK, \
744
698
.merge_3d = _merge_3d, \
745
-
.sblk = &_sblk \
699
+
.sblk = &_sblk, \
700
+
.intr_done = _done, \
701
+
.intr_rdptr = _rdptr, \
746
702
}
747
-
#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
703
+
#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
748
704
{\
749
705
.name = _name, .id = _id, \
750
706
.base = _base, .len = 0xd4, \
751
707
.features = PINGPONG_SDM845_MASK, \
752
708
.merge_3d = _merge_3d, \
753
-
.sblk = &_sblk \
709
+
.sblk = &_sblk, \
710
+
.intr_done = _done, \
711
+
.intr_rdptr = _rdptr, \
754
712
}
755
713
756
714
static const struct dpu_pingpong_cfg sdm845_pp[] = {
757
-
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
758
-
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
759
-
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
760
-
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
715
+
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
716
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
717
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
718
+
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
719
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
720
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
721
+
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
722
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
723
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
724
+
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
725
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
726
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
761
727
};
762
728
763
729
static struct dpu_pingpong_cfg sc7180_pp[] = {
764
-
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
765
-
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
730
+
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
731
+
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
766
732
};
767
733
768
734
static const struct dpu_pingpong_cfg sm8150_pp[] = {
769
-
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te),
770
-
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te),
771
-
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk),
772
-
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk),
773
-
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk),
774
-
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk),
735
+
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
736
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
737
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
738
+
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
739
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
740
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
741
+
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
742
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
743
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
744
+
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
745
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
746
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
747
+
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
748
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
749
+
-1),
750
+
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
751
+
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
752
+
-1),
775
753
};
776
754
777
755
/*************************************************************
···
816
746
};
817
747
818
748
static const struct dpu_pingpong_cfg sc7280_pp[] = {
819
-
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
820
-
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
821
-
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
822
-
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
749
+
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
750
+
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
751
+
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
752
+
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
823
753
};
824
754
/*************************************************************
825
755
* INTF sub blocks config
826
756
*************************************************************/
827
-
#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \
757
+
#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
828
758
{\
829
759
.name = _name, .id = _id, \
830
760
.base = _base, .len = 0x280, \
831
761
.features = _features, \
832
762
.type = _type, \
833
763
.controller_id = _ctrl_id, \
834
-
.prog_fetch_lines_worst_case = _progfetch \
764
+
.prog_fetch_lines_worst_case = _progfetch, \
765
+
.intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
766
+
.intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
835
767
}
836
768
837
769
static const struct dpu_intf_cfg sdm845_intf[] = {
838
-
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK),
839
-
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK),
840
-
INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK),
841
-
INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK),
770
+
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
771
+
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
772
+
INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
773
+
INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
842
774
};
843
775
844
776
static const struct dpu_intf_cfg sc7180_intf[] = {
845
-
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
846
-
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
777
+
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
778
+
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
847
779
};
848
780
849
781
static const struct dpu_intf_cfg sm8150_intf[] = {
850
-
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
851
-
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
852
-
INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK),
853
-
INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK),
782
+
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
783
+
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
784
+
INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
785
+
INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
854
786
};
855
787
856
788
static const struct dpu_intf_cfg sc7280_intf[] = {
857
-
INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK),
858
-
INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK),
859
-
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
789
+
INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
790
+
INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
791
+
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
860
792
};
861
793
862
794
/*************************************************************
···
1132
1060
.reg_dma_count = 1,
1133
1061
.dma_cfg = sdm845_regdma,
1134
1062
.perf = sdm845_perf_data,
1135
-
.mdss_irqs = 0x3ff,
1063
+
.mdss_irqs = IRQ_SDM845_MASK,
1136
1064
};
1137
1065
}
1138
1066
···
1163
1091
.reg_dma_count = 1,
1164
1092
.dma_cfg = sdm845_regdma,
1165
1093
.perf = sc7180_perf_data,
1166
-
.mdss_irqs = 0x3f,
1167
-
.obsolete_irq = INTR_SC7180_MASK,
1094
+
.mdss_irqs = IRQ_SC7180_MASK,
1168
1095
};
1169
1096
}
1170
1097
···
1196
1125
.reg_dma_count = 1,
1197
1126
.dma_cfg = sm8150_regdma,
1198
1127
.perf = sm8150_perf_data,
1199
-
.mdss_irqs = 0x3ff,
1128
+
.mdss_irqs = IRQ_SDM845_MASK,
1200
1129
};
1201
1130
}
1202
1131
···
1229
1158
.reg_dma_count = 1,
1230
1159
.dma_cfg = sm8250_regdma,
1231
1160
.perf = sm8250_perf_data,
1232
-
.mdss_irqs = 0xff,
1161
+
.mdss_irqs = IRQ_SM8250_MASK,
1233
1162
};
1234
1163
}
1235
1164
···
1252
1181
.vbif_count = ARRAY_SIZE(sdm845_vbif),
1253
1182
.vbif = sdm845_vbif,
1254
1183
.perf = sc7280_perf_data,
1255
-
.mdss_irqs = 0x1c07,
1256
-
.obsolete_irq = INTR_SC7180_MASK,
1184
+
.mdss_irqs = IRQ_SC7280_MASK,
1257
1185
};
1258
1186
}
1259
1187
+12
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+12
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
+
/* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
3
3
*/
4
4
5
5
#ifndef _DPU_HW_CATALOG_H
···
464
464
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
465
465
};
466
466
467
-
/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
467
+
/* struct dpu_ctl_cfg : MDP CTL instance info
468
468
* @id: index identifying this block
469
469
* @base: register base offset to mdss
470
470
* @features bit mask identifying sub-blocks/features
471
+
* @intr_start: interrupt index for CTL_START
471
472
*/
472
473
struct dpu_ctl_cfg {
473
474
DPU_HW_BLK_INFO;
475
+
s32 intr_start;
474
476
};
475
477
476
478
/**
···
528
526
* @id enum identifying this block
529
527
* @base register offset of this block
530
528
* @features bit mask identifying sub-blocks/features
529
+
* @intr_done: index for PINGPONG done interrupt
530
+
* @intr_rdptr: index for PINGPONG readpointer done interrupt
531
531
* @sblk sub-blocks information
532
532
*/
533
533
struct dpu_pingpong_cfg {
534
534
DPU_HW_BLK_INFO;
535
535
u32 merge_3d;
536
+
s32 intr_done;
537
+
s32 intr_rdptr;
536
538
const struct dpu_pingpong_sub_blks *sblk;
537
539
};
538
540
···
561
555
* @type: Interface type(DSI, DP, HDMI)
562
556
* @controller_id: Controller Instance ID in case of multiple of intf type
563
557
* @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
558
+
* @intr_underrun: index for INTF underrun interrupt
559
+
* @intr_vsync: index for INTF VSYNC interrupt
564
560
*/
565
561
struct dpu_intf_cfg {
566
562
DPU_HW_BLK_INFO;
567
563
u32 type; /* interface type*/
568
564
u32 controller_id;
569
565
u32 prog_fetch_lines_worst_case;
566
+
s32 intr_underrun;
567
+
s32 intr_vsync;
570
568
};
571
569
572
570
/**
···
733
723
* @cursor_formats Supported formats for cursor pipe
734
724
* @vig_formats Supported formats for vig pipe
735
725
* @mdss_irqs: Bitmap with the irqs supported by the target
736
-
* @obsolete_irq: Irq types that are obsolete for a particular target
737
726
*/
738
727
struct dpu_mdss_cfg {
739
728
u32 hwversion;
···
779
770
const struct dpu_format_extended *vig_formats;
780
771
781
772
unsigned long mdss_irqs;
782
-
unsigned long obsolete_irq;
783
773
};
784
774
785
775
struct dpu_mdss_hw_cfg_handler {
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
···
589
589
ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active;
590
590
};
591
591
592
-
static struct dpu_hw_blk_ops dpu_hw_ops;
593
-
594
592
struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
595
593
void __iomem *addr,
596
594
const struct dpu_mdss_cfg *m)
···
613
615
c->mixer_count = m->mixer_count;
614
616
c->mixer_hw_caps = m->mixer;
615
617
616
-
dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops);
617
-
618
618
return c;
619
619
}
620
620
621
621
void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)
622
622
{
623
-
if (ctx)
624
-
dpu_hw_blk_destroy(&ctx->base);
625
623
kfree(ctx);
626
624
}
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
···
85
85
return ERR_PTR(-EINVAL);
86
86
}
87
87
88
-
static struct dpu_hw_blk_ops dpu_hw_ops;
89
-
90
88
struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
91
89
void __iomem *addr,
92
90
const struct dpu_mdss_cfg *m)
···
110
112
c->cap = cfg;
111
113
_setup_dspp_ops(c, c->cap->features);
112
114
113
-
dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops);
114
-
115
115
return c;
116
116
}
117
117
118
118
void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
119
119
{
120
-
if (dspp)
121
-
dpu_hw_blk_destroy(&dspp->base);
122
-
123
120
kfree(dspp);
124
121
}
125
122
+109
-1397
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+109
-1397
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
···
30
30
#define MDP_INTF_5_OFF_REV_7xxx 0x39000
31
31
32
32
/**
33
-
* WB interrupt status bit definitions
34
-
*/
35
-
#define DPU_INTR_WB_0_DONE BIT(0)
36
-
#define DPU_INTR_WB_1_DONE BIT(1)
37
-
#define DPU_INTR_WB_2_DONE BIT(4)
38
-
39
-
/**
40
-
* WDOG timer interrupt status bit definitions
41
-
*/
42
-
#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
43
-
#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
44
-
#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
45
-
#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
46
-
#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
47
-
48
-
/**
49
-
* Pingpong interrupt status bit definitions
50
-
*/
51
-
#define DPU_INTR_PING_PONG_0_DONE BIT(8)
52
-
#define DPU_INTR_PING_PONG_1_DONE BIT(9)
53
-
#define DPU_INTR_PING_PONG_2_DONE BIT(10)
54
-
#define DPU_INTR_PING_PONG_3_DONE BIT(11)
55
-
#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
56
-
#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
57
-
#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
58
-
#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
59
-
#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
60
-
#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
61
-
#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
62
-
#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
63
-
#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
64
-
#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
65
-
#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
66
-
#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
67
-
68
-
/**
69
-
* Interface interrupt status bit definitions
70
-
*/
71
-
#define DPU_INTR_INTF_0_UNDERRUN BIT(24)
72
-
#define DPU_INTR_INTF_1_UNDERRUN BIT(26)
73
-
#define DPU_INTR_INTF_2_UNDERRUN BIT(28)
74
-
#define DPU_INTR_INTF_3_UNDERRUN BIT(30)
75
-
#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
76
-
#define DPU_INTR_INTF_0_VSYNC BIT(25)
77
-
#define DPU_INTR_INTF_1_VSYNC BIT(27)
78
-
#define DPU_INTR_INTF_2_VSYNC BIT(29)
79
-
#define DPU_INTR_INTF_3_VSYNC BIT(31)
80
-
#define DPU_INTR_INTF_5_VSYNC BIT(23)
81
-
82
-
/**
83
-
* Pingpong Secondary interrupt status bit definitions
84
-
*/
85
-
#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
86
-
#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4)
87
-
#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8)
88
-
#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
89
-
#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
90
-
91
-
/**
92
-
* Pingpong TEAR detection interrupt status bit definitions
93
-
*/
94
-
#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
95
-
#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
96
-
#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
97
-
#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
98
-
99
-
/**
100
-
* Pingpong TE detection interrupt status bit definitions
101
-
*/
102
-
#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24)
103
-
#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25)
104
-
#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26)
105
-
#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27)
106
-
107
-
/**
108
-
* Ctl start interrupt status bit definitions
109
-
*/
110
-
#define DPU_INTR_CTL_0_START BIT(9)
111
-
#define DPU_INTR_CTL_1_START BIT(10)
112
-
#define DPU_INTR_CTL_2_START BIT(11)
113
-
#define DPU_INTR_CTL_3_START BIT(12)
114
-
#define DPU_INTR_CTL_4_START BIT(13)
115
-
116
-
/**
117
-
* Concurrent WB overflow interrupt status bit definitions
118
-
*/
119
-
#define DPU_INTR_CWB_2_OVERFLOW BIT(14)
120
-
#define DPU_INTR_CWB_3_OVERFLOW BIT(15)
121
-
122
-
/**
123
-
* Histogram VIG done interrupt status bit definitions
124
-
*/
125
-
#define DPU_INTR_HIST_VIG_0_DONE BIT(0)
126
-
#define DPU_INTR_HIST_VIG_1_DONE BIT(4)
127
-
#define DPU_INTR_HIST_VIG_2_DONE BIT(8)
128
-
#define DPU_INTR_HIST_VIG_3_DONE BIT(10)
129
-
130
-
/**
131
-
* Histogram VIG reset Sequence done interrupt status bit definitions
132
-
*/
133
-
#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1)
134
-
#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5)
135
-
#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9)
136
-
#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11)
137
-
138
-
/**
139
-
* Histogram DSPP done interrupt status bit definitions
140
-
*/
141
-
#define DPU_INTR_HIST_DSPP_0_DONE BIT(12)
142
-
#define DPU_INTR_HIST_DSPP_1_DONE BIT(16)
143
-
#define DPU_INTR_HIST_DSPP_2_DONE BIT(20)
144
-
#define DPU_INTR_HIST_DSPP_3_DONE BIT(22)
145
-
146
-
/**
147
-
* Histogram DSPP reset Sequence done interrupt status bit definitions
148
-
*/
149
-
#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13)
150
-
#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17)
151
-
#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21)
152
-
#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23)
153
-
154
-
/**
155
-
* INTF interrupt status bit definitions
156
-
*/
157
-
#define DPU_INTR_VIDEO_INTO_STATIC BIT(0)
158
-
#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1)
159
-
#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2)
160
-
#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3)
161
-
#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4)
162
-
#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5)
163
-
#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6)
164
-
#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7)
165
-
#define DPU_INTR_PROG_LINE BIT(8)
166
-
167
-
/**
168
-
* AD4 interrupt status bit definitions
169
-
*/
170
-
#define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
171
-
/**
172
33
* struct dpu_intr_reg - array of DPU register sets
173
34
* @clr_off: offset to CLEAR reg
174
35
* @en_off: offset to ENABLE reg
···
41
180
u32 status_off;
42
181
};
43
182
44
-
/**
45
-
* struct dpu_irq_type - maps each irq with i/f
46
-
* @intr_type: type of interrupt listed in dpu_intr_type
47
-
* @instance_idx: instance index of the associated HW block in DPU
48
-
* @irq_mask: corresponding bit in the interrupt status reg
49
-
* @reg_idx: which reg set to use
50
-
*/
51
-
struct dpu_irq_type {
52
-
u32 intr_type;
53
-
u32 instance_idx;
54
-
u32 irq_mask;
55
-
u32 reg_idx;
56
-
};
57
-
58
183
/*
59
184
* struct dpu_intr_reg - List of DPU interrupt registers
185
+
*
186
+
* When making changes be sure to sync with dpu_hw_intr_reg
60
187
*/
61
188
static const struct dpu_intr_reg dpu_intr_set[] = {
62
189
{
···
114
265
},
115
266
};
116
267
117
-
/*
118
-
* struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this
119
-
* table that have a matching interface type and
120
-
* instance index.
121
-
*/
122
-
static const struct dpu_irq_type dpu_irq_map[] = {
123
-
/* BEGIN MAP_RANGE: 0-31, INTR */
124
-
/* irq_idx: 0-3 */
125
-
{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0},
126
-
{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0},
127
-
{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0},
128
-
{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0},
129
-
/* irq_idx: 4-7 */
130
-
{ DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0},
131
-
{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0},
132
-
{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0},
133
-
{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0},
134
-
/* irq_idx: 8-11 */
135
-
{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0,
136
-
DPU_INTR_PING_PONG_0_DONE, 0},
137
-
{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1,
138
-
DPU_INTR_PING_PONG_1_DONE, 0},
139
-
{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2,
140
-
DPU_INTR_PING_PONG_2_DONE, 0},
141
-
{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3,
142
-
DPU_INTR_PING_PONG_3_DONE, 0},
143
-
/* irq_idx: 12-15 */
144
-
{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0,
145
-
DPU_INTR_PING_PONG_0_RD_PTR, 0},
146
-
{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1,
147
-
DPU_INTR_PING_PONG_1_RD_PTR, 0},
148
-
{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2,
149
-
DPU_INTR_PING_PONG_2_RD_PTR, 0},
150
-
{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3,
151
-
DPU_INTR_PING_PONG_3_RD_PTR, 0},
152
-
/* irq_idx: 16-19 */
153
-
{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0,
154
-
DPU_INTR_PING_PONG_0_WR_PTR, 0},
155
-
{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1,
156
-
DPU_INTR_PING_PONG_1_WR_PTR, 0},
157
-
{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2,
158
-
DPU_INTR_PING_PONG_2_WR_PTR, 0},
159
-
{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3,
160
-
DPU_INTR_PING_PONG_3_WR_PTR, 0},
161
-
/* irq_idx: 20-23 */
162
-
{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0,
163
-
DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0},
164
-
{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1,
165
-
DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0},
166
-
{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2,
167
-
DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0},
168
-
{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3,
169
-
DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0},
170
-
/* irq_idx: 24-27 */
171
-
{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0},
172
-
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0},
173
-
{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0},
174
-
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0},
175
-
/* irq_idx: 28-31 */
176
-
{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0},
177
-
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
178
-
{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
179
-
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
180
-
/* irq_idx:32-33 */
181
-
{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
182
-
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
183
-
/* irq_idx:34-63 */
184
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
185
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
186
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
187
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
188
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
189
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
190
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
191
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
192
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
193
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
194
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
195
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
196
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
197
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
198
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
199
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
200
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
201
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
202
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
203
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
204
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
205
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
206
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
207
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
208
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
209
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
210
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
211
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
212
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
213
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
214
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
215
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
216
-
/* BEGIN MAP_RANGE: 64-95, INTR2 */
217
-
/* irq_idx: 64-67 */
218
-
{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
219
-
DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
220
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
221
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
222
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
223
-
/* irq_idx: 68-71 */
224
-
{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
225
-
DPU_INTR_PING_PONG_S0_WR_PTR, 1},
226
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
227
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
228
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
229
-
/* irq_idx: 72 */
230
-
{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
231
-
DPU_INTR_PING_PONG_S0_RD_PTR, 1},
232
-
/* irq_idx: 73-77 */
233
-
{ DPU_IRQ_TYPE_CTL_START, CTL_0,
234
-
DPU_INTR_CTL_0_START, 1},
235
-
{ DPU_IRQ_TYPE_CTL_START, CTL_1,
236
-
DPU_INTR_CTL_1_START, 1},
237
-
{ DPU_IRQ_TYPE_CTL_START, CTL_2,
238
-
DPU_INTR_CTL_2_START, 1},
239
-
{ DPU_IRQ_TYPE_CTL_START, CTL_3,
240
-
DPU_INTR_CTL_3_START, 1},
241
-
{ DPU_IRQ_TYPE_CTL_START, CTL_4,
242
-
DPU_INTR_CTL_4_START, 1},
243
-
/* irq_idx: 78-79 */
244
-
{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1},
245
-
{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1},
246
-
/* irq_idx: 80-83 */
247
-
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
248
-
DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1},
249
-
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
250
-
DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1},
251
-
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
252
-
DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1},
253
-
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
254
-
DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1},
255
-
/* irq_idx: 84-87 */
256
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
257
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
258
-
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
259
-
DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
260
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
261
-
/* irq_idx: 88-91 */
262
-
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
263
-
DPU_INTR_PING_PONG_0_TE_DETECTED, 1},
264
-
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
265
-
DPU_INTR_PING_PONG_1_TE_DETECTED, 1},
266
-
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
267
-
DPU_INTR_PING_PONG_2_TE_DETECTED, 1},
268
-
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
269
-
DPU_INTR_PING_PONG_3_TE_DETECTED, 1},
270
-
/* irq_idx: 92-95 */
271
-
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
272
-
DPU_INTR_PING_PONG_S0_TE_DETECTED, 1},
273
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
274
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
275
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
276
-
/* irq_idx: 96-127 */
277
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
278
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
279
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
280
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
281
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
282
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
283
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
284
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
285
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
286
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
287
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
288
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
289
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
290
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
291
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
292
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
293
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
294
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
295
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
296
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
297
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
298
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
299
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
300
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
301
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
302
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
303
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
304
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
305
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
306
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
307
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
308
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
309
-
/* BEGIN MAP_RANGE: 128-159 HIST */
310
-
/* irq_idx: 128-131 */
311
-
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
312
-
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
313
-
DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
314
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
315
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
316
-
/* irq_idx: 132-135 */
317
-
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
318
-
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
319
-
DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
320
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
321
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
322
-
/* irq_idx: 136-139 */
323
-
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
324
-
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
325
-
DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
326
-
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2},
327
-
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
328
-
DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
329
-
/* irq_idx: 140-143 */
330
-
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2},
331
-
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
332
-
DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
333
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
334
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
335
-
/* irq_idx: 144-147 */
336
-
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2},
337
-
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
338
-
DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
339
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
340
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
341
-
/* irq_idx: 148-151 */
342
-
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2},
343
-
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
344
-
DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
345
-
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2},
346
-
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
347
-
DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
348
-
/* irq_idx: 152-155 */
349
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
350
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
351
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
352
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
353
-
/* irq_idx: 156-159 */
354
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
355
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
356
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
357
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
358
-
/* irq_idx: 160-191 */
359
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
360
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
361
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
362
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
363
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
364
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
365
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
366
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
367
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
368
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
369
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
370
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
371
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
372
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
373
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
374
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
375
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
376
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
377
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
378
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
379
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
380
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
381
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
382
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
383
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
384
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
385
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
386
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
387
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
388
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
389
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
390
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
391
-
/* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */
392
-
/* irq_idx: 192-195 */
393
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
394
-
DPU_INTR_VIDEO_INTO_STATIC, 3},
395
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
396
-
DPU_INTR_VIDEO_OUTOF_STATIC, 3},
397
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
398
-
DPU_INTR_DSICMD_0_INTO_STATIC, 3},
399
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
400
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 3},
401
-
/* irq_idx: 196-199 */
402
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
403
-
DPU_INTR_DSICMD_1_INTO_STATIC, 3},
404
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
405
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 3},
406
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
407
-
DPU_INTR_DSICMD_2_INTO_STATIC, 3},
408
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
409
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 3},
410
-
/* irq_idx: 200-203 */
411
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3},
412
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
413
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
414
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
415
-
/* irq_idx: 204-207 */
416
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
417
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
418
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
419
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
420
-
/* irq_idx: 208-211 */
421
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
422
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
423
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
424
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
425
-
/* irq_idx: 212-215 */
426
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
427
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
428
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
429
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
430
-
/* irq_idx: 216-219 */
431
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
432
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
433
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
434
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
435
-
/* irq_idx: 220-223 */
436
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
437
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
438
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
439
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
440
-
/* irq_idx: 224-255 */
441
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
442
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
443
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
444
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
445
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
446
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
447
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
448
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
449
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
450
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
451
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
452
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
453
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
454
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
455
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
456
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
457
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
458
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
459
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
460
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
461
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
462
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
463
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
464
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
465
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
466
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
467
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
468
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
469
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
470
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
471
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
472
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
473
-
/* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */
474
-
/* irq_idx: 256-259 */
475
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
476
-
DPU_INTR_VIDEO_INTO_STATIC, 4},
477
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
478
-
DPU_INTR_VIDEO_OUTOF_STATIC, 4},
479
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
480
-
DPU_INTR_DSICMD_0_INTO_STATIC, 4},
481
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
482
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 4},
483
-
/* irq_idx: 260-263 */
484
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
485
-
DPU_INTR_DSICMD_1_INTO_STATIC, 4},
486
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
487
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 4},
488
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
489
-
DPU_INTR_DSICMD_2_INTO_STATIC, 4},
490
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
491
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 4},
492
-
/* irq_idx: 264-267 */
493
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4},
494
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
495
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
496
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
497
-
/* irq_idx: 268-271 */
498
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
499
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
500
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
501
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
502
-
/* irq_idx: 272-275 */
503
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
504
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
505
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
506
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
507
-
/* irq_idx: 276-279 */
508
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
509
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
510
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
511
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
512
-
/* irq_idx: 280-283 */
513
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
514
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
515
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
516
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
517
-
/* irq_idx: 284-287 */
518
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
519
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
520
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
521
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
522
-
/* irq_idx: 288-319 */
523
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
524
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
525
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
526
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
527
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
528
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
529
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
530
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
531
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
532
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
533
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
534
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
535
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
536
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
537
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
538
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
539
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
540
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
541
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
542
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
543
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
544
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
545
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
546
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
547
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
548
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
549
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
550
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
551
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
552
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
553
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
554
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
555
-
/* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */
556
-
/* irq_idx: 320-323 */
557
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
558
-
DPU_INTR_VIDEO_INTO_STATIC, 5},
559
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
560
-
DPU_INTR_VIDEO_OUTOF_STATIC, 5},
561
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2,
562
-
DPU_INTR_DSICMD_0_INTO_STATIC, 5},
563
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
564
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 5},
565
-
/* irq_idx: 324-327 */
566
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
567
-
DPU_INTR_DSICMD_1_INTO_STATIC, 5},
568
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
569
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 5},
570
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2,
571
-
DPU_INTR_DSICMD_2_INTO_STATIC, 5},
572
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
573
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 5},
574
-
/* irq_idx: 328-331 */
575
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5},
576
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
577
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
578
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
579
-
/* irq_idx: 332-335 */
580
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
581
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
582
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
583
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
584
-
/* irq_idx: 336-339 */
585
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
586
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
587
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
588
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
589
-
/* irq_idx: 340-343 */
590
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
591
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
592
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
593
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
594
-
/* irq_idx: 344-347 */
595
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
596
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
597
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
598
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
599
-
/* irq_idx: 348-351 */
600
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
601
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
602
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
603
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
604
-
/* irq_idx: 352-383 */
605
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
606
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
607
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
608
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
609
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
610
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
611
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
612
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
613
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
614
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
615
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
616
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
617
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
618
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
619
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
620
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
621
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
622
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
623
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
624
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
625
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
626
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
627
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
628
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
629
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
630
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
631
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
632
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
633
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
634
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
635
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
636
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
637
-
/* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */
638
-
/* irq_idx: 384-387 */
639
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
640
-
DPU_INTR_VIDEO_INTO_STATIC, 6},
641
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
642
-
DPU_INTR_VIDEO_OUTOF_STATIC, 6},
643
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3,
644
-
DPU_INTR_DSICMD_0_INTO_STATIC, 6},
645
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
646
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 6},
647
-
/* irq_idx: 388-391 */
648
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
649
-
DPU_INTR_DSICMD_1_INTO_STATIC, 6},
650
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
651
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 6},
652
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3,
653
-
DPU_INTR_DSICMD_2_INTO_STATIC, 6},
654
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
655
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 6},
656
-
/* irq_idx: 392-395 */
657
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6},
658
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
659
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
660
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
661
-
/* irq_idx: 396-399 */
662
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
663
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
664
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
665
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
666
-
/* irq_idx: 400-403 */
667
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
668
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
669
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
670
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
671
-
/* irq_idx: 404-407 */
672
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
673
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
674
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
675
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
676
-
/* irq_idx: 408-411 */
677
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
678
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
679
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
680
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
681
-
/* irq_idx: 412-415 */
682
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
683
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
684
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
685
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
686
-
/* irq_idx: 416-447*/
687
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
688
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
689
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
690
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
691
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
692
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
693
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
694
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
695
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
696
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
697
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
698
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
699
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
700
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
701
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
702
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
703
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
704
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
705
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
706
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
707
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
708
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
709
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
710
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
711
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
712
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
713
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
714
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
715
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
716
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
717
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
718
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
719
-
/* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */
720
-
/* irq_idx: 448-451 */
721
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
722
-
DPU_INTR_VIDEO_INTO_STATIC, 7},
723
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
724
-
DPU_INTR_VIDEO_OUTOF_STATIC, 7},
725
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4,
726
-
DPU_INTR_DSICMD_0_INTO_STATIC, 7},
727
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
728
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 7},
729
-
/* irq_idx: 452-455 */
730
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
731
-
DPU_INTR_DSICMD_1_INTO_STATIC, 7},
732
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
733
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 7},
734
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4,
735
-
DPU_INTR_DSICMD_2_INTO_STATIC, 7},
736
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
737
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 7},
738
-
/* irq_idx: 456-459 */
739
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7},
740
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
741
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
742
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
743
-
/* irq_idx: 460-463 */
744
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
745
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
746
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
747
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
748
-
/* irq_idx: 464-467 */
749
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
750
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
751
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
752
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
753
-
/* irq_idx: 468-471 */
754
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
755
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
756
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
757
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
758
-
/* irq_idx: 472-475 */
759
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
760
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
761
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
762
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
763
-
/* irq_idx: 476-479 */
764
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
765
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
766
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
767
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
768
-
/* irq_idx: 480-511 */
769
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
770
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
771
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
772
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
773
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
774
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
775
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
776
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
777
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
778
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
779
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
780
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
781
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
782
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
783
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
784
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
785
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
786
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
787
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
788
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
789
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
790
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
791
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
792
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
793
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
794
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
795
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
796
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
797
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
798
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
799
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
800
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
801
-
/* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */
802
-
/* irq_idx: 512-515 */
803
-
{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8},
804
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
805
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
806
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
807
-
/* irq_idx: 516-519 */
808
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
809
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
810
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
811
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
812
-
/* irq_idx: 520-523 */
813
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
814
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
815
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
816
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
817
-
/* irq_idx: 524-527 */
818
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
819
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
820
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
821
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
822
-
/* irq_idx: 528-531 */
823
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
824
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
825
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
826
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
827
-
/* irq_idx: 532-535 */
828
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
829
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
830
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
831
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
832
-
/* irq_idx: 536-539 */
833
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
834
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
835
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
836
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
837
-
/* irq_idx: 540-543 */
838
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
839
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
840
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
841
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
842
-
/* irq_idx: 544-575*/
843
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
844
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
845
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
846
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
847
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
848
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
849
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
850
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
851
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
852
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
853
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
854
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
855
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
856
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
857
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
858
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
859
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
860
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
861
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
862
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
863
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
864
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
865
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
866
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
867
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
868
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
869
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
870
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
871
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
872
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
873
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
874
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
875
-
/* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */
876
-
/* irq_idx: 576-579 */
877
-
{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9},
878
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
879
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
880
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
881
-
/* irq_idx: 580-583 */
882
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
883
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
884
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
885
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
886
-
/* irq_idx: 584-587 */
887
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
888
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
889
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
890
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
891
-
/* irq_idx: 588-591 */
892
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
893
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
894
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
895
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
896
-
/* irq_idx: 592-595 */
897
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
898
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
899
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
900
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
901
-
/* irq_idx: 596-599 */
902
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
903
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
904
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
905
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
906
-
/* irq_idx: 600-603 */
907
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
908
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
909
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
910
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
911
-
/* irq_idx: 604-607 */
912
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
913
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
914
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
915
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
916
-
/* irq_idx: 608-639 */
917
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
918
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
919
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
920
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
921
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
922
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
923
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
924
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
925
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
926
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
927
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
928
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
929
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
930
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
931
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
932
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
933
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
934
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
935
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
936
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
937
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
938
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
939
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
940
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
941
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
942
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
943
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
944
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
945
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
946
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
947
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
948
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
949
-
/* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */
950
-
/* irq_idx: 640-643 */
951
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
952
-
DPU_INTR_VIDEO_INTO_STATIC, 10},
953
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
954
-
DPU_INTR_VIDEO_OUTOF_STATIC, 10},
955
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
956
-
DPU_INTR_DSICMD_0_INTO_STATIC, 10},
957
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
958
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 10},
959
-
/* irq_idx: 644-647 */
960
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
961
-
DPU_INTR_DSICMD_1_INTO_STATIC, 10},
962
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
963
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 10},
964
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
965
-
DPU_INTR_DSICMD_2_INTO_STATIC, 10},
966
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
967
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 10},
968
-
/* irq_idx: 648-651 */
969
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10},
970
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
971
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
972
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
973
-
/* irq_idx: 652-655 */
974
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
975
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
976
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
977
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
978
-
/* irq_idx: 656-659 */
979
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
980
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
981
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
982
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
983
-
/* irq_idx: 660-663 */
984
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
985
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
986
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
987
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
988
-
/* irq_idx: 664-667 */
989
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
990
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
991
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
992
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
993
-
/* irq_idx: 668-671 */
994
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
995
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
996
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
997
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
998
-
/* irq_idx: 672-703 */
999
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1000
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1001
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1002
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1003
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1004
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1005
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1006
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1007
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1008
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1009
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1010
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1011
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1012
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1013
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1014
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1015
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1016
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1017
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1018
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1019
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1020
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1021
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1022
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1023
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1024
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1025
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1026
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1027
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1028
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1029
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1030
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
1031
-
/* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */
1032
-
/* irq_idx: 704-707 */
1033
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
1034
-
DPU_INTR_VIDEO_INTO_STATIC, 11},
1035
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
1036
-
DPU_INTR_VIDEO_OUTOF_STATIC, 11},
1037
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
1038
-
DPU_INTR_DSICMD_0_INTO_STATIC, 11},
1039
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
1040
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 11},
1041
-
/* irq_idx: 708-711 */
1042
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
1043
-
DPU_INTR_DSICMD_1_INTO_STATIC, 11},
1044
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
1045
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 11},
1046
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
1047
-
DPU_INTR_DSICMD_2_INTO_STATIC, 11},
1048
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
1049
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 11},
1050
-
/* irq_idx: 712-715 */
1051
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11},
1052
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1053
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1054
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1055
-
/* irq_idx: 716-719 */
1056
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1057
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1058
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1059
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1060
-
/* irq_idx: 720-723 */
1061
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1062
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1063
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1064
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1065
-
/* irq_idx: 724-727 */
1066
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1067
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1068
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1069
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1070
-
/* irq_idx: 728-731 */
1071
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1072
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1073
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1074
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1075
-
/* irq_idx: 732-735 */
1076
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1077
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1078
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1079
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1080
-
/* irq_idx: 736-767 */
1081
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1082
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1083
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1084
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1085
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1086
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1087
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1088
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1089
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1090
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1091
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1092
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1093
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1094
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1095
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1096
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1097
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1098
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1099
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1100
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1101
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1102
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1103
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1104
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1105
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1106
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1107
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1108
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1109
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1110
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1111
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1112
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
1113
-
/* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */
1114
-
/* irq_idx: 768-771 */
1115
-
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5,
1116
-
DPU_INTR_VIDEO_INTO_STATIC, 12},
1117
-
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5,
1118
-
DPU_INTR_VIDEO_OUTOF_STATIC, 12},
1119
-
{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5,
1120
-
DPU_INTR_DSICMD_0_INTO_STATIC, 12},
1121
-
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5,
1122
-
DPU_INTR_DSICMD_0_OUTOF_STATIC, 12},
1123
-
/* irq_idx: 772-775 */
1124
-
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5,
1125
-
DPU_INTR_DSICMD_1_INTO_STATIC, 12},
1126
-
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5,
1127
-
DPU_INTR_DSICMD_1_OUTOF_STATIC, 12},
1128
-
{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5,
1129
-
DPU_INTR_DSICMD_2_INTO_STATIC, 12},
1130
-
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5,
1131
-
DPU_INTR_DSICMD_2_OUTOF_STATIC, 12},
1132
-
/* irq_idx: 776-779 */
1133
-
{ DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12},
1134
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1135
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1136
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1137
-
/* irq_idx: 780-783 */
1138
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1139
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1140
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1141
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1142
-
/* irq_idx: 784-787 */
1143
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1144
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1145
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1146
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1147
-
/* irq_idx: 788-791 */
1148
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1149
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1150
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1151
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1152
-
/* irq_idx: 792-795 */
1153
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1154
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1155
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1156
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1157
-
/* irq_idx: 796-799 */
1158
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1159
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1160
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1161
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1162
-
/* irq_idx: 800-831 */
1163
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1164
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1165
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1166
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1167
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1168
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1169
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1170
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1171
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1172
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1173
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1174
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1175
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1176
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1177
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1178
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1179
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1180
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1181
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1182
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1183
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1184
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1185
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1186
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1187
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1188
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1189
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1190
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1191
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1192
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1193
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1194
-
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
1195
-
};
268
+
#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
269
+
#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
1196
270
1197
-
static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
1198
-
enum dpu_intr_type intr_type, u32 instance_idx)
271
+
static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
272
+
int irq_idx)
1199
273
{
1200
-
int i;
274
+
int reg_idx;
1201
275
1202
-
for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
1203
-
if (intr_type == dpu_irq_map[i].intr_type &&
1204
-
instance_idx == dpu_irq_map[i].instance_idx &&
1205
-
!(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
1206
-
return i;
1207
-
}
276
+
if (!intr)
277
+
return;
1208
278
1209
-
pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",
1210
-
intr_type, instance_idx);
1211
-
return -EINVAL;
279
+
reg_idx = DPU_IRQ_REG(irq_idx);
280
+
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));
281
+
282
+
/* ensure register writes go through */
283
+
wmb();
1212
284
}
1213
285
1214
286
static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
···
138
1368
{
139
1369
int reg_idx;
140
1370
int irq_idx;
141
-
int start_idx;
142
-
int end_idx;
143
1371
u32 irq_status;
1372
+
u32 enable_mask;
1373
+
int bit;
144
1374
unsigned long irq_flags;
145
1375
146
1376
if (!intr)
···
153
1383
*/
154
1384
spin_lock_irqsave(&intr->irq_lock, irq_flags);
155
1385
for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
156
-
irq_status = intr->save_irq_status[reg_idx];
1386
+
if (!test_bit(reg_idx, &intr->irq_mask))
1387
+
continue;
157
1388
158
-
/*
159
-
* Each Interrupt register has a range of 64 indexes, and
160
-
* that is static for dpu_irq_map.
161
-
*/
162
-
start_idx = reg_idx * 64;
163
-
end_idx = start_idx + 64;
1389
+
/* Read interrupt status */
1390
+
irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
164
1391
165
-
if (!test_bit(reg_idx, &intr->irq_mask) ||
166
-
start_idx >= ARRAY_SIZE(dpu_irq_map))
1392
+
/* Read enable mask */
1393
+
enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
1394
+
1395
+
/* and clear the interrupt */
1396
+
if (irq_status)
1397
+
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
1398
+
irq_status);
1399
+
1400
+
/* Finally update IRQ status based on enable mask */
1401
+
irq_status &= enable_mask;
1402
+
1403
+
if (!irq_status)
167
1404
continue;
168
1405
169
1406
/*
170
-
* Search through matching intr status from irq map.
171
-
* start_idx and end_idx defined the search range in
172
-
* the dpu_irq_map.
1407
+
* Search through matching intr status.
173
1408
*/
174
-
for (irq_idx = start_idx;
175
-
(irq_idx < end_idx) && irq_status;
176
-
irq_idx++)
177
-
if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
178
-
(dpu_irq_map[irq_idx].reg_idx == reg_idx) &&
179
-
!(intr->obsolete_irq &
180
-
BIT(dpu_irq_map[irq_idx].intr_type))) {
181
-
/*
182
-
* Once a match on irq mask, perform a callback
183
-
* to the given cbfunc. cbfunc will take care
184
-
* the interrupt status clearing. If cbfunc is
185
-
* not provided, then the interrupt clearing
186
-
* is here.
187
-
*/
188
-
if (cbfunc)
189
-
cbfunc(arg, irq_idx);
190
-
else
191
-
intr->ops.clear_intr_status_nolock(
192
-
intr, irq_idx);
1409
+
while ((bit = ffs(irq_status)) != 0) {
1410
+
irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
1411
+
/*
1412
+
* Once a match on irq mask, perform a callback
1413
+
* to the given cbfunc. cbfunc will take care
1414
+
* the interrupt status clearing. If cbfunc is
1415
+
* not provided, then the interrupt clearing
1416
+
* is here.
1417
+
*/
1418
+
if (cbfunc)
1419
+
cbfunc(arg, irq_idx);
193
1420
194
-
/*
195
-
* When callback finish, clear the irq_status
196
-
* with the matching mask. Once irq_status
197
-
* is all cleared, the search can be stopped.
198
-
*/
199
-
irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
200
-
}
1421
+
dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
1422
+
1423
+
/*
1424
+
* When callback finish, clear the irq_status
1425
+
* with the matching mask. Once irq_status
1426
+
* is all cleared, the search can be stopped.
1427
+
*/
1428
+
irq_status &= ~BIT(bit - 1);
1429
+
}
201
1430
}
1431
+
1432
+
/* ensure register writes go through */
1433
+
wmb();
1434
+
202
1435
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
203
1436
}
204
1437
205
-
static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
1438
+
static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
206
1439
{
207
1440
int reg_idx;
208
-
unsigned long irq_flags;
209
1441
const struct dpu_intr_reg *reg;
210
-
const struct dpu_irq_type *irq;
211
1442
const char *dbgstr = NULL;
212
1443
uint32_t cache_irq_mask;
213
1444
214
1445
if (!intr)
215
1446
return -EINVAL;
216
1447
217
-
if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
1448
+
if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
218
1449
pr_err("invalid IRQ index: [%d]\n", irq_idx);
219
1450
return -EINVAL;
220
1451
}
221
1452
222
-
irq = &dpu_irq_map[irq_idx];
223
-
reg_idx = irq->reg_idx;
1453
+
/*
1454
+
* The cache_irq_mask and hardware RMW operations needs to be done
1455
+
* under irq_lock and it's the caller's responsibility to ensure that's
1456
+
* held.
1457
+
*/
1458
+
assert_spin_locked(&intr->irq_lock);
1459
+
1460
+
reg_idx = DPU_IRQ_REG(irq_idx);
224
1461
reg = &dpu_intr_set[reg_idx];
225
1462
226
-
spin_lock_irqsave(&intr->irq_lock, irq_flags);
227
1463
cache_irq_mask = intr->cache_irq_mask[reg_idx];
228
-
if (cache_irq_mask & irq->irq_mask) {
1464
+
if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
229
1465
dbgstr = "DPU IRQ already set:";
230
1466
} else {
231
1467
dbgstr = "DPU IRQ enabled:";
232
1468
233
-
cache_irq_mask |= irq->irq_mask;
1469
+
cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
234
1470
/* Cleaning any pending interrupt */
235
-
DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
1471
+
DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
236
1472
/* Enabling interrupts with the new mask */
237
1473
DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
238
1474
···
247
1471
248
1472
intr->cache_irq_mask[reg_idx] = cache_irq_mask;
249
1473
}
250
-
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
251
1474
252
-
pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
253
-
irq->irq_mask, cache_irq_mask);
1475
+
pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
1476
+
DPU_IRQ_MASK(irq_idx), cache_irq_mask);
254
1477
255
1478
return 0;
256
1479
}
257
1480
258
-
static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
1481
+
static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
259
1482
{
260
1483
int reg_idx;
261
1484
const struct dpu_intr_reg *reg;
262
-
const struct dpu_irq_type *irq;
263
1485
const char *dbgstr = NULL;
264
1486
uint32_t cache_irq_mask;
265
1487
266
1488
if (!intr)
267
1489
return -EINVAL;
268
1490
269
-
if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
1491
+
if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
270
1492
pr_err("invalid IRQ index: [%d]\n", irq_idx);
271
1493
return -EINVAL;
272
1494
}
273
1495
274
-
irq = &dpu_irq_map[irq_idx];
275
-
reg_idx = irq->reg_idx;
1496
+
/*
1497
+
* The cache_irq_mask and hardware RMW operations needs to be done
1498
+
* under irq_lock and it's the caller's responsibility to ensure that's
1499
+
* held.
1500
+
*/
1501
+
assert_spin_locked(&intr->irq_lock);
1502
+
1503
+
reg_idx = DPU_IRQ_REG(irq_idx);
276
1504
reg = &dpu_intr_set[reg_idx];
277
1505
278
1506
cache_irq_mask = intr->cache_irq_mask[reg_idx];
279
-
if ((cache_irq_mask & irq->irq_mask) == 0) {
1507
+
if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
280
1508
dbgstr = "DPU IRQ is already cleared:";
281
1509
} else {
282
1510
dbgstr = "DPU IRQ mask disable:";
283
1511
284
-
cache_irq_mask &= ~irq->irq_mask;
1512
+
cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
285
1513
/* Disable interrupts based on the new mask */
286
1514
DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
287
1515
/* Cleaning any pending interrupt */
288
-
DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
1516
+
DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
289
1517
290
1518
/* ensure register write goes through */
291
1519
wmb();
···
297
1517
intr->cache_irq_mask[reg_idx] = cache_irq_mask;
298
1518
}
299
1519
300
-
pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
301
-
irq->irq_mask, cache_irq_mask);
302
-
303
-
return 0;
304
-
}
305
-
306
-
static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
307
-
{
308
-
unsigned long irq_flags;
309
-
310
-
if (!intr)
311
-
return -EINVAL;
312
-
313
-
if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
314
-
pr_err("invalid IRQ index: [%d]\n", irq_idx);
315
-
return -EINVAL;
316
-
}
317
-
318
-
spin_lock_irqsave(&intr->irq_lock, irq_flags);
319
-
dpu_hw_intr_disable_irq_nolock(intr, irq_idx);
320
-
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1520
+
pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
1521
+
DPU_IRQ_MASK(irq_idx), cache_irq_mask);
321
1522
322
1523
return 0;
323
1524
}
···
341
1580
return 0;
342
1581
}
343
1582
344
-
static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
345
-
{
346
-
int i;
347
-
u32 enable_mask;
348
-
unsigned long irq_flags;
349
-
350
-
if (!intr)
351
-
return;
352
-
353
-
spin_lock_irqsave(&intr->irq_lock, irq_flags);
354
-
for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
355
-
if (!test_bit(i, &intr->irq_mask))
356
-
continue;
357
-
358
-
/* Read interrupt status */
359
-
intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
360
-
dpu_intr_set[i].status_off);
361
-
362
-
/* Read enable mask */
363
-
enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
364
-
365
-
/* and clear the interrupt */
366
-
if (intr->save_irq_status[i])
367
-
DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off,
368
-
intr->save_irq_status[i]);
369
-
370
-
/* Finally update IRQ status based on enable mask */
371
-
intr->save_irq_status[i] &= enable_mask;
372
-
}
373
-
374
-
/* ensure register writes go through */
375
-
wmb();
376
-
377
-
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
378
-
}
379
-
380
-
static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
381
-
int irq_idx)
382
-
{
383
-
int reg_idx;
384
-
385
-
if (!intr)
386
-
return;
387
-
388
-
reg_idx = dpu_irq_map[irq_idx].reg_idx;
389
-
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
390
-
dpu_irq_map[irq_idx].irq_mask);
391
-
392
-
/* ensure register writes go through */
393
-
wmb();
394
-
}
395
-
396
1583
static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
397
1584
int irq_idx, bool clear)
398
1585
{
···
351
1642
if (!intr)
352
1643
return 0;
353
1644
354
-
if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) {
1645
+
if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
355
1646
pr_err("invalid IRQ index: [%d]\n", irq_idx);
356
1647
return 0;
357
1648
}
358
1649
359
1650
spin_lock_irqsave(&intr->irq_lock, irq_flags);
360
1651
361
-
reg_idx = dpu_irq_map[irq_idx].reg_idx;
1652
+
reg_idx = DPU_IRQ_REG(irq_idx);
362
1653
intr_status = DPU_REG_READ(&intr->hw,
363
1654
dpu_intr_set[reg_idx].status_off) &
364
-
dpu_irq_map[irq_idx].irq_mask;
1655
+
DPU_IRQ_MASK(irq_idx);
365
1656
if (intr_status && clear)
366
1657
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
367
1658
intr_status);
···
374
1665
return intr_status;
375
1666
}
376
1667
1668
+
static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr)
1669
+
{
1670
+
unsigned long irq_flags;
1671
+
1672
+
spin_lock_irqsave(&intr->irq_lock, irq_flags);
1673
+
1674
+
return irq_flags;
1675
+
}
1676
+
1677
+
static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags)
1678
+
{
1679
+
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
1680
+
}
1681
+
377
1682
static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
378
1683
{
379
-
ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
380
-
ops->enable_irq = dpu_hw_intr_enable_irq;
381
-
ops->disable_irq = dpu_hw_intr_disable_irq;
1684
+
ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked;
1685
+
ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked;
382
1686
ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
383
1687
ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
384
1688
ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
385
-
ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
386
-
ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
387
1689
ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
1690
+
ops->lock = dpu_hw_intr_lock;
1691
+
ops->unlock = dpu_hw_intr_unlock;
388
1692
}
389
1693
390
1694
static void __intr_offset(struct dpu_mdss_cfg *m,
···
423
1701
__intr_offset(m, addr, &intr->hw);
424
1702
__setup_intr_ops(&intr->ops);
425
1703
426
-
intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);
1704
+
intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
427
1705
428
1706
intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
429
1707
GFP_KERNEL);
···
432
1710
return ERR_PTR(-ENOMEM);
433
1711
}
434
1712
435
-
intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
436
-
GFP_KERNEL);
437
-
if (intr->save_irq_status == NULL) {
438
-
kfree(intr->cache_irq_mask);
439
-
kfree(intr);
440
-
return ERR_PTR(-ENOMEM);
441
-
}
442
-
443
1713
intr->irq_mask = m->mdss_irqs;
444
-
intr->obsolete_irq = m->obsolete_irq;
445
1714
446
1715
spin_lock_init(&intr->irq_lock);
447
1716
···
443
1730
{
444
1731
if (intr) {
445
1732
kfree(intr->cache_irq_mask);
446
-
kfree(intr->save_irq_status);
447
1733
kfree(intr);
448
1734
}
449
1735
}
+38
-94
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+38
-94
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
···
12
12
#include "dpu_hw_util.h"
13
13
#include "dpu_hw_mdss.h"
14
14
15
-
/**
16
-
* dpu_intr_type - HW Interrupt Type
17
-
* @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done
18
-
* @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done
19
-
* @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done
20
-
* @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer
21
-
* @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer
22
-
* @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh
23
-
* @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check
24
-
* @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection
25
-
* @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun
26
-
* @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC
27
-
* @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow
28
-
* @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done
29
-
* @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset
30
-
* @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done
31
-
* @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset
32
-
* @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer
33
-
* @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static
34
-
* @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static
35
-
* @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static
36
-
* @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static
37
-
* @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static
38
-
* @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static
39
-
* @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static
40
-
* @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static
41
-
* @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt
42
-
* @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight
43
-
* @DPU_IRQ_TYPE_CTL_START: Control start
44
-
* @DPU_IRQ_TYPE_RESERVED: Reserved for expansion
45
-
*/
46
-
enum dpu_intr_type {
47
-
DPU_IRQ_TYPE_WB_ROT_COMP,
48
-
DPU_IRQ_TYPE_WB_WFD_COMP,
49
-
DPU_IRQ_TYPE_PING_PONG_COMP,
50
-
DPU_IRQ_TYPE_PING_PONG_RD_PTR,
51
-
DPU_IRQ_TYPE_PING_PONG_WR_PTR,
52
-
DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
53
-
DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
54
-
DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
55
-
DPU_IRQ_TYPE_INTF_UNDER_RUN,
56
-
DPU_IRQ_TYPE_INTF_VSYNC,
57
-
DPU_IRQ_TYPE_CWB_OVERFLOW,
58
-
DPU_IRQ_TYPE_HIST_VIG_DONE,
59
-
DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
60
-
DPU_IRQ_TYPE_HIST_DSPP_DONE,
61
-
DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
62
-
DPU_IRQ_TYPE_WD_TIMER,
63
-
DPU_IRQ_TYPE_SFI_VIDEO_IN,
64
-
DPU_IRQ_TYPE_SFI_VIDEO_OUT,
65
-
DPU_IRQ_TYPE_SFI_CMD_0_IN,
66
-
DPU_IRQ_TYPE_SFI_CMD_0_OUT,
67
-
DPU_IRQ_TYPE_SFI_CMD_1_IN,
68
-
DPU_IRQ_TYPE_SFI_CMD_1_OUT,
69
-
DPU_IRQ_TYPE_SFI_CMD_2_IN,
70
-
DPU_IRQ_TYPE_SFI_CMD_2_OUT,
71
-
DPU_IRQ_TYPE_PROG_LINE,
72
-
DPU_IRQ_TYPE_AD4_BL_DONE,
73
-
DPU_IRQ_TYPE_CTL_START,
74
-
DPU_IRQ_TYPE_RESERVED,
15
+
/* When making changes be sure to sync with dpu_intr_set */
16
+
enum dpu_hw_intr_reg {
17
+
MDP_SSPP_TOP0_INTR,
18
+
MDP_SSPP_TOP0_INTR2,
19
+
MDP_SSPP_TOP0_HIST_INTR,
20
+
MDP_INTF0_INTR,
21
+
MDP_INTF1_INTR,
22
+
MDP_INTF2_INTR,
23
+
MDP_INTF3_INTR,
24
+
MDP_INTF4_INTR,
25
+
MDP_AD4_0_INTR,
26
+
MDP_AD4_1_INTR,
27
+
MDP_INTF0_7xxx_INTR,
28
+
MDP_INTF1_7xxx_INTR,
29
+
MDP_INTF5_7xxx_INTR,
30
+
MDP_INTR_MAX,
75
31
};
32
+
33
+
#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
76
34
77
35
struct dpu_hw_intr;
78
36
···
38
80
* Interrupt operations.
39
81
*/
40
82
struct dpu_hw_intr_ops {
41
-
/**
42
-
* irq_idx_lookup - Lookup IRQ index on the HW interrupt type
43
-
* Used for all irq related ops
44
-
* @intr: HW interrupt handle
45
-
* @intr_type: Interrupt type defined in dpu_intr_type
46
-
* @instance_idx: HW interrupt block instance
47
-
* @return: irq_idx or -EINVAL for lookup fail
48
-
*/
49
-
int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
50
-
enum dpu_intr_type intr_type,
51
-
u32 instance_idx);
52
83
53
84
/**
54
85
* enable_irq - Enable IRQ based on lookup IRQ index
···
45
98
* @irq_idx: Lookup irq index return from irq_idx_lookup
46
99
* @return: 0 for success, otherwise failure
47
100
*/
48
-
int (*enable_irq)(
101
+
int (*enable_irq_locked)(
49
102
struct dpu_hw_intr *intr,
50
103
int irq_idx);
51
104
···
55
108
* @irq_idx: Lookup irq index return from irq_idx_lookup
56
109
* @return: 0 for success, otherwise failure
57
110
*/
58
-
int (*disable_irq)(
111
+
int (*disable_irq_locked)(
59
112
struct dpu_hw_intr *intr,
60
113
int irq_idx);
61
114
···
90
143
void *arg);
91
144
92
145
/**
93
-
* get_interrupt_statuses - Gets and store value from all interrupt
94
-
* status registers that are currently fired.
95
-
* @intr: HW interrupt handle
96
-
*/
97
-
void (*get_interrupt_statuses)(
98
-
struct dpu_hw_intr *intr);
99
-
100
-
/**
101
-
* clear_intr_status_nolock() - clears the HW interrupts without lock
102
-
* @intr: HW interrupt handle
103
-
* @irq_idx: Lookup irq index return from irq_idx_lookup
104
-
*/
105
-
void (*clear_intr_status_nolock)(
106
-
struct dpu_hw_intr *intr,
107
-
int irq_idx);
108
-
109
-
/**
110
146
* get_interrupt_status - Gets HW interrupt status, and clear if set,
111
147
* based on given lookup IRQ index.
112
148
* @intr: HW interrupt handle
···
100
170
struct dpu_hw_intr *intr,
101
171
int irq_idx,
102
172
bool clear);
173
+
174
+
/**
175
+
* lock - take the IRQ lock
176
+
* @intr: HW interrupt handle
177
+
* @return: irq_flags for the taken spinlock
178
+
*/
179
+
unsigned long (*lock)(
180
+
struct dpu_hw_intr *intr);
181
+
182
+
/**
183
+
* unlock - take the IRQ lock
184
+
* @intr: HW interrupt handle
185
+
* @irq_flags: the irq_flags returned from lock
186
+
*/
187
+
void (*unlock)(
188
+
struct dpu_hw_intr *intr, unsigned long irq_flags);
103
189
};
104
190
105
191
/**
···
124
178
* @ops: function pointer mapping for IRQ handling
125
179
* @cache_irq_mask: array of IRQ enable masks reg storage created during init
126
180
* @save_irq_status: array of IRQ status reg storage created during init
127
-
* @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
181
+
* @total_irqs: total number of irq_idx mapped in the hw_interrupts
128
182
* @irq_lock: spinlock for accessing IRQ resources
129
-
* @obsolete_irq: irq types that are obsolete for a particular target
130
183
*/
131
184
struct dpu_hw_intr {
132
185
struct dpu_hw_blk_reg_map hw;
133
186
struct dpu_hw_intr_ops ops;
134
187
u32 *cache_irq_mask;
135
188
u32 *save_irq_status;
136
-
u32 irq_idx_tbl_size;
189
+
u32 total_irqs;
137
190
spinlock_t irq_lock;
138
191
unsigned long irq_mask;
139
-
unsigned long obsolete_irq;
140
192
};
141
193
142
194
/**
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
···
299
299
ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
300
300
}
301
301
302
-
static struct dpu_hw_blk_ops dpu_hw_ops;
303
-
304
302
struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
305
303
void __iomem *addr,
306
304
const struct dpu_mdss_cfg *m)
···
325
327
c->mdss = m;
326
328
_setup_intf_ops(&c->ops, c->cap->features);
327
329
328
-
dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
329
-
330
330
return c;
331
331
}
332
332
333
333
void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
334
334
{
335
-
if (intf)
336
-
dpu_hw_blk_destroy(&intf->base);
337
335
kfree(intf);
338
336
}
339
337
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
···
160
160
ops->setup_border_color = dpu_hw_lm_setup_border_color;
161
161
}
162
162
163
-
static struct dpu_hw_blk_ops dpu_hw_ops;
164
-
165
163
struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
166
164
void __iomem *addr,
167
165
const struct dpu_mdss_cfg *m)
···
182
184
c->cap = cfg;
183
185
_setup_mixer_ops(m, &c->ops, c->cap->features);
184
186
185
-
dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops);
186
-
187
187
return c;
188
188
}
189
189
190
190
void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
191
191
{
192
-
if (lm)
193
-
dpu_hw_blk_destroy(&lm->base);
194
192
kfree(lm);
195
193
}
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
···
343
343
344
344
/** struct dpu_format - defines the format configuration which
345
345
* allows DPU HW to correctly fetch and decode the format
346
-
* @base: base msm_format struture containing fourcc code
346
+
* @base: base msm_format structure containing fourcc code
347
347
* @fetch_planes: how the color components are packed in pixel format
348
348
* @element: element color ordering
349
349
* @bits: element bit widths
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
···
58
58
c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
59
59
};
60
60
61
-
static struct dpu_hw_blk_ops dpu_hw_ops;
62
-
63
61
struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx,
64
62
void __iomem *addr,
65
63
const struct dpu_mdss_cfg *m)
···
79
81
c->caps = cfg;
80
82
_setup_merge_3d_ops(c, c->caps->features);
81
83
82
-
dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops);
83
-
84
84
return c;
85
85
}
86
86
87
87
void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw)
88
88
{
89
-
if (hw)
90
-
dpu_hw_blk_destroy(&hw->base);
91
89
kfree(hw);
92
90
}
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
···
261
261
c->ops.setup_dither = dpu_hw_pp_setup_dither;
262
262
};
263
263
264
-
static struct dpu_hw_blk_ops dpu_hw_ops;
265
-
266
264
struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
267
265
void __iomem *addr,
268
266
const struct dpu_mdss_cfg *m)
···
282
284
c->caps = cfg;
283
285
_setup_pingpong_ops(c, c->caps->features);
284
286
285
-
dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
286
-
287
287
return c;
288
288
}
289
289
290
290
void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
291
291
{
292
-
if (pp)
293
-
dpu_hw_blk_destroy(&pp->base);
294
292
kfree(pp);
295
293
}
+3
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+3
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
···
126
126
struct dpu_hw_dither_cfg *cfg);
127
127
};
128
128
129
+
struct dpu_hw_merge_3d;
130
+
129
131
struct dpu_hw_pingpong {
130
132
struct dpu_hw_blk base;
131
133
struct dpu_hw_blk_reg_map hw;
···
135
133
/* pingpong */
136
134
enum dpu_pingpong idx;
137
135
const struct dpu_pingpong_cfg *caps;
138
-
struct dpu_hw_blk *merge_3d;
136
+
struct dpu_hw_merge_3d *merge_3d;
139
137
140
138
/* ops */
141
139
struct dpu_hw_pingpong_ops ops;
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
···
706
706
return ERR_PTR(-ENOMEM);
707
707
}
708
708
709
-
static struct dpu_hw_blk_ops dpu_hw_ops;
710
-
711
709
struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
712
710
void __iomem *addr, struct dpu_mdss_cfg *catalog,
713
711
bool is_virtual_pipe)
···
733
735
hw_pipe->cap = cfg;
734
736
_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
735
737
736
-
dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops);
737
-
738
738
return hw_pipe;
739
739
}
740
740
741
741
void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
742
742
{
743
-
if (ctx)
744
-
dpu_hw_blk_destroy(&ctx->base);
745
743
kfree(ctx);
746
744
}
747
745
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
-6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
···
295
295
return ERR_PTR(-EINVAL);
296
296
}
297
297
298
-
static struct dpu_hw_blk_ops dpu_hw_ops;
299
-
300
298
struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
301
299
void __iomem *addr,
302
300
const struct dpu_mdss_cfg *m)
···
322
324
mdp->caps = cfg;
323
325
_setup_mdp_ops(&mdp->ops, mdp->caps->features);
324
326
325
-
dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops);
326
-
327
327
return mdp;
328
328
}
329
329
330
330
void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
331
331
{
332
-
if (mdp)
333
-
dpu_hw_blk_destroy(&mdp->base);
334
332
kfree(mdp);
335
333
}
336
334
+55
-15
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+55
-15
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
19
19
#include "msm_drv.h"
20
20
#include "msm_mmu.h"
21
21
#include "msm_gem.h"
22
+
#include "disp/msm_disp_snapshot.h"
22
23
23
24
#include "dpu_kms.h"
24
25
#include "dpu_core_irq.h"
···
799
798
dpu_core_irq_uninstall(dpu_kms);
800
799
}
801
800
801
+
static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
802
+
{
803
+
int i;
804
+
struct dpu_kms *dpu_kms;
805
+
struct dpu_mdss_cfg *cat;
806
+
struct dpu_hw_mdp *top;
807
+
808
+
dpu_kms = to_dpu_kms(kms);
809
+
810
+
cat = dpu_kms->catalog;
811
+
top = dpu_kms->hw_mdp;
812
+
813
+
pm_runtime_get_sync(&dpu_kms->pdev->dev);
814
+
815
+
/* dump CTL sub-blocks HW regs info */
816
+
for (i = 0; i < cat->ctl_count; i++)
817
+
msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
818
+
dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
819
+
820
+
/* dump DSPP sub-blocks HW regs info */
821
+
for (i = 0; i < cat->dspp_count; i++)
822
+
msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
823
+
dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
824
+
825
+
/* dump INTF sub-blocks HW regs info */
826
+
for (i = 0; i < cat->intf_count; i++)
827
+
msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
828
+
dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
829
+
830
+
/* dump PP sub-blocks HW regs info */
831
+
for (i = 0; i < cat->pingpong_count; i++)
832
+
msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
833
+
dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
834
+
835
+
/* dump SSPP sub-blocks HW regs info */
836
+
for (i = 0; i < cat->sspp_count; i++)
837
+
msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
838
+
dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
839
+
840
+
msm_disp_snapshot_add_block(disp_state, top->hw.length,
841
+
dpu_kms->mmio + top->hw.blk_off, "top");
842
+
843
+
pm_runtime_put_sync(&dpu_kms->pdev->dev);
844
+
}
845
+
802
846
static const struct msm_kms_funcs kms_funcs = {
803
847
.hw_init = dpu_kms_hw_init,
804
848
.irq_preinstall = dpu_irq_preinstall,
···
864
818
.round_pixclk = dpu_kms_round_pixclk,
865
819
.destroy = dpu_kms_destroy,
866
820
.set_encoder_mode = _dpu_kms_set_encoder_mode,
821
+
.snapshot = dpu_kms_mdp_snapshot,
867
822
#ifdef CONFIG_DEBUG_FS
868
823
.debugfs_init = dpu_kms_debugfs_init,
869
824
#endif
···
1136
1089
if (!dpu_kms)
1137
1090
return -ENOMEM;
1138
1091
1139
-
dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
1140
-
if (IS_ERR(dpu_kms->opp_table))
1141
-
return PTR_ERR(dpu_kms->opp_table);
1092
+
ret = devm_pm_opp_set_clkname(dev, "core");
1093
+
if (ret)
1094
+
return ret;
1142
1095
/* OPP table is optional */
1143
-
ret = dev_pm_opp_of_add_table(dev);
1096
+
ret = devm_pm_opp_of_add_table(dev);
1144
1097
if (ret && ret != -ENODEV) {
1145
1098
dev_err(dev, "invalid OPP table in device tree\n");
1146
-
goto put_clkname;
1099
+
return ret;
1147
1100
}
1148
1101
1149
1102
mp = &dpu_kms->mp;
1150
1103
ret = msm_dss_parse_clock(pdev, mp);
1151
1104
if (ret) {
1152
1105
DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1153
-
goto err;
1106
+
return ret;
1154
1107
}
1155
1108
1156
1109
platform_set_drvdata(pdev, dpu_kms);
···
1158
1111
ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1159
1112
if (ret) {
1160
1113
DPU_ERROR("failed to init kms, ret=%d\n", ret);
1161
-
goto err;
1114
+
return ret;
1162
1115
}
1163
1116
dpu_kms->dev = ddev;
1164
1117
dpu_kms->pdev = pdev;
···
1167
1120
dpu_kms->rpm_enabled = true;
1168
1121
1169
1122
priv->kms = &dpu_kms->base;
1170
-
return ret;
1171
-
err:
1172
-
dev_pm_opp_of_remove_table(dev);
1173
-
put_clkname:
1174
-
dev_pm_opp_put_clkname(dpu_kms->opp_table);
1123
+
1175
1124
return ret;
1176
1125
}
1177
1126
···
1183
1140
1184
1141
if (dpu_kms->rpm_enabled)
1185
1142
pm_runtime_disable(&pdev->dev);
1186
-
1187
-
dev_pm_opp_of_remove_table(dev);
1188
-
dev_pm_opp_put_clkname(dpu_kms->opp_table);
1189
1143
}
1190
1144
1191
1145
static const struct component_ops dpu_ops = {
+1
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+1
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
···
82
82
* struct dpu_irq: IRQ structure contains callback registration info
83
83
* @total_irq: total number of irq_idx obtained from HW interrupts mapping
84
84
* @irq_cb_tbl: array of IRQ callbacks setting
85
-
* @enable_counts array of IRQ enable counts
86
-
* @cb_lock: callback lock
87
85
* @debugfs_file: debugfs file for irq statistics
88
86
*/
89
87
struct dpu_irq {
90
88
u32 total_irqs;
91
89
struct list_head *irq_cb_tbl;
92
-
atomic_t *enable_counts;
93
90
atomic_t *irq_counts;
94
-
spinlock_t cb_lock;
95
91
};
96
92
97
93
struct dpu_kms {
···
125
129
126
130
struct platform_device *pdev;
127
131
bool rpm_enabled;
128
-
129
-
struct opp_table *opp_table;
130
132
131
133
struct dss_module_power mp;
132
134
···
252
258
253
259
/**
254
260
* dpu_kms_get_clk_rate() - get the clock rate
255
-
* @dpu_kms: poiner to dpu_kms structure
261
+
* @dpu_kms: pointer to dpu_kms structure
256
262
* @clock_name: clock name to get the rate
257
263
*
258
264
* Return: current clock rate
+5
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+5
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
···
225
225
struct msm_drm_private *priv = dev->dev_private;
226
226
struct dpu_mdss *dpu_mdss;
227
227
struct dss_module_power *mp;
228
-
int ret = 0;
228
+
int ret;
229
229
int irq;
230
230
231
231
dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
···
253
253
goto irq_domain_error;
254
254
255
255
irq = platform_get_irq(pdev, 0);
256
-
if (irq < 0)
256
+
if (irq < 0) {
257
+
ret = irq;
257
258
goto irq_error;
259
+
}
258
260
259
261
irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
260
262
dpu_mdss);
···
265
263
266
264
pm_runtime_enable(dev->dev);
267
265
268
-
return ret;
266
+
return 0;
269
267
270
268
irq_error:
271
269
_dpu_mdss_irq_domain_fini(dpu_mdss);
+10
-13
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+10
-13
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
···
25
25
#include "dpu_vbif.h"
26
26
#include "dpu_plane.h"
27
27
28
-
#define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
28
+
#define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
29
29
(pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
30
30
31
31
#define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
···
284
284
}
285
285
}
286
286
287
-
DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
288
-
plane->base.id, pdpu->pipe - SSPP_VIG0,
287
+
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
288
+
pdpu->pipe - SSPP_VIG0,
289
289
(char *)&fmt->base.pixel_format,
290
290
src_width, total_fl);
291
291
···
354
354
(fmt) ? fmt->base.pixel_format : 0,
355
355
pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
356
356
357
-
DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
358
-
plane->base.id,
357
+
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
359
358
pdpu->pipe - SSPP_VIG0,
360
359
fmt ? (char *)&fmt->base.pixel_format : NULL,
361
360
pdpu->is_rt_pipe, total_fl, qos_lut);
···
363
364
}
364
365
365
366
/**
366
-
* _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
367
+
* _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane
367
368
* @plane: Pointer to drm plane
368
369
* @fb: Pointer to framebuffer associated with the given plane
369
370
*/
···
406
407
pdpu->pipe_qos_cfg.danger_lut,
407
408
pdpu->pipe_qos_cfg.safe_lut);
408
409
409
-
DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
410
-
plane->base.id,
410
+
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
411
411
pdpu->pipe - SSPP_VIG0,
412
412
fmt ? (char *)&fmt->base.pixel_format : NULL,
413
413
fmt ? fmt->fetch_mode : -1,
···
449
451
pdpu->pipe_qos_cfg.danger_safe_en = false;
450
452
}
451
453
452
-
DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
453
-
plane->base.id,
454
+
DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
454
455
pdpu->pipe - SSPP_VIG0,
455
456
pdpu->pipe_qos_cfg.danger_safe_en,
456
457
pdpu->pipe_qos_cfg.vblank_en,
···
488
491
}
489
492
490
493
/**
491
-
* _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
494
+
* _dpu_plane_set_qos_remap - set vbif QoS for the given plane
492
495
* @plane: Pointer to drm plane
493
496
*/
494
497
static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
···
504
507
qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
505
508
qos_params.is_rt = pdpu->is_rt_pipe;
506
509
507
-
DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
508
-
plane->base.id, qos_params.num,
510
+
DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
511
+
qos_params.num,
509
512
qos_params.vbif_idx,
510
513
qos_params.xin_id, qos_params.is_rt,
511
514
qos_params.clk_ctrl);
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
···
162
162
goto fail;
163
163
}
164
164
if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
165
-
hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0];
165
+
hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]);
166
166
rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base;
167
167
}
168
168
···
428
428
features = ctl->caps->features;
429
429
has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
430
430
431
-
DPU_DEBUG("ctl %d caps 0x%lX\n", rm->ctl_blks[j]->id, features);
431
+
DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
432
432
433
433
if (needs_split_display != has_split_display)
434
434
continue;
+18
-45
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+18
-45
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
···
168
168
);
169
169
170
170
DECLARE_EVENT_CLASS(dpu_enc_irq_template,
171
-
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
171
+
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
172
172
int irq_idx),
173
-
TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx),
173
+
TP_ARGS(drm_id, intr_idx, irq_idx),
174
174
TP_STRUCT__entry(
175
175
__field( uint32_t, drm_id )
176
176
__field( enum dpu_intr_idx, intr_idx )
177
-
__field( int, hw_idx )
178
177
__field( int, irq_idx )
179
178
),
180
179
TP_fast_assign(
181
180
__entry->drm_id = drm_id;
182
181
__entry->intr_idx = intr_idx;
183
-
__entry->hw_idx = hw_idx;
184
182
__entry->irq_idx = irq_idx;
185
183
),
186
-
TP_printk("id=%u, intr=%d, hw=%d, irq=%d",
187
-
__entry->drm_id, __entry->intr_idx, __entry->hw_idx,
184
+
TP_printk("id=%u, intr=%d, irq=%d",
185
+
__entry->drm_id, __entry->intr_idx,
188
186
__entry->irq_idx)
189
187
);
190
188
DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
191
-
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
189
+
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
192
190
int irq_idx),
193
-
TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
191
+
TP_ARGS(drm_id, intr_idx, irq_idx)
194
192
);
195
193
DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
196
-
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
194
+
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
197
195
int irq_idx),
198
-
TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
196
+
TP_ARGS(drm_id, intr_idx, irq_idx)
199
197
);
200
198
201
199
TRACE_EVENT(dpu_enc_irq_wait_success,
202
-
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
200
+
TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
203
201
int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
204
-
TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
202
+
TP_ARGS(drm_id, intr_idx, irq_idx, pp_idx, atomic_cnt),
205
203
TP_STRUCT__entry(
206
204
__field( uint32_t, drm_id )
207
205
__field( enum dpu_intr_idx, intr_idx )
208
-
__field( int, hw_idx )
209
206
__field( int, irq_idx )
210
207
__field( enum dpu_pingpong, pp_idx )
211
208
__field( int, atomic_cnt )
···
210
213
TP_fast_assign(
211
214
__entry->drm_id = drm_id;
212
215
__entry->intr_idx = intr_idx;
213
-
__entry->hw_idx = hw_idx;
214
216
__entry->irq_idx = irq_idx;
215
217
__entry->pp_idx = pp_idx;
216
218
__entry->atomic_cnt = atomic_cnt;
217
219
),
218
-
TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
219
-
__entry->drm_id, __entry->intr_idx, __entry->hw_idx,
220
+
TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d",
221
+
__entry->drm_id, __entry->intr_idx,
220
222
__entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
221
223
);
222
224
···
510
514
);
511
515
512
516
TRACE_EVENT(dpu_enc_wait_event_timeout,
513
-
TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
517
+
TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
514
518
s64 expected_time, int atomic_cnt),
515
-
TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
519
+
TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
516
520
TP_STRUCT__entry(
517
521
__field( uint32_t, drm_id )
518
-
__field( int32_t, hw_id )
522
+
__field( int, irq_idx )
519
523
__field( int, rc )
520
524
__field( s64, time )
521
525
__field( s64, expected_time )
···
523
527
),
524
528
TP_fast_assign(
525
529
__entry->drm_id = drm_id;
526
-
__entry->hw_id = hw_id;
530
+
__entry->irq_idx = irq_idx;
527
531
__entry->rc = rc;
528
532
__entry->time = time;
529
533
__entry->expected_time = expected_time;
530
534
__entry->atomic_cnt = atomic_cnt;
531
535
),
532
-
TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
533
-
__entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
536
+
TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
537
+
__entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
534
538
__entry->expected_time, __entry->atomic_cnt)
535
539
);
536
540
···
873
877
__entry->cfg = cfg;
874
878
),
875
879
TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
876
-
);
877
-
878
-
DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
879
-
TP_PROTO(int irq_idx, int enable_count),
880
-
TP_ARGS(irq_idx, enable_count),
881
-
TP_STRUCT__entry(
882
-
__field( int, irq_idx )
883
-
__field( int, enable_count )
884
-
),
885
-
TP_fast_assign(
886
-
__entry->irq_idx = irq_idx;
887
-
__entry->enable_count = enable_count;
888
-
),
889
-
TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
890
-
__entry->enable_count)
891
-
);
892
-
DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
893
-
TP_PROTO(int irq_idx, int enable_count),
894
-
TP_ARGS(irq_idx, enable_count)
895
-
);
896
-
DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
897
-
TP_PROTO(int irq_idx, int enable_count),
898
-
TP_ARGS(irq_idx, enable_count)
899
880
);
900
881
901
882
DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
···
46
46
vbif->idx - VBIF_0, xin_id);
47
47
} else {
48
48
rc = 0;
49
-
DPU_DEBUG("VBIF %d client %d is halted\n",
49
+
DRM_DEBUG_ATOMIC("VBIF %d client %d is halted\n",
50
50
vbif->idx - VBIF_0, xin_id);
51
51
}
52
52
···
87
87
}
88
88
}
89
89
90
-
DPU_DEBUG("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",
90
+
DRM_DEBUG_ATOMIC("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n",
91
91
vbif->idx - VBIF_0, params->xin_id,
92
92
params->width, params->height, params->frame_rate,
93
93
pps, *ot_lim);
···
133
133
}
134
134
135
135
exit:
136
-
DPU_DEBUG("vbif:%d xin:%d ot_lim:%d\n",
136
+
DRM_DEBUG_ATOMIC("vbif:%d xin:%d ot_lim:%d\n",
137
137
vbif->idx - VBIF_0, params->xin_id, ot_lim);
138
138
return ot_lim;
139
139
}
···
163
163
}
164
164
165
165
if (!vbif || !mdp) {
166
-
DPU_DEBUG("invalid arguments vbif %d mdp %d\n",
166
+
DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n",
167
167
vbif != NULL, mdp != NULL);
168
168
return;
169
169
}
···
230
230
}
231
231
232
232
if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) {
233
-
DPU_DEBUG("qos remap not supported\n");
233
+
DRM_DEBUG_ATOMIC("qos remap not supported\n");
234
234
return;
235
235
}
236
236
···
238
238
&vbif->cap->qos_nrt_tbl;
239
239
240
240
if (!qos_tbl->npriority_lvl || !qos_tbl->priority_lvl) {
241
-
DPU_DEBUG("qos tbl not defined\n");
241
+
DRM_DEBUG_ATOMIC("qos tbl not defined\n");
242
242
return;
243
243
}
244
244
245
245
forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true);
246
246
247
247
for (i = 0; i < qos_tbl->npriority_lvl; i++) {
248
-
DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n",
248
+
DRM_DEBUG_ATOMIC("vbif:%d xin:%d lvl:%d/%d\n",
249
249
params->vbif_idx, params->xin_id, i,
250
250
qos_tbl->priority_lvl[i]);
251
251
vbif->ops.set_qos_remap(vbif, params->xin_id, i,
+20
-12
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
+20
-12
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+24
-12
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
+24
-12
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
···
86
78
SSPP_RGB3 = 10,
87
79
SSPP_CURSOR0 = 11,
88
80
SSPP_CURSOR1 = 12,
81
+
};
82
+
83
+
enum mdp5_format {
84
+
DUMMY = 0,
89
85
};
90
86
91
87
enum mdp5_ctl_mode {
+35
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+35
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
···
95
95
[3] = INTF_HDMI,
96
96
},
97
97
},
98
+
.perf = {
99
+
.ab_inefficiency = 200,
100
+
.ib_inefficiency = 120,
101
+
.clk_inefficiency = 125
102
+
},
98
103
.max_clk = 200000000,
99
104
};
100
105
···
181
176
[2] = INTF_DSI,
182
177
[3] = INTF_HDMI,
183
178
},
179
+
},
180
+
.perf = {
181
+
.ab_inefficiency = 200,
182
+
.ib_inefficiency = 120,
183
+
.clk_inefficiency = 125
184
184
},
185
185
.max_clk = 320000000,
186
186
};
···
282
272
[3] = INTF_HDMI,
283
273
},
284
274
},
275
+
.perf = {
276
+
.ab_inefficiency = 200,
277
+
.ib_inefficiency = 120,
278
+
.clk_inefficiency = 105
279
+
},
285
280
.max_clk = 320000000,
286
281
};
287
282
···
353
338
[0] = INTF_DISABLED,
354
339
[1] = INTF_DSI,
355
340
},
341
+
},
342
+
.perf = {
343
+
.ab_inefficiency = 100,
344
+
.ib_inefficiency = 200,
345
+
.clk_inefficiency = 105
356
346
},
357
347
.max_clk = 320000000,
358
348
};
···
433
413
[1] = INTF_DSI,
434
414
[2] = INTF_DSI,
435
415
},
416
+
},
417
+
.perf = {
418
+
.ab_inefficiency = 100,
419
+
.ib_inefficiency = 200,
420
+
.clk_inefficiency = 105
436
421
},
437
422
.max_clk = 366670000,
438
423
};
···
533
508
[2] = INTF_DSI,
534
509
[3] = INTF_HDMI,
535
510
},
511
+
},
512
+
.perf = {
513
+
.ab_inefficiency = 100,
514
+
.ib_inefficiency = 100,
515
+
.clk_inefficiency = 105
536
516
},
537
517
.max_clk = 400000000,
538
518
};
···
646
616
[2] = INTF_DSI,
647
617
[3] = INTF_HDMI,
648
618
},
619
+
},
620
+
.perf = {
621
+
.ab_inefficiency = 100,
622
+
.ib_inefficiency = 200,
623
+
.clk_inefficiency = 105
649
624
},
650
625
.max_clk = 412500000,
651
626
};
+7
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
+7
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
···
76
76
u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
77
77
};
78
78
79
+
struct mdp5_perf_block {
80
+
u32 ab_inefficiency;
81
+
u32 ib_inefficiency;
82
+
u32 clk_inefficiency;
83
+
};
84
+
79
85
struct mdp5_cfg_hw {
80
86
char *name;
81
87
···
99
93
struct mdp5_sub_block dsc;
100
94
struct mdp5_sub_block cdm;
101
95
struct mdp5_intf_block intf;
96
+
struct mdp5_perf_block perf;
102
97
103
98
uint32_t max_clk;
104
99
};
+7
-5
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+7
-5
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
···
291
291
plane = pstates[i]->base.plane;
292
292
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
293
293
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
294
-
fg_alpha = pstates[i]->alpha;
295
-
bg_alpha = 0xFF - pstates[i]->alpha;
294
+
fg_alpha = pstates[i]->base.alpha >> 8;
295
+
bg_alpha = 0xFF - fg_alpha;
296
296
297
297
if (!format->alpha_enable && bg_alpha_enabled)
298
298
mixer_op_mode = 0;
···
301
301
302
302
DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
303
303
304
-
if (format->alpha_enable && pstates[i]->premultiplied) {
304
+
if (format->alpha_enable &&
305
+
pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
305
306
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
306
307
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
307
308
if (fg_alpha != 0xff) {
···
313
312
} else {
314
313
blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
315
314
}
316
-
} else if (format->alpha_enable) {
315
+
} else if (format->alpha_enable &&
316
+
pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
317
317
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
318
318
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
319
319
if (fg_alpha != 0xff) {
···
650
648
{
651
649
struct plane_state *pa = (struct plane_state *)a;
652
650
struct plane_state *pb = (struct plane_state *)b;
653
-
return pa->state->zpos - pb->state->zpos;
651
+
return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos;
654
652
}
655
653
656
654
/* is there a helper for this? */
-5
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
-5
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
···
98
98
struct mdp5_hw_pipe *hwpipe;
99
99
struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */
100
100
101
-
/* aligned with property */
102
-
uint8_t premultiplied;
103
-
uint8_t zpos;
104
-
uint8_t alpha;
105
-
106
101
/* assigned by crtc blender */
107
102
enum mdp_mixer_stage_id stage;
108
103
};
+19
-116
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+19
-116
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
···
44
44
kfree(mdp5_plane);
45
45
}
46
46
47
-
static void mdp5_plane_install_rotation_property(struct drm_device *dev,
48
-
struct drm_plane *plane)
47
+
/* helper to install properties which are common to planes and crtcs */
48
+
static void mdp5_plane_install_properties(struct drm_plane *plane,
49
+
struct drm_mode_object *obj)
49
50
{
50
51
drm_plane_create_rotation_property(plane,
51
52
DRM_MODE_ROTATE_0,
···
54
53
DRM_MODE_ROTATE_180 |
55
54
DRM_MODE_REFLECT_X |
56
55
DRM_MODE_REFLECT_Y);
57
-
}
58
-
59
-
/* helper to install properties which are common to planes and crtcs */
60
-
static void mdp5_plane_install_properties(struct drm_plane *plane,
61
-
struct drm_mode_object *obj)
62
-
{
63
-
struct drm_device *dev = plane->dev;
64
-
struct msm_drm_private *dev_priv = dev->dev_private;
65
-
struct drm_property *prop;
66
-
67
-
#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
68
-
prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
69
-
if (!prop) { \
70
-
prop = drm_property_##fnc(dev, 0, #name, \
71
-
##__VA_ARGS__); \
72
-
if (!prop) { \
73
-
dev_warn(dev->dev, \
74
-
"Create property %s failed\n", \
75
-
#name); \
76
-
return; \
77
-
} \
78
-
dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
79
-
} \
80
-
drm_object_attach_property(&plane->base, prop, init_val); \
81
-
} while (0)
82
-
83
-
#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
84
-
INSTALL_PROPERTY(name, NAME, init_val, \
85
-
create_range, min, max)
86
-
87
-
#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
88
-
INSTALL_PROPERTY(name, NAME, init_val, \
89
-
create_enum, name##_prop_enum_list, \
90
-
ARRAY_SIZE(name##_prop_enum_list))
91
-
92
-
INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
93
-
94
-
mdp5_plane_install_rotation_property(dev, plane);
95
-
96
-
#undef INSTALL_RANGE_PROPERTY
97
-
#undef INSTALL_ENUM_PROPERTY
98
-
#undef INSTALL_PROPERTY
99
-
}
100
-
101
-
static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
102
-
struct drm_plane_state *state, struct drm_property *property,
103
-
uint64_t val)
104
-
{
105
-
struct drm_device *dev = plane->dev;
106
-
struct mdp5_plane_state *pstate;
107
-
struct msm_drm_private *dev_priv = dev->dev_private;
108
-
int ret = 0;
109
-
110
-
pstate = to_mdp5_plane_state(state);
111
-
112
-
#define SET_PROPERTY(name, NAME, type) do { \
113
-
if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
114
-
pstate->name = (type)val; \
115
-
DBG("Set property %s %d", #name, (type)val); \
116
-
goto done; \
117
-
} \
118
-
} while (0)
119
-
120
-
SET_PROPERTY(zpos, ZPOS, uint8_t);
121
-
122
-
DRM_DEV_ERROR(dev->dev, "Invalid property\n");
123
-
ret = -EINVAL;
124
-
done:
125
-
return ret;
126
-
#undef SET_PROPERTY
127
-
}
128
-
129
-
static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
130
-
const struct drm_plane_state *state,
131
-
struct drm_property *property, uint64_t *val)
132
-
{
133
-
struct drm_device *dev = plane->dev;
134
-
struct mdp5_plane_state *pstate;
135
-
struct msm_drm_private *dev_priv = dev->dev_private;
136
-
int ret = 0;
137
-
138
-
pstate = to_mdp5_plane_state(state);
139
-
140
-
#define GET_PROPERTY(name, NAME, type) do { \
141
-
if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
142
-
*val = pstate->name; \
143
-
DBG("Get property %s %lld", #name, *val); \
144
-
goto done; \
145
-
} \
146
-
} while (0)
147
-
148
-
GET_PROPERTY(zpos, ZPOS, uint8_t);
149
-
150
-
DRM_DEV_ERROR(dev->dev, "Invalid property\n");
151
-
ret = -EINVAL;
152
-
done:
153
-
return ret;
154
-
#undef SET_PROPERTY
56
+
drm_plane_create_alpha_property(plane);
57
+
drm_plane_create_blend_mode_property(plane,
58
+
BIT(DRM_MODE_BLEND_PIXEL_NONE) |
59
+
BIT(DRM_MODE_BLEND_PREMULTI) |
60
+
BIT(DRM_MODE_BLEND_COVERAGE));
61
+
drm_plane_create_zpos_property(plane, 1, 1, 255);
155
62
}
156
63
157
64
static void
···
75
166
drm_printf(p, "\tright-hwpipe=%s\n",
76
167
pstate->r_hwpipe ? pstate->r_hwpipe->name :
77
168
"(null)");
78
-
drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
79
-
drm_printf(p, "\tzpos=%u\n", pstate->zpos);
80
-
drm_printf(p, "\talpha=%u\n", pstate->alpha);
169
+
drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode);
170
+
drm_printf(p, "\tzpos=%u\n", pstate->base.zpos);
171
+
drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos);
172
+
drm_printf(p, "\talpha=%u\n", pstate->base.alpha);
81
173
drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
82
174
}
83
175
···
86
176
{
87
177
struct mdp5_plane_state *mdp5_state;
88
178
89
-
if (plane->state && plane->state->fb)
90
-
drm_framebuffer_put(plane->state->fb);
179
+
if (plane->state)
180
+
__drm_atomic_helper_plane_destroy_state(plane->state);
91
181
92
182
kfree(to_mdp5_plane_state(plane->state));
93
183
mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
94
184
95
-
/* assign default blend parameters */
96
-
mdp5_state->alpha = 255;
97
-
mdp5_state->premultiplied = 0;
98
-
99
185
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
100
-
mdp5_state->zpos = STAGE_BASE;
186
+
mdp5_state->base.zpos = STAGE_BASE;
101
187
else
102
-
mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
188
+
mdp5_state->base.zpos = STAGE0 + drm_plane_index(plane);
189
+
mdp5_state->base.normalized_zpos = mdp5_state->base.zpos;
103
190
104
-
mdp5_state->base.plane = plane;
105
-
106
-
plane->state = &mdp5_state->base;
191
+
__drm_atomic_helper_plane_reset(plane, &mdp5_state->base);
107
192
}
108
193
109
194
static struct drm_plane_state *
···
134
229
.update_plane = drm_atomic_helper_update_plane,
135
230
.disable_plane = drm_atomic_helper_disable_plane,
136
231
.destroy = mdp5_plane_destroy,
137
-
.atomic_set_property = mdp5_plane_atomic_set_property,
138
-
.atomic_get_property = mdp5_plane_atomic_get_property,
139
232
.reset = mdp5_plane_reset,
140
233
.atomic_duplicate_state = mdp5_plane_duplicate_state,
141
234
.atomic_destroy_state = mdp5_plane_destroy_state,
+20
-12
drivers/gpu/drm/msm/disp/mdp_common.xml.h
+20
-12
drivers/gpu/drm/msm/disp/mdp_common.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+125
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c
+125
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
+
8
+
#include "msm_disp_snapshot.h"
9
+
10
+
static ssize_t __maybe_unused disp_devcoredump_read(char *buffer, loff_t offset,
11
+
size_t count, void *data, size_t datalen)
12
+
{
13
+
struct drm_print_iterator iter;
14
+
struct drm_printer p;
15
+
struct msm_disp_state *disp_state;
16
+
17
+
disp_state = data;
18
+
19
+
iter.data = buffer;
20
+
iter.offset = 0;
21
+
iter.start = offset;
22
+
iter.remain = count;
23
+
24
+
p = drm_coredump_printer(&iter);
25
+
26
+
msm_disp_state_print(disp_state, &p);
27
+
28
+
return count - iter.remain;
29
+
}
30
+
31
+
static void _msm_disp_snapshot_work(struct kthread_work *work)
32
+
{
33
+
struct msm_kms *kms = container_of(work, struct msm_kms, dump_work);
34
+
struct drm_device *drm_dev = kms->dev;
35
+
struct msm_disp_state *disp_state;
36
+
struct drm_printer p;
37
+
38
+
disp_state = kzalloc(sizeof(struct msm_disp_state), GFP_KERNEL);
39
+
if (!disp_state)
40
+
return;
41
+
42
+
disp_state->dev = drm_dev->dev;
43
+
disp_state->drm_dev = drm_dev;
44
+
45
+
INIT_LIST_HEAD(&disp_state->blocks);
46
+
47
+
/* Serialize dumping here */
48
+
mutex_lock(&kms->dump_mutex);
49
+
50
+
msm_disp_snapshot_capture_state(disp_state);
51
+
52
+
mutex_unlock(&kms->dump_mutex);
53
+
54
+
if (MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) {
55
+
p = drm_info_printer(disp_state->drm_dev->dev);
56
+
msm_disp_state_print(disp_state, &p);
57
+
}
58
+
59
+
/*
60
+
* If COREDUMP is disabled, the stub will call the free function.
61
+
* If there is a codedump pending for the device, the dev_coredumpm()
62
+
* will also free new coredump state.
63
+
*/
64
+
dev_coredumpm(disp_state->dev, THIS_MODULE, disp_state, 0, GFP_KERNEL,
65
+
disp_devcoredump_read, msm_disp_state_free);
66
+
}
67
+
68
+
void msm_disp_snapshot_state(struct drm_device *drm_dev)
69
+
{
70
+
struct msm_drm_private *priv;
71
+
struct msm_kms *kms;
72
+
73
+
if (!drm_dev) {
74
+
DRM_ERROR("invalid params\n");
75
+
return;
76
+
}
77
+
78
+
priv = drm_dev->dev_private;
79
+
kms = priv->kms;
80
+
81
+
kthread_queue_work(kms->dump_worker, &kms->dump_work);
82
+
}
83
+
84
+
int msm_disp_snapshot_init(struct drm_device *drm_dev)
85
+
{
86
+
struct msm_drm_private *priv;
87
+
struct msm_kms *kms;
88
+
89
+
if (!drm_dev) {
90
+
DRM_ERROR("invalid params\n");
91
+
return -EINVAL;
92
+
}
93
+
94
+
priv = drm_dev->dev_private;
95
+
kms = priv->kms;
96
+
97
+
mutex_init(&kms->dump_mutex);
98
+
99
+
kms->dump_worker = kthread_create_worker(0, "%s", "disp_snapshot");
100
+
if (IS_ERR(kms->dump_worker))
101
+
DRM_ERROR("failed to create disp state task\n");
102
+
103
+
kthread_init_work(&kms->dump_work, _msm_disp_snapshot_work);
104
+
105
+
return 0;
106
+
}
107
+
108
+
void msm_disp_snapshot_destroy(struct drm_device *drm_dev)
109
+
{
110
+
struct msm_kms *kms;
111
+
struct msm_drm_private *priv;
112
+
113
+
if (!drm_dev) {
114
+
DRM_ERROR("invalid params\n");
115
+
return;
116
+
}
117
+
118
+
priv = drm_dev->dev_private;
119
+
kms = priv->kms;
120
+
121
+
if (kms->dump_worker)
122
+
kthread_destroy_worker(kms->dump_worker);
123
+
124
+
mutex_destroy(&kms->dump_mutex);
125
+
}
+136
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h
+136
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef MSM_DISP_SNAPSHOT_H_
7
+
#define MSM_DISP_SNAPSHOT_H_
8
+
9
+
#include <drm/drm_atomic_helper.h>
10
+
#include <drm/drm_device.h>
11
+
#include "../../../drm_crtc_internal.h"
12
+
#include <drm/drm_print.h>
13
+
#include <drm/drm_atomic.h>
14
+
#include <linux/debugfs.h>
15
+
#include <linux/list.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/spinlock.h>
18
+
#include <linux/ktime.h>
19
+
#include <linux/debugfs.h>
20
+
#include <linux/uaccess.h>
21
+
#include <linux/dma-buf.h>
22
+
#include <linux/slab.h>
23
+
#include <linux/list_sort.h>
24
+
#include <linux/pm.h>
25
+
#include <linux/pm_runtime.h>
26
+
#include <linux/kthread.h>
27
+
#include <linux/devcoredump.h>
28
+
#include <stdarg.h>
29
+
#include "msm_kms.h"
30
+
31
+
#define MSM_DISP_SNAPSHOT_MAX_BLKS 10
32
+
33
+
/* debug option to print the registers in logs */
34
+
#define MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE 0
35
+
36
+
/* print debug ranges in groups of 4 u32s */
37
+
#define REG_DUMP_ALIGN 16
38
+
39
+
/**
40
+
* struct msm_disp_state - structure to store current dpu state
41
+
* @dev: device pointer
42
+
* @drm_dev: drm device pointer
43
+
* @atomic_state: atomic state duplicated at the time of the error
44
+
* @timestamp: timestamp at which the coredump was captured
45
+
*/
46
+
struct msm_disp_state {
47
+
struct device *dev;
48
+
struct drm_device *drm_dev;
49
+
50
+
struct list_head blocks;
51
+
52
+
struct drm_atomic_state *atomic_state;
53
+
54
+
ktime_t timestamp;
55
+
};
56
+
57
+
/**
58
+
* struct msm_disp_state_block - structure to store each hardware block state
59
+
* @name: name of the block
60
+
* @drm_dev: handle to the linked list head
61
+
* @size: size of the register space of this hardware block
62
+
* @state: array holding the register dump of this hardware block
63
+
* @base_addr: starting address of this hardware block's register space
64
+
*/
65
+
struct msm_disp_state_block {
66
+
char name[SZ_128];
67
+
struct list_head node;
68
+
unsigned int size;
69
+
u32 *state;
70
+
void __iomem *base_addr;
71
+
};
72
+
73
+
/**
74
+
* msm_disp_snapshot_init - initialize display snapshot
75
+
* @drm_dev: drm device handle
76
+
*
77
+
* Returns: 0 or -ERROR
78
+
*/
79
+
int msm_disp_snapshot_init(struct drm_device *drm_dev);
80
+
81
+
/**
82
+
* msm_disp_snapshot_destroy - destroy the display snapshot
83
+
* @drm_dev: drm device handle
84
+
*
85
+
* Returns: none
86
+
*/
87
+
void msm_disp_snapshot_destroy(struct drm_device *drm_dev);
88
+
89
+
/**
90
+
* msm_disp_snapshot_state - trigger to dump the display snapshot
91
+
* @drm_dev: handle to drm device
92
+
93
+
* Returns: none
94
+
*/
95
+
void msm_disp_snapshot_state(struct drm_device *drm_dev);
96
+
97
+
/**
98
+
* msm_disp_state_print - print out the current dpu state
99
+
* @disp_state: handle to drm device
100
+
* @p: handle to drm printer
101
+
*
102
+
* Returns: none
103
+
*/
104
+
void msm_disp_state_print(struct msm_disp_state *disp_state, struct drm_printer *p);
105
+
106
+
/**
107
+
* msm_disp_snapshot_capture_state - utility to capture atomic state and hw registers
108
+
* @disp_state: handle to msm_disp_state struct
109
+
110
+
* Returns: none
111
+
*/
112
+
void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state);
113
+
114
+
/**
115
+
* msm_disp_state_free - free the memory after the coredump has been read
116
+
* @data: handle to struct msm_disp_state
117
+
118
+
* Returns: none
119
+
*/
120
+
void msm_disp_state_free(void *data);
121
+
122
+
/**
123
+
* msm_disp_snapshot_add_block - add a hardware block with its register dump
124
+
* @disp_state: handle to struct msm_disp_state
125
+
* @name: name of the hardware block
126
+
* @len: size of the register space of the hardware block
127
+
* @base_addr: starting address of the register space of the hardware block
128
+
* @fmt: format in which the block names need to be printed
129
+
*
130
+
* Returns: none
131
+
*/
132
+
__printf(4, 5)
133
+
void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
134
+
void __iomem *base_addr, const char *fmt, ...);
135
+
136
+
#endif /* MSM_DISP_SNAPSHOT_H_ */
+187
drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c
+187
drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
+
8
+
#include "msm_disp_snapshot.h"
9
+
10
+
static void msm_disp_state_dump_regs(u32 **reg, u32 aligned_len, void __iomem *base_addr)
11
+
{
12
+
u32 len_padded;
13
+
u32 num_rows;
14
+
u32 x0, x4, x8, xc;
15
+
void __iomem *addr;
16
+
u32 *dump_addr = NULL;
17
+
void __iomem *end_addr;
18
+
int i;
19
+
20
+
len_padded = aligned_len * REG_DUMP_ALIGN;
21
+
num_rows = aligned_len / REG_DUMP_ALIGN;
22
+
23
+
addr = base_addr;
24
+
end_addr = base_addr + aligned_len;
25
+
26
+
if (!(*reg))
27
+
*reg = kzalloc(len_padded, GFP_KERNEL);
28
+
29
+
if (*reg)
30
+
dump_addr = *reg;
31
+
32
+
for (i = 0; i < num_rows; i++) {
33
+
x0 = (addr < end_addr) ? readl_relaxed(addr + 0x0) : 0;
34
+
x4 = (addr + 0x4 < end_addr) ? readl_relaxed(addr + 0x4) : 0;
35
+
x8 = (addr + 0x8 < end_addr) ? readl_relaxed(addr + 0x8) : 0;
36
+
xc = (addr + 0xc < end_addr) ? readl_relaxed(addr + 0xc) : 0;
37
+
38
+
if (dump_addr) {
39
+
dump_addr[i * 4] = x0;
40
+
dump_addr[i * 4 + 1] = x4;
41
+
dump_addr[i * 4 + 2] = x8;
42
+
dump_addr[i * 4 + 3] = xc;
43
+
}
44
+
45
+
addr += REG_DUMP_ALIGN;
46
+
}
47
+
}
48
+
49
+
static void msm_disp_state_print_regs(u32 **reg, u32 len, void __iomem *base_addr,
50
+
struct drm_printer *p)
51
+
{
52
+
int i;
53
+
u32 *dump_addr = NULL;
54
+
void __iomem *addr;
55
+
u32 num_rows;
56
+
57
+
addr = base_addr;
58
+
num_rows = len / REG_DUMP_ALIGN;
59
+
60
+
if (*reg)
61
+
dump_addr = *reg;
62
+
63
+
for (i = 0; i < num_rows; i++) {
64
+
drm_printf(p, "0x%lx : %08x %08x %08x %08x\n",
65
+
(unsigned long)(addr - base_addr),
66
+
dump_addr[i * 4], dump_addr[i * 4 + 1],
67
+
dump_addr[i * 4 + 2], dump_addr[i * 4 + 3]);
68
+
addr += REG_DUMP_ALIGN;
69
+
}
70
+
}
71
+
72
+
void msm_disp_state_print(struct msm_disp_state *state, struct drm_printer *p)
73
+
{
74
+
struct msm_disp_state_block *block, *tmp;
75
+
76
+
if (!p) {
77
+
DRM_ERROR("invalid drm printer\n");
78
+
return;
79
+
}
80
+
81
+
drm_printf(p, "---\n");
82
+
83
+
drm_printf(p, "module: " KBUILD_MODNAME "\n");
84
+
drm_printf(p, "dpu devcoredump\n");
85
+
drm_printf(p, "timestamp %lld\n", ktime_to_ns(state->timestamp));
86
+
87
+
list_for_each_entry_safe(block, tmp, &state->blocks, node) {
88
+
drm_printf(p, "====================%s================\n", block->name);
89
+
msm_disp_state_print_regs(&block->state, block->size, block->base_addr, p);
90
+
}
91
+
92
+
drm_printf(p, "===================dpu drm state================\n");
93
+
94
+
if (state->atomic_state)
95
+
drm_atomic_print_new_state(state->atomic_state, p);
96
+
}
97
+
98
+
static void msm_disp_capture_atomic_state(struct msm_disp_state *disp_state)
99
+
{
100
+
struct drm_device *ddev;
101
+
struct drm_modeset_acquire_ctx ctx;
102
+
103
+
disp_state->timestamp = ktime_get();
104
+
105
+
ddev = disp_state->drm_dev;
106
+
107
+
drm_modeset_acquire_init(&ctx, 0);
108
+
109
+
while (drm_modeset_lock_all_ctx(ddev, &ctx) != 0)
110
+
drm_modeset_backoff(&ctx);
111
+
112
+
disp_state->atomic_state = drm_atomic_helper_duplicate_state(ddev,
113
+
&ctx);
114
+
drm_modeset_drop_locks(&ctx);
115
+
drm_modeset_acquire_fini(&ctx);
116
+
}
117
+
118
+
void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state)
119
+
{
120
+
struct msm_drm_private *priv;
121
+
struct drm_device *drm_dev;
122
+
struct msm_kms *kms;
123
+
int i;
124
+
125
+
drm_dev = disp_state->drm_dev;
126
+
priv = drm_dev->dev_private;
127
+
kms = priv->kms;
128
+
129
+
if (priv->dp)
130
+
msm_dp_snapshot(disp_state, priv->dp);
131
+
132
+
for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
133
+
if (!priv->dsi[i])
134
+
continue;
135
+
136
+
msm_dsi_snapshot(disp_state, priv->dsi[i]);
137
+
}
138
+
139
+
if (kms->funcs->snapshot)
140
+
kms->funcs->snapshot(disp_state, kms);
141
+
142
+
msm_disp_capture_atomic_state(disp_state);
143
+
}
144
+
145
+
void msm_disp_state_free(void *data)
146
+
{
147
+
struct msm_disp_state *disp_state = data;
148
+
struct msm_disp_state_block *block, *tmp;
149
+
150
+
if (disp_state->atomic_state) {
151
+
drm_atomic_state_put(disp_state->atomic_state);
152
+
disp_state->atomic_state = NULL;
153
+
}
154
+
155
+
list_for_each_entry_safe(block, tmp, &disp_state->blocks, node) {
156
+
list_del(&block->node);
157
+
kfree(block->state);
158
+
kfree(block);
159
+
}
160
+
161
+
kfree(disp_state);
162
+
}
163
+
164
+
void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len,
165
+
void __iomem *base_addr, const char *fmt, ...)
166
+
{
167
+
struct msm_disp_state_block *new_blk;
168
+
struct va_format vaf;
169
+
va_list va;
170
+
171
+
new_blk = kzalloc(sizeof(struct msm_disp_state_block), GFP_KERNEL);
172
+
173
+
va_start(va, fmt);
174
+
175
+
vaf.fmt = fmt;
176
+
vaf.va = &va;
177
+
snprintf(new_blk->name, sizeof(new_blk->name), "%pV", &vaf);
178
+
179
+
va_end(va);
180
+
181
+
INIT_LIST_HEAD(&new_blk->node);
182
+
new_blk->size = ALIGN(len, REG_DUMP_ALIGN);
183
+
new_blk->base_addr = base_addr;
184
+
185
+
msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr);
186
+
list_add(&new_blk->node, &disp_state->blocks);
187
+
}
+78
-103
drivers/gpu/drm/msm/dp/dp_aux.c
+78
-103
drivers/gpu/drm/msm/dp/dp_aux.c
···
9
9
#include "dp_reg.h"
10
10
#include "dp_aux.h"
11
11
12
-
#define DP_AUX_ENUM_STR(x) #x
12
+
enum msm_dp_aux_err {
13
+
DP_AUX_ERR_NONE,
14
+
DP_AUX_ERR_ADDR,
15
+
DP_AUX_ERR_TOUT,
16
+
DP_AUX_ERR_NACK,
17
+
DP_AUX_ERR_DEFER,
18
+
DP_AUX_ERR_NACK_DEFER,
19
+
DP_AUX_ERR_PHY,
20
+
};
13
21
14
22
struct dp_aux_private {
15
23
struct device *dev;
···
26
18
struct mutex mutex;
27
19
struct completion comp;
28
20
29
-
u32 aux_error_num;
21
+
enum msm_dp_aux_err aux_error_num;
30
22
u32 retry_cnt;
31
23
bool cmd_busy;
32
24
bool native;
···
35
27
bool no_send_stop;
36
28
u32 offset;
37
29
u32 segment;
38
-
u32 isr;
39
30
40
31
struct drm_dp_aux dp_aux;
41
32
};
42
33
43
34
#define MAX_AUX_RETRIES 5
44
35
45
-
static const char *dp_aux_get_error(u32 aux_error)
46
-
{
47
-
switch (aux_error) {
48
-
case DP_AUX_ERR_NONE:
49
-
return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE);
50
-
case DP_AUX_ERR_ADDR:
51
-
return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
52
-
case DP_AUX_ERR_TOUT:
53
-
return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
54
-
case DP_AUX_ERR_NACK:
55
-
return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
56
-
case DP_AUX_ERR_DEFER:
57
-
return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
58
-
case DP_AUX_ERR_NACK_DEFER:
59
-
return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
60
-
default:
61
-
return "unknown";
62
-
}
63
-
}
64
-
65
-
static u32 dp_aux_write(struct dp_aux_private *aux,
36
+
static ssize_t dp_aux_write(struct dp_aux_private *aux,
66
37
struct drm_dp_aux_msg *msg)
67
38
{
68
-
u32 data[4], reg, len;
39
+
u8 data[4];
40
+
u32 reg;
41
+
ssize_t len;
69
42
u8 *msgdata = msg->buffer;
70
43
int const AUX_CMD_FIFO_LEN = 128;
71
44
int i = 0;
72
45
73
46
if (aux->read)
74
-
len = 4;
47
+
len = 0;
75
48
else
76
-
len = msg->size + 4;
49
+
len = msg->size;
77
50
78
51
/*
79
52
* cmd fifo only has depth of 144 bytes
80
53
* limit buf length to 128 bytes here
81
54
*/
82
-
if (len > AUX_CMD_FIFO_LEN) {
55
+
if (len > AUX_CMD_FIFO_LEN - 4) {
83
56
DRM_ERROR("buf size greater than allowed size of 128 bytes\n");
84
-
return 0;
57
+
return -EINVAL;
85
58
}
86
59
87
60
/* Pack cmd and write to HW */
88
-
data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
61
+
data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
89
62
if (aux->read)
90
-
data[0] |= BIT(4); /* R/W */
63
+
data[0] |= BIT(4); /* R/W */
91
64
92
-
data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */
93
-
data[2] = msg->address & 0xff; /* addr[7:0] */
94
-
data[3] = (msg->size - 1) & 0xff; /* len[7:0] */
65
+
data[1] = msg->address >> 8; /* addr[15:8] */
66
+
data[2] = msg->address; /* addr[7:0] */
67
+
data[3] = msg->size - 1; /* len[7:0] */
95
68
96
-
for (i = 0; i < len; i++) {
69
+
for (i = 0; i < len + 4; i++) {
97
70
reg = (i < 4) ? data[i] : msgdata[i - 4];
71
+
reg <<= DP_AUX_DATA_OFFSET;
72
+
reg &= DP_AUX_DATA_MASK;
73
+
reg |= DP_AUX_DATA_WRITE;
98
74
/* index = 0, write */
99
-
reg = (((reg) << DP_AUX_DATA_OFFSET)
100
-
& DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE;
101
75
if (i == 0)
102
76
reg |= DP_AUX_DATA_INDEX_WRITE;
103
77
aux->catalog->aux_data = reg;
···
107
117
return len;
108
118
}
109
119
110
-
static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
120
+
static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
111
121
struct drm_dp_aux_msg *msg)
112
122
{
113
-
u32 ret, len, timeout;
114
-
int aux_timeout_ms = HZ/4;
123
+
ssize_t ret;
124
+
unsigned long time_left;
115
125
116
126
reinit_completion(&aux->comp);
117
127
118
-
len = dp_aux_write(aux, msg);
119
-
if (len == 0) {
120
-
DRM_ERROR("DP AUX write failed\n");
121
-
return -EINVAL;
122
-
}
128
+
ret = dp_aux_write(aux, msg);
129
+
if (ret < 0)
130
+
return ret;
123
131
124
-
timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
125
-
if (!timeout) {
126
-
DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write"));
132
+
time_left = wait_for_completion_timeout(&aux->comp,
133
+
msecs_to_jiffies(250));
134
+
if (!time_left)
127
135
return -ETIMEDOUT;
128
-
}
129
-
130
-
if (aux->aux_error_num == DP_AUX_ERR_NONE) {
131
-
ret = len;
132
-
} else {
133
-
DRM_ERROR_RATELIMITED("aux err: %s\n",
134
-
dp_aux_get_error(aux->aux_error_num));
135
-
136
-
ret = -EINVAL;
137
-
}
138
136
139
137
return ret;
140
138
}
141
139
142
-
static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
140
+
static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
143
141
struct drm_dp_aux_msg *msg)
144
142
{
145
143
u32 data;
···
154
176
155
177
actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF;
156
178
if (i != actual_i)
157
-
DRM_ERROR("Index mismatch: expected %d, found %d\n",
158
-
i, actual_i);
179
+
break;
159
180
}
181
+
182
+
return i;
160
183
}
161
184
162
-
static void dp_aux_native_handler(struct dp_aux_private *aux)
185
+
static void dp_aux_native_handler(struct dp_aux_private *aux, u32 isr)
163
186
{
164
-
u32 isr = aux->isr;
165
-
166
187
if (isr & DP_INTR_AUX_I2C_DONE)
167
188
aux->aux_error_num = DP_AUX_ERR_NONE;
168
189
else if (isr & DP_INTR_WRONG_ADDR)
···
174
197
aux->aux_error_num = DP_AUX_ERR_PHY;
175
198
dp_catalog_aux_clear_hw_interrupts(aux->catalog);
176
199
}
177
-
178
-
complete(&aux->comp);
179
200
}
180
201
181
-
static void dp_aux_i2c_handler(struct dp_aux_private *aux)
202
+
static void dp_aux_i2c_handler(struct dp_aux_private *aux, u32 isr)
182
203
{
183
-
u32 isr = aux->isr;
184
-
185
204
if (isr & DP_INTR_AUX_I2C_DONE) {
186
205
if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
187
206
aux->aux_error_num = DP_AUX_ERR_NACK;
···
199
226
dp_catalog_aux_clear_hw_interrupts(aux->catalog);
200
227
}
201
228
}
202
-
203
-
complete(&aux->comp);
204
229
}
205
230
206
231
static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
···
309
338
ssize_t ret;
310
339
int const aux_cmd_native_max = 16;
311
340
int const aux_cmd_i2c_max = 128;
312
-
struct dp_aux_private *aux = container_of(dp_aux,
313
-
struct dp_aux_private, dp_aux);
341
+
struct dp_aux_private *aux;
314
342
315
-
mutex_lock(&aux->mutex);
343
+
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
316
344
317
345
aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
318
346
319
347
/* Ignore address only message */
320
-
if ((msg->size == 0) || (msg->buffer == NULL)) {
348
+
if (msg->size == 0 || !msg->buffer) {
321
349
msg->reply = aux->native ?
322
350
DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
323
-
ret = msg->size;
324
-
goto unlock_exit;
351
+
return msg->size;
325
352
}
326
353
327
354
/* msg sanity check */
328
-
if ((aux->native && (msg->size > aux_cmd_native_max)) ||
329
-
(msg->size > aux_cmd_i2c_max)) {
355
+
if ((aux->native && msg->size > aux_cmd_native_max) ||
356
+
msg->size > aux_cmd_i2c_max) {
330
357
DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n",
331
358
__func__, msg->size, msg->request);
332
-
ret = -EINVAL;
333
-
goto unlock_exit;
359
+
return -EINVAL;
334
360
}
361
+
362
+
mutex_lock(&aux->mutex);
335
363
336
364
dp_aux_update_offset_and_segment(aux, msg);
337
365
dp_aux_transfer_helper(aux, msg, true);
···
347
377
}
348
378
349
379
ret = dp_aux_cmd_fifo_tx(aux, msg);
350
-
351
380
if (ret < 0) {
352
381
if (aux->native) {
353
382
aux->retry_cnt++;
354
383
if (!(aux->retry_cnt % MAX_AUX_RETRIES))
355
384
dp_catalog_aux_update_cfg(aux->catalog);
356
385
}
357
-
usleep_range(400, 500); /* at least 400us to next try */
358
-
goto unlock_exit;
359
-
}
360
-
361
-
if (aux->aux_error_num == DP_AUX_ERR_NONE) {
362
-
if (aux->read)
363
-
dp_aux_cmd_fifo_rx(aux, msg);
364
-
365
-
msg->reply = aux->native ?
366
-
DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
367
386
} else {
368
-
/* Reply defer to retry */
369
-
msg->reply = aux->native ?
370
-
DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
387
+
aux->retry_cnt = 0;
388
+
switch (aux->aux_error_num) {
389
+
case DP_AUX_ERR_NONE:
390
+
if (aux->read)
391
+
ret = dp_aux_cmd_fifo_rx(aux, msg);
392
+
msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
393
+
break;
394
+
case DP_AUX_ERR_DEFER:
395
+
msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
396
+
break;
397
+
case DP_AUX_ERR_PHY:
398
+
case DP_AUX_ERR_ADDR:
399
+
case DP_AUX_ERR_NACK:
400
+
case DP_AUX_ERR_NACK_DEFER:
401
+
msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_NACK : DP_AUX_I2C_REPLY_NACK;
402
+
break;
403
+
case DP_AUX_ERR_TOUT:
404
+
ret = -ETIMEDOUT;
405
+
break;
406
+
}
371
407
}
372
408
373
-
/* Return requested size for success or retry */
374
-
ret = msg->size;
375
-
aux->retry_cnt = 0;
376
-
377
-
unlock_exit:
378
409
aux->cmd_busy = false;
379
410
mutex_unlock(&aux->mutex);
411
+
380
412
return ret;
381
413
}
382
414
383
415
void dp_aux_isr(struct drm_dp_aux *dp_aux)
384
416
{
417
+
u32 isr;
385
418
struct dp_aux_private *aux;
386
419
387
420
if (!dp_aux) {
···
394
421
395
422
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
396
423
397
-
aux->isr = dp_catalog_aux_get_irq(aux->catalog);
424
+
isr = dp_catalog_aux_get_irq(aux->catalog);
398
425
399
426
if (!aux->cmd_busy)
400
427
return;
401
428
402
429
if (aux->native)
403
-
dp_aux_native_handler(aux);
430
+
dp_aux_native_handler(aux, isr);
404
431
else
405
-
dp_aux_i2c_handler(aux);
432
+
dp_aux_i2c_handler(aux, isr);
433
+
434
+
complete(&aux->comp);
406
435
}
407
436
408
437
void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
-8
drivers/gpu/drm/msm/dp/dp_aux.h
-8
drivers/gpu/drm/msm/dp/dp_aux.h
···
9
9
#include "dp_catalog.h"
10
10
#include <drm/drm_dp_helper.h>
11
11
12
-
#define DP_AUX_ERR_NONE 0
13
-
#define DP_AUX_ERR_ADDR -1
14
-
#define DP_AUX_ERR_TOUT -2
15
-
#define DP_AUX_ERR_NACK -3
16
-
#define DP_AUX_ERR_DEFER -4
17
-
#define DP_AUX_ERR_NACK_DEFER -5
18
-
#define DP_AUX_ERR_PHY -6
19
-
20
12
int dp_aux_register(struct drm_dp_aux *dp_aux);
21
13
void dp_aux_unregister(struct drm_dp_aux *dp_aux);
22
14
void dp_aux_isr(struct drm_dp_aux *dp_aux);
+13
-5
drivers/gpu/drm/msm/dp/dp_catalog.c
+13
-5
drivers/gpu/drm/msm/dp/dp_catalog.c
···
62
62
u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
63
63
};
64
64
65
+
void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
66
+
{
67
+
struct dp_catalog_private *catalog = container_of(dp_catalog,
68
+
struct dp_catalog_private, dp_catalog);
69
+
70
+
msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len,
71
+
catalog->io->dp_controller.base, "dp_ctrl");
72
+
}
73
+
65
74
static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset)
66
75
{
67
76
offset += MSM_DP_CONTROLLER_AUX_OFFSET;
···
202
193
/**
203
194
* dp_catalog_aux_reset() - reset AUX controller
204
195
*
205
-
* @aux: DP catalog structure
196
+
* @dp_catalog: DP catalog structure
206
197
*
207
198
* return: void
208
199
*
···
301
292
dump_regs(catalog->io->dp_controller.base + offset, len);
302
293
}
303
294
304
-
int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
295
+
u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
305
296
{
306
297
struct dp_catalog_private *catalog = container_of(dp_catalog,
307
298
struct dp_catalog_private, dp_catalog);
···
591
582
592
583
u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
593
584
594
-
/* enable HPD interrupts */
585
+
/* enable HPD plug and unplug interrupts */
595
586
dp_catalog_hpd_config_intr(dp_catalog,
596
-
DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK
597
-
| DP_DP_HPD_UNPLUG_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true);
587
+
DP_DP_HPD_PLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK, true);
598
588
599
589
/* Configure REFTIMER and enable it */
600
590
reftimer |= DP_DP_HPD_REFTIMER_ENABLE;
+5
-2
drivers/gpu/drm/msm/dp/dp_catalog.h
+5
-2
drivers/gpu/drm/msm/dp/dp_catalog.h
···
9
9
#include <drm/drm_modes.h>
10
10
11
11
#include "dp_parser.h"
12
+
#include "disp/msm_disp_snapshot.h"
12
13
13
14
/* interrupts */
14
15
#define DP_INTR_HPD BIT(0)
···
72
71
u32 audio_data;
73
72
};
74
73
74
+
/* Debug module */
75
+
void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state);
76
+
75
77
/* AUX APIs */
76
78
u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
77
79
int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
···
84
80
void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
85
81
void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
86
82
void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog);
87
-
int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
83
+
u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
88
84
89
85
/* DP Controller APIs */
90
86
void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
···
127
123
void dp_catalog_audio_get_header(struct dp_catalog *catalog);
128
124
void dp_catalog_audio_set_header(struct dp_catalog *catalog);
129
125
void dp_catalog_audio_config_acr(struct dp_catalog *catalog);
130
-
void dp_catalog_audio_enable(struct dp_catalog *catalog);
131
126
void dp_catalog_audio_enable(struct dp_catalog *catalog);
132
127
void dp_catalog_audio_config_sdp(struct dp_catalog *catalog);
133
128
void dp_catalog_audio_init(struct dp_catalog *catalog);
+63
-24
drivers/gpu/drm/msm/dp/dp_ctrl.c
+63
-24
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
77
77
struct dp_parser *parser;
78
78
struct dp_catalog *catalog;
79
79
80
-
struct opp_table *opp_table;
81
-
82
80
struct completion idle_comp;
83
81
struct completion video_comp;
84
82
};
···
1807
1809
return ret;
1808
1810
}
1809
1811
1812
+
int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1813
+
{
1814
+
struct dp_ctrl_private *ctrl;
1815
+
struct dp_io *dp_io;
1816
+
struct phy *phy;
1817
+
int ret;
1818
+
1819
+
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1820
+
dp_io = &ctrl->parser->io;
1821
+
phy = dp_io->phy;
1822
+
1823
+
/* set dongle to D3 (power off) mode */
1824
+
dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1825
+
1826
+
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1827
+
1828
+
if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1829
+
ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1830
+
if (ret) {
1831
+
DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1832
+
return ret;
1833
+
}
1834
+
}
1835
+
1836
+
ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1837
+
if (ret) {
1838
+
DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1839
+
return ret;
1840
+
}
1841
+
1842
+
phy_power_off(phy);
1843
+
1844
+
/* aux channel down, reinit phy */
1845
+
phy_exit(phy);
1846
+
phy_init(phy);
1847
+
1848
+
DRM_DEBUG_DP("DP off link/stream done\n");
1849
+
return ret;
1850
+
}
1851
+
1852
+
void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl)
1853
+
{
1854
+
struct dp_ctrl_private *ctrl;
1855
+
struct dp_io *dp_io;
1856
+
struct phy *phy;
1857
+
1858
+
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1859
+
dp_io = &ctrl->parser->io;
1860
+
phy = dp_io->phy;
1861
+
1862
+
dp_catalog_ctrl_reset(ctrl->catalog);
1863
+
1864
+
phy_exit(phy);
1865
+
1866
+
DRM_DEBUG_DP("DP off phy done\n");
1867
+
}
1868
+
1810
1869
int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1811
1870
{
1812
1871
struct dp_ctrl_private *ctrl;
···
1941
1886
return ERR_PTR(-ENOMEM);
1942
1887
}
1943
1888
1944
-
ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");
1945
-
if (IS_ERR(ctrl->opp_table)) {
1889
+
ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
1890
+
if (ret) {
1946
1891
dev_err(dev, "invalid DP OPP table in device tree\n");
1947
-
/* caller do PTR_ERR(ctrl->opp_table) */
1948
-
return (struct dp_ctrl *)ctrl->opp_table;
1892
+
/* caller do PTR_ERR(opp_table) */
1893
+
return (struct dp_ctrl *)ERR_PTR(ret);
1949
1894
}
1950
1895
1951
1896
/* OPP table is optional */
1952
-
ret = dev_pm_opp_of_add_table(dev);
1953
-
if (ret) {
1897
+
ret = devm_pm_opp_of_add_table(dev);
1898
+
if (ret)
1954
1899
dev_err(dev, "failed to add DP OPP table\n");
1955
-
dev_pm_opp_put_clkname(ctrl->opp_table);
1956
-
ctrl->opp_table = NULL;
1957
-
}
1958
1900
1959
1901
init_completion(&ctrl->idle_comp);
1960
1902
init_completion(&ctrl->video_comp);
···
1966
1914
ctrl->dev = dev;
1967
1915
1968
1916
return &ctrl->dp_ctrl;
1969
-
}
1970
-
1971
-
void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
1972
-
{
1973
-
struct dp_ctrl_private *ctrl;
1974
-
1975
-
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1976
-
1977
-
if (ctrl->opp_table) {
1978
-
dev_pm_opp_of_remove_table(ctrl->dev);
1979
-
dev_pm_opp_put_clkname(ctrl->opp_table);
1980
-
ctrl->opp_table = NULL;
1981
-
}
1982
1917
}
+2
-1
drivers/gpu/drm/msm/dp/dp_ctrl.h
+2
-1
drivers/gpu/drm/msm/dp/dp_ctrl.h
···
23
23
void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl);
24
24
int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
25
25
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);
26
+
int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);
27
+
void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl);
26
28
int dp_ctrl_off(struct dp_ctrl *dp_ctrl);
27
29
void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl);
28
30
void dp_ctrl_isr(struct dp_ctrl *dp_ctrl);
···
33
31
struct dp_panel *panel, struct drm_dp_aux *aux,
34
32
struct dp_power *power, struct dp_catalog *catalog,
35
33
struct dp_parser *parser);
36
-
void dp_ctrl_put(struct dp_ctrl *dp_ctrl);
37
34
38
35
#endif /* _DP_CTRL_H_ */
+76
-45
drivers/gpu/drm/msm/dp/dp_display.c
+76
-45
drivers/gpu/drm/msm/dp/dp_display.c
···
208
208
209
209
dp = container_of(g_dp_display,
210
210
struct dp_display_private, dp_display);
211
-
if (!dp) {
212
-
DRM_ERROR("DP driver bind failed. Invalid driver data\n");
213
-
return -EINVAL;
214
-
}
215
211
216
212
dp->dp_display.drm_dev = drm;
217
213
priv = drm->dev_private;
···
248
252
249
253
dp = container_of(g_dp_display,
250
254
struct dp_display_private, dp_display);
251
-
if (!dp) {
252
-
DRM_ERROR("Invalid DP driver data\n");
253
-
return;
254
-
}
255
255
256
256
dp_power_client_deinit(dp->power);
257
257
dp_aux_unregister(dp->aux);
···
338
346
dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;
339
347
dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes;
340
348
349
+
/*
350
+
* set sink to normal operation mode -- D0
351
+
* before dpcd read
352
+
*/
353
+
dp_link_psm_config(dp->link, &dp->panel->link_info, false);
354
+
341
355
dp_link_reset_phy_params_vx_px(dp->link);
342
356
rc = dp_ctrl_on_link(dp->ctrl);
343
357
if (rc) {
···
404
406
405
407
dp = container_of(g_dp_display,
406
408
struct dp_display_private, dp_display);
407
-
if (!dp) {
408
-
DRM_ERROR("no driver data found\n");
409
-
rc = -ENODEV;
410
-
goto end;
411
-
}
412
409
413
410
dp_display_host_init(dp, false);
414
411
415
-
/*
416
-
* set sink to normal operation mode -- D0
417
-
* before dpcd read
418
-
*/
419
-
dp_link_psm_config(dp->link, &dp->panel->link_info, false);
420
412
rc = dp_display_process_hpd_high(dp);
421
413
end:
422
414
return rc;
···
425
437
426
438
dp = container_of(g_dp_display,
427
439
struct dp_display_private, dp_display);
428
-
if (!dp) {
429
-
DRM_ERROR("no driver data found\n");
430
-
rc = -ENODEV;
431
-
return rc;
432
-
}
433
440
434
441
dp_add_event(dp, EV_USER_NOTIFICATION, false, 0);
435
442
···
485
502
int rc = 0;
486
503
u32 sink_request;
487
504
struct dp_display_private *dp;
488
-
struct dp_usbpd *hpd;
489
505
490
506
if (!dev) {
491
507
DRM_ERROR("invalid dev\n");
···
493
511
494
512
dp = container_of(g_dp_display,
495
513
struct dp_display_private, dp_display);
496
-
if (!dp) {
497
-
DRM_ERROR("no driver data found\n");
498
-
return -ENODEV;
499
-
}
500
-
501
-
hpd = dp->usbpd;
502
514
503
515
/* check for any test request issued by sink */
504
516
rc = dp_link_process_request(dp->link);
···
555
579
dp_add_event(dp, EV_CONNECT_PENDING_TIMEOUT, 0, tout);
556
580
}
557
581
582
+
/* enable HDP irq_hpd/replug interrupt */
583
+
dp_catalog_hpd_config_intr(dp->catalog,
584
+
DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true);
585
+
558
586
mutex_unlock(&dp->event_mutex);
559
587
560
588
/* uevent will complete connection part */
···
608
628
mutex_lock(&dp->event_mutex);
609
629
610
630
state = dp->hpd_state;
611
-
if (state == ST_DISCONNECT_PENDING || state == ST_DISCONNECTED) {
631
+
632
+
/* disable irq_hpd/replug interrupts */
633
+
dp_catalog_hpd_config_intr(dp->catalog,
634
+
DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false);
635
+
636
+
/* unplugged, no more irq_hpd handle */
637
+
dp_del_event(dp, EV_IRQ_HPD_INT);
638
+
639
+
if (state == ST_DISCONNECTED) {
640
+
/* triggered by irq_hdp with sink_count = 0 */
641
+
if (dp->link->sink_count == 0) {
642
+
dp_ctrl_off_phy(dp->ctrl);
643
+
hpd->hpd_high = 0;
644
+
dp->core_initialized = false;
645
+
}
646
+
mutex_unlock(&dp->event_mutex);
647
+
return 0;
648
+
}
649
+
650
+
if (state == ST_DISCONNECT_PENDING) {
612
651
mutex_unlock(&dp->event_mutex);
613
652
return 0;
614
653
}
···
641
642
642
643
dp->hpd_state = ST_DISCONNECT_PENDING;
643
644
644
-
/* disable HPD plug interrupt until disconnect is done */
645
-
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK
646
-
| DP_DP_IRQ_HPD_INT_MASK, false);
645
+
/* disable HPD plug interrupts */
646
+
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false);
647
647
648
648
hpd->hpd_high = 0;
649
649
···
658
660
/* signal the disconnect event early to ensure proper teardown */
659
661
dp_display_handle_plugged_change(g_dp_display, false);
660
662
661
-
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK |
662
-
DP_DP_IRQ_HPD_INT_MASK, true);
663
+
/* enable HDP plug interrupt to prepare for next plugin */
664
+
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, true);
663
665
664
666
/* uevent will complete disconnection part */
665
667
mutex_unlock(&dp->event_mutex);
···
690
692
691
693
/* irq_hpd can happen at either connected or disconnected state */
692
694
state = dp->hpd_state;
693
-
if (state == ST_DISPLAY_OFF) {
695
+
if (state == ST_DISPLAY_OFF || state == ST_SUSPENDED) {
694
696
mutex_unlock(&dp->event_mutex);
695
697
return 0;
696
698
}
···
722
724
static void dp_display_deinit_sub_modules(struct dp_display_private *dp)
723
725
{
724
726
dp_debug_put(dp->debug);
725
-
dp_ctrl_put(dp->ctrl);
726
727
dp_panel_put(dp->panel);
727
728
dp_aux_put(dp->aux);
728
729
dp_audio_put(dp->audio);
···
815
818
rc = PTR_ERR(dp->audio);
816
819
pr_err("failed to initialize audio, rc = %d\n", rc);
817
820
dp->audio = NULL;
818
-
goto error_audio;
821
+
goto error_ctrl;
819
822
}
820
823
821
824
return rc;
822
825
823
-
error_audio:
824
-
dp_ctrl_put(dp->ctrl);
825
826
error_ctrl:
826
827
dp_panel_put(dp->panel);
827
828
error_link:
···
905
910
906
911
dp_display->audio_enabled = false;
907
912
908
-
dp_ctrl_off(dp->ctrl);
909
-
910
-
dp->core_initialized = false;
913
+
/* triggered by irq_hpd with sink_count = 0 */
914
+
if (dp->link->sink_count == 0) {
915
+
dp_ctrl_off_link_stream(dp->ctrl);
916
+
} else {
917
+
dp_ctrl_off(dp->ctrl);
918
+
dp->core_initialized = false;
919
+
}
911
920
912
921
dp_display->power_on = false;
913
922
···
1009
1010
1010
1011
return dp_link_bit_depth_to_bpp(
1011
1012
dp_display->link->test_video.test_bit_depth);
1013
+
}
1014
+
1015
+
void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp)
1016
+
{
1017
+
struct dp_display_private *dp_display;
1018
+
struct drm_device *drm;
1019
+
1020
+
dp_display = container_of(dp, struct dp_display_private, dp_display);
1021
+
drm = dp->drm_dev;
1022
+
1023
+
/*
1024
+
* if we are reading registers we need the link clocks to be on
1025
+
* however till DP cable is connected this will not happen as we
1026
+
* do not know the resolution to power up with. Hence check the
1027
+
* power_on status before dumping DP registers to avoid crash due
1028
+
* to unclocked access
1029
+
*/
1030
+
mutex_lock(&dp_display->event_mutex);
1031
+
1032
+
if (!dp->power_on) {
1033
+
mutex_unlock(&dp_display->event_mutex);
1034
+
return;
1035
+
}
1036
+
1037
+
dp_catalog_snapshot(dp_display->catalog, disp_state);
1038
+
1039
+
mutex_unlock(&dp_display->event_mutex);
1012
1040
}
1013
1041
1014
1042
static void dp_display_config_hpd(struct dp_display_private *dp)
···
1326
1300
1327
1301
mutex_lock(&dp->event_mutex);
1328
1302
1329
-
if (dp->core_initialized == true)
1303
+
if (dp->core_initialized == true) {
1304
+
/* mainlink enabled */
1305
+
if (dp_power_clk_status(dp->power, DP_CTRL_PM))
1306
+
dp_ctrl_off_link_stream(dp->ctrl);
1307
+
1330
1308
dp_display_host_deinit(dp);
1309
+
}
1331
1310
1332
1311
dp->hpd_state = ST_SUSPENDED;
1333
1312
+1
drivers/gpu/drm/msm/dp/dp_display.h
+1
drivers/gpu/drm/msm/dp/dp_display.h
+6
-15
drivers/gpu/drm/msm/dp/dp_link.c
+6
-15
drivers/gpu/drm/msm/dp/dp_link.c
···
364
364
}
365
365
366
366
/**
367
-
* dp_parse_video_pattern_params() - parses video pattern parameters from DPCD
367
+
* dp_link_parse_video_pattern_params() - parses video pattern parameters from DPCD
368
368
* @link: Display Port Driver data
369
369
*
370
370
* Returns 0 if it successfully parses the video link pattern and the link
···
563
563
}
564
564
565
565
/**
566
-
* dp_parse_phy_test_params() - parses the phy link parameters
566
+
* dp_link_parse_phy_test_params() - parses the phy link parameters
567
567
* @link: Display Port Driver data
568
568
*
569
569
* Parses the DPCD (Byte 0x248) for the DP PHY link pattern that is being
···
843
843
return ret == 1;
844
844
}
845
845
846
-
static int dp_link_parse_vx_px(struct dp_link_private *link)
846
+
static void dp_link_parse_vx_px(struct dp_link_private *link)
847
847
{
848
-
int ret = 0;
849
-
850
848
DRM_DEBUG_DP("vx: 0=%d, 1=%d, 2=%d, 3=%d\n",
851
849
drm_dp_get_adjust_request_voltage(link->link_status, 0),
852
850
drm_dp_get_adjust_request_voltage(link->link_status, 1),
···
874
876
DRM_DEBUG_DP("Requested: v_level = 0x%x, p_level = 0x%x\n",
875
877
link->dp_link.phy_params.v_level,
876
878
link->dp_link.phy_params.p_level);
877
-
878
-
return ret;
879
879
}
880
880
881
881
/**
···
887
891
static int dp_link_process_phy_test_pattern_request(
888
892
struct dp_link_private *link)
889
893
{
890
-
int ret = 0;
891
-
892
894
if (!(link->request.test_requested & DP_TEST_LINK_PHY_TEST_PATTERN)) {
893
895
DRM_DEBUG_DP("no phy test\n");
894
896
return -EINVAL;
···
912
918
link->dp_link.link_params.rate =
913
919
drm_dp_bw_code_to_link_rate(link->request.test_link_rate);
914
920
915
-
ret = dp_link_parse_vx_px(link);
921
+
dp_link_parse_vx_px(link);
916
922
917
-
if (ret)
918
-
DRM_ERROR("parse_vx_px failed. ret=%d\n", ret);
919
-
920
-
return ret;
923
+
return 0;
921
924
}
922
925
923
926
static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
···
952
961
}
953
962
954
963
/**
955
-
* dp_link_process_downstream_port_status_change() - process port status changes
964
+
* dp_link_process_ds_port_status_change() - process port status changes
956
965
* @link: Display Port Driver data
957
966
*
958
967
* This function will handle downstream port updates that are initiated by
+1
-3
drivers/gpu/drm/msm/dp/dp_panel.c
+1
-3
drivers/gpu/drm/msm/dp/dp_panel.c
···
141
141
return rc;
142
142
}
143
143
rc = drm_add_edid_modes(connector, edid);
144
-
DRM_DEBUG_DP("%s -", __func__);
145
144
return rc;
146
145
}
147
146
···
350
351
351
352
int dp_panel_timing_cfg(struct dp_panel *dp_panel)
352
353
{
353
-
int rc = 0;
354
354
u32 data, total_ver, total_hor;
355
355
struct dp_catalog *catalog;
356
356
struct dp_panel_private *panel;
···
402
404
dp_catalog_panel_timing_cfg(catalog);
403
405
panel->panel_on = true;
404
406
405
-
return rc;
407
+
return 0;
406
408
}
407
409
408
410
int dp_panel_init_panel_info(struct dp_panel *dp_panel)
+2
-2
drivers/gpu/drm/msm/dp/dp_power.h
+2
-2
drivers/gpu/drm/msm/dp/dp_power.h
···
88
88
* return: 0 for success, error for failure.
89
89
*
90
90
* This API will de-initialize the DisplayPort's clocks and regulator
91
-
* modueles.
91
+
* modules.
92
92
*/
93
93
void dp_power_client_deinit(struct dp_power *power);
94
94
···
100
100
*
101
101
* This API will configure the DisplayPort's power module and provides
102
102
* methods to be called by the client to configure the power related
103
-
* modueles.
103
+
* modules.
104
104
*/
105
105
struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser);
106
106
+6
drivers/gpu/drm/msm/dsi/dsi.c
+6
drivers/gpu/drm/msm/dsi/dsi.c
+3
-1
drivers/gpu/drm/msm/dsi/dsi.h
+3
-1
drivers/gpu/drm/msm/dsi/dsi.h
···
15
15
#include <drm/drm_panel.h>
16
16
17
17
#include "msm_drv.h"
18
+
#include "disp/msm_disp_snapshot.h"
18
19
19
20
#define DSI_0 0
20
21
#define DSI_1 1
···
147
146
int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
148
147
int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);
149
148
int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);
150
-
149
+
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
151
150
/* dsi phy */
152
151
struct msm_dsi_phy;
153
152
struct msm_dsi_phy_shared_timings {
···
174
173
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
175
174
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
176
175
int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);
176
+
void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy);
177
177
178
178
#endif /* __DSI_CONNECTOR_H__ */
179
179
+21
-1699
drivers/gpu/drm/msm/dsi/dsi.xml.h
+21
-1699
drivers/gpu/drm/msm/dsi/dsi.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
···
629
621
return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
630
622
}
631
623
632
-
#define REG_DSI_PHY_PLL_CTRL_0 0x00000200
633
-
#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
624
+
#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
634
625
635
-
#define REG_DSI_PHY_PLL_CTRL_1 0x00000204
636
-
637
-
#define REG_DSI_PHY_PLL_CTRL_2 0x00000208
638
-
639
-
#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
640
-
641
-
#define REG_DSI_PHY_PLL_CTRL_4 0x00000210
642
-
643
-
#define REG_DSI_PHY_PLL_CTRL_5 0x00000214
644
-
645
-
#define REG_DSI_PHY_PLL_CTRL_6 0x00000218
646
-
647
-
#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
648
-
649
-
#define REG_DSI_PHY_PLL_CTRL_8 0x00000220
650
-
651
-
#define REG_DSI_PHY_PLL_CTRL_9 0x00000224
652
-
653
-
#define REG_DSI_PHY_PLL_CTRL_10 0x00000228
654
-
655
-
#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
656
-
657
-
#define REG_DSI_PHY_PLL_CTRL_12 0x00000230
658
-
659
-
#define REG_DSI_PHY_PLL_CTRL_13 0x00000234
660
-
661
-
#define REG_DSI_PHY_PLL_CTRL_14 0x00000238
662
-
663
-
#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
664
-
665
-
#define REG_DSI_PHY_PLL_CTRL_16 0x00000240
666
-
667
-
#define REG_DSI_PHY_PLL_CTRL_17 0x00000244
668
-
669
-
#define REG_DSI_PHY_PLL_CTRL_18 0x00000248
670
-
671
-
#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
672
-
673
-
#define REG_DSI_PHY_PLL_CTRL_20 0x00000250
674
-
675
-
#define REG_DSI_PHY_PLL_STATUS 0x00000280
676
-
#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
677
-
678
-
#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
679
-
680
-
#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
681
-
682
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
683
-
684
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
685
-
686
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
687
-
688
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
689
-
690
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
691
-
692
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
693
-
694
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
695
-
696
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
697
-
698
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
699
-
700
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
701
-
702
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
703
-
704
-
#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
705
-
706
-
#define REG_DSI_8x60_PHY_CTRL_0 0x00000290
707
-
708
-
#define REG_DSI_8x60_PHY_CTRL_1 0x00000294
709
-
710
-
#define REG_DSI_8x60_PHY_CTRL_2 0x00000298
711
-
712
-
#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
713
-
714
-
#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
715
-
716
-
#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
717
-
718
-
#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
719
-
720
-
#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
721
-
722
-
#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
723
-
724
-
#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
725
-
726
-
#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
727
-
728
-
#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
729
-
730
-
#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
731
-
732
-
#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
733
-
734
-
#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
735
-
736
-
#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
737
-
#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
738
-
739
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
740
-
741
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
742
-
743
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
744
-
745
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
746
-
747
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
748
-
749
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
750
-
751
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
752
-
753
-
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
754
-
755
-
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
756
-
757
-
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
758
-
759
-
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
760
-
761
-
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
762
-
763
-
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
764
-
765
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
766
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
767
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
768
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
769
-
{
770
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
771
-
}
772
-
773
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
774
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
775
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
776
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
777
-
{
778
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
779
-
}
780
-
781
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
782
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
783
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
784
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
785
-
{
786
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
787
-
}
788
-
789
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
790
-
791
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
792
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
793
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
794
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
795
-
{
796
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
797
-
}
798
-
799
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
800
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
801
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
802
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
803
-
{
804
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
805
-
}
806
-
807
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
808
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
809
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
810
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
811
-
{
812
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
813
-
}
814
-
815
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
816
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
817
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
818
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
819
-
{
820
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
821
-
}
822
-
823
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
824
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
825
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
826
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
827
-
{
828
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
829
-
}
830
-
831
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
832
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
833
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
834
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
835
-
{
836
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
837
-
}
838
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
839
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
840
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
841
-
{
842
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
843
-
}
844
-
845
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
846
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
847
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
848
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
849
-
{
850
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
851
-
}
852
-
853
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
854
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
855
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
856
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
857
-
{
858
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
859
-
}
860
-
861
-
#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
862
-
863
-
#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
864
-
865
-
#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
866
-
867
-
#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
868
-
869
-
#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
870
-
871
-
#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
872
-
873
-
#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
874
-
875
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
876
-
877
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
878
-
879
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
880
-
881
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
882
-
883
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
884
-
885
-
#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
886
-
887
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
888
-
889
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
890
-
891
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
892
-
893
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
894
-
895
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
896
-
897
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
898
-
899
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
900
-
901
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
902
-
903
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
904
-
905
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
906
-
907
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
908
-
909
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
910
-
911
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
912
-
913
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
914
-
915
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
916
-
917
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
918
-
919
-
#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
920
-
#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
921
-
922
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
923
-
#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
924
-
925
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
926
-
927
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
928
-
929
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
930
-
931
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
932
-
933
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
934
-
935
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
936
-
937
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
938
-
939
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
940
-
941
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
942
-
943
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
944
-
945
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
946
-
947
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
948
-
949
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
950
-
951
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
952
-
953
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
954
-
955
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
956
-
957
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
958
-
959
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
960
-
961
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
962
-
963
-
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
964
-
965
-
#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
966
-
#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
967
-
968
-
static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
969
-
970
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
971
-
972
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
973
-
974
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
975
-
976
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
977
-
978
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
979
-
980
-
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
981
-
982
-
static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
983
-
984
-
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
985
-
986
-
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
987
-
988
-
#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
989
-
990
-
#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
991
-
992
-
#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
993
-
994
-
#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
995
-
996
-
#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
997
-
998
-
#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
999
-
1000
-
#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
1001
-
1002
-
#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
1003
-
1004
-
#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
1005
-
1006
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
1007
-
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1008
-
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1009
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1010
-
{
1011
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1012
-
}
1013
-
1014
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
1015
-
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1016
-
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1017
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1018
-
{
1019
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1020
-
}
1021
-
1022
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
1023
-
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1024
-
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1025
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1026
-
{
1027
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1028
-
}
1029
-
1030
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
1031
-
#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1032
-
1033
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
1034
-
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1035
-
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1036
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1037
-
{
1038
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1039
-
}
1040
-
1041
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
1042
-
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1043
-
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1044
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1045
-
{
1046
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1047
-
}
1048
-
1049
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
1050
-
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1051
-
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1052
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1053
-
{
1054
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1055
-
}
1056
-
1057
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
1058
-
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1059
-
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1060
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1061
-
{
1062
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1063
-
}
1064
-
1065
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
1066
-
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1067
-
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1068
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1069
-
{
1070
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1071
-
}
1072
-
1073
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
1074
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1075
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1076
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1077
-
{
1078
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1079
-
}
1080
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1081
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1082
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1083
-
{
1084
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1085
-
}
1086
-
1087
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
1088
-
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1089
-
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1090
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1091
-
{
1092
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1093
-
}
1094
-
1095
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
1096
-
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1097
-
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1098
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1099
-
{
1100
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1101
-
}
1102
-
1103
-
#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
1104
-
1105
-
#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
1106
-
1107
-
#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
1108
-
1109
-
#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
1110
-
1111
-
#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
1112
-
1113
-
#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
1114
-
1115
-
#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
1116
-
1117
-
#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
1118
-
1119
-
#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
1120
-
1121
-
#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
1122
-
1123
-
#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
1124
-
1125
-
#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
1126
-
1127
-
#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
1128
-
1129
-
#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
1130
-
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1131
-
1132
-
#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
1133
-
1134
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
1135
-
1136
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
1137
-
1138
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
1139
-
1140
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
1141
-
1142
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
1143
-
1144
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
1145
-
1146
-
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1147
-
1148
-
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
1149
-
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
1150
-
1151
-
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
1152
-
1153
-
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
1154
-
1155
-
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
1156
-
1157
-
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
1158
-
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
1159
-
1160
-
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
1161
-
1162
-
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
1163
-
1164
-
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
1165
-
1166
-
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
1167
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1168
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1169
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1170
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1171
-
1172
-
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1173
-
1174
-
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1175
-
1176
-
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1177
-
1178
-
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1179
-
1180
-
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1181
-
1182
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1183
-
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1184
-
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1185
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
1186
-
{
1187
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
1188
-
}
1189
-
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1190
-
1191
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1192
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1193
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1194
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
1195
-
{
1196
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
1197
-
}
1198
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1199
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
1200
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
1201
-
{
1202
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
1203
-
}
1204
-
1205
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1206
-
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1207
-
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1208
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
1209
-
{
1210
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
1211
-
}
1212
-
1213
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1214
-
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1215
-
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1216
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
1217
-
{
1218
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
1219
-
}
1220
-
1221
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1222
-
1223
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1224
-
1225
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1226
-
1227
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1228
-
1229
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1230
-
1231
-
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1232
-
1233
-
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1234
-
1235
-
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1236
-
1237
-
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1238
-
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1239
-
1240
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1241
-
1242
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1243
-
1244
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1245
-
1246
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1247
-
1248
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1249
-
1250
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1251
-
1252
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1253
-
1254
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1255
-
1256
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1257
-
1258
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1259
-
1260
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1261
-
1262
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1263
-
1264
-
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1265
-
1266
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1267
-
1268
-
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1269
-
1270
-
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1271
-
1272
-
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1273
-
1274
-
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1275
-
1276
-
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1277
-
1278
-
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1279
-
1280
-
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1281
-
1282
-
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1283
-
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1284
-
1285
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1286
-
1287
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1288
-
1289
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1290
-
1291
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1292
-
1293
-
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1294
-
1295
-
static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1296
-
1297
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
1298
-
1299
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
1300
-
1301
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
1302
-
1303
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
1304
-
1305
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
1306
-
1307
-
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
1308
-
1309
-
static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
1310
-
1311
-
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
1312
-
1313
-
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
1314
-
1315
-
#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1316
-
1317
-
#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1318
-
1319
-
#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1320
-
1321
-
#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1322
-
1323
-
#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1324
-
1325
-
#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1326
-
1327
-
#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1328
-
1329
-
#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1330
-
1331
-
#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1332
-
1333
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1334
-
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1335
-
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1336
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
1337
-
{
1338
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
1339
-
}
1340
-
1341
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1342
-
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1343
-
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1344
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
1345
-
{
1346
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
1347
-
}
1348
-
1349
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1350
-
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1351
-
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1352
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
1353
-
{
1354
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
1355
-
}
1356
-
1357
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1358
-
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1359
-
1360
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1361
-
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1362
-
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1363
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1364
-
{
1365
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
1366
-
}
1367
-
1368
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1369
-
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1370
-
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1371
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1372
-
{
1373
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
1374
-
}
1375
-
1376
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1377
-
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1378
-
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1379
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1380
-
{
1381
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
1382
-
}
1383
-
1384
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1385
-
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1386
-
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1387
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1388
-
{
1389
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
1390
-
}
1391
-
1392
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1393
-
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1394
-
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1395
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
1396
-
{
1397
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
1398
-
}
1399
-
1400
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1401
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1402
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1403
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
1404
-
{
1405
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
1406
-
}
1407
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1408
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
1409
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
1410
-
{
1411
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
1412
-
}
1413
-
1414
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1415
-
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1416
-
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1417
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
1418
-
{
1419
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
1420
-
}
1421
-
1422
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1423
-
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1424
-
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1425
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1426
-
{
1427
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
1428
-
}
1429
-
1430
-
#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1431
-
1432
-
#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1433
-
1434
-
#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1435
-
1436
-
#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1437
-
1438
-
#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1439
-
1440
-
#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1441
-
1442
-
#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1443
-
1444
-
#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1445
-
1446
-
#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1447
-
1448
-
#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1449
-
1450
-
#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1451
-
1452
-
#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1453
-
1454
-
#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1455
-
1456
-
#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1457
-
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1458
-
1459
-
#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1460
-
1461
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1462
-
1463
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1464
-
1465
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1466
-
1467
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1468
-
1469
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1470
-
1471
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1472
-
1473
-
#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1474
-
1475
-
#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
1476
-
1477
-
#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
1478
-
1479
-
#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
1480
-
1481
-
#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
1482
-
1483
-
#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
1484
-
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
1485
-
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
1486
-
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
1487
-
{
1488
-
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
1489
-
}
1490
-
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
1491
-
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
1492
-
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
1493
-
{
1494
-
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
1495
-
}
1496
-
1497
-
#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
1498
-
#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
1499
-
1500
-
#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
1501
-
#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
1502
-
1503
-
#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
1504
-
1505
-
#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
1506
-
1507
-
#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
1508
-
1509
-
#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
1510
-
1511
-
#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
1512
-
1513
-
#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
1514
-
1515
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
1516
-
1517
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
1518
-
1519
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
1520
-
1521
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
1522
-
1523
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
1524
-
1525
-
#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
1526
-
#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
1527
-
1528
-
#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
1529
-
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
1530
-
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
1531
-
static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
1532
-
{
1533
-
return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
1534
-
}
1535
-
1536
-
static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1537
-
1538
-
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1539
-
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
1540
-
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
1541
-
static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
1542
-
{
1543
-
return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
1544
-
}
1545
-
1546
-
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1547
-
#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
1548
-
1549
-
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1550
-
1551
-
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1552
-
1553
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1554
-
1555
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1556
-
1557
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1558
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1559
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1560
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
1561
-
{
1562
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
1563
-
}
1564
-
1565
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1566
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1567
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1568
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
1569
-
{
1570
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
1571
-
}
1572
-
1573
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1574
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1575
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1576
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
1577
-
{
1578
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
1579
-
}
1580
-
1581
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1582
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1583
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1584
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
1585
-
{
1586
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
1587
-
}
1588
-
1589
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1590
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1591
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
1592
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
1593
-
{
1594
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
1595
-
}
1596
-
1597
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1598
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1599
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
1600
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
1601
-
{
1602
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
1603
-
}
1604
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1605
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
1606
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
1607
-
{
1608
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
1609
-
}
1610
-
1611
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
1612
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1613
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
1614
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
1615
-
{
1616
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
1617
-
}
1618
-
1619
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
1620
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1621
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1622
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
1623
-
{
1624
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
1625
-
}
1626
-
1627
-
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
1628
-
1629
-
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
1630
-
1631
-
static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
1632
-
1633
-
#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
1634
-
1635
-
#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
1636
-
1637
-
#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
1638
-
1639
-
#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
1640
-
1641
-
#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
1642
-
1643
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
1644
-
1645
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
1646
-
1647
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
1648
-
1649
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
1650
-
1651
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
1652
-
1653
-
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
1654
-
1655
-
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
1656
-
1657
-
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
1658
-
1659
-
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
1660
-
1661
-
#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
1662
-
1663
-
#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
1664
-
1665
-
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
1666
-
1667
-
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
1668
-
1669
-
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
1670
-
1671
-
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
1672
-
1673
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
1674
-
1675
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
1676
-
1677
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
1678
-
1679
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
1680
-
1681
-
#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
1682
-
1683
-
#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
1684
-
1685
-
#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
1686
-
1687
-
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
1688
-
1689
-
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
1690
-
1691
-
#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
1692
-
1693
-
#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
1694
-
1695
-
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
1696
-
1697
-
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
1698
-
1699
-
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
1700
-
1701
-
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
1702
-
1703
-
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
1704
-
1705
-
#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
1706
-
1707
-
#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
1708
-
1709
-
#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
1710
-
1711
-
#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
1712
-
1713
-
#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
1714
-
1715
-
#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
1716
-
1717
-
#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
1718
-
1719
-
#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
1720
-
1721
-
#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
1722
-
1723
-
#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
1724
-
1725
-
#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
1726
-
1727
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
1728
-
1729
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
1730
-
1731
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
1732
-
1733
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
1734
-
1735
-
#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
1736
-
1737
-
#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
1738
-
1739
-
#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
1740
-
1741
-
#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
1742
-
1743
-
#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
1744
-
1745
-
#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
1746
-
1747
-
#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
1748
-
1749
-
#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
1750
-
1751
-
#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
1752
-
1753
-
#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
1754
-
1755
-
#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
1756
-
1757
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
1758
-
1759
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
1760
-
1761
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
1762
-
1763
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
1764
-
1765
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
1766
-
1767
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
1768
-
1769
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
1770
-
1771
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
1772
-
1773
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
1774
-
1775
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
1776
-
1777
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
1778
-
1779
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
1780
-
1781
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
1782
-
1783
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
1784
-
1785
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
1786
-
1787
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
1788
-
1789
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
1790
-
1791
-
#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
1792
-
1793
-
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
1794
-
1795
-
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
1796
-
1797
-
static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1798
-
1799
-
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1800
-
1801
-
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1802
-
1803
-
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1804
-
1805
-
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
1806
-
1807
-
static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
1808
-
1809
-
static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
1810
-
1811
-
static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
1812
-
1813
-
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
1814
-
1815
-
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
1816
-
1817
-
static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
1818
-
1819
-
static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
1820
-
1821
-
static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
1822
-
1823
-
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
1824
-
1825
-
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
1826
-
1827
-
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
1828
-
1829
-
#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
1830
-
1831
-
#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
1832
-
1833
-
#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
1834
-
1835
-
#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
1836
-
1837
-
#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
1838
-
1839
-
#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
1840
-
1841
-
#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
1842
-
1843
-
#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
1844
-
1845
-
#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
1846
-
1847
-
#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
1848
-
1849
-
#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
1850
-
1851
-
#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
1852
-
1853
-
#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
1854
-
1855
-
#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
1856
-
1857
-
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
1858
-
1859
-
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
1860
-
1861
-
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
1862
-
1863
-
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
1864
-
1865
-
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
1866
-
1867
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
1868
-
1869
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
1870
-
1871
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
1872
-
1873
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
1874
-
1875
-
#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
1876
-
1877
-
#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
1878
-
1879
-
#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
1880
-
1881
-
#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
1882
-
1883
-
#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
1884
-
1885
-
#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
1886
-
1887
-
#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
1888
-
1889
-
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
1890
-
1891
-
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
1892
-
1893
-
#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
1894
-
1895
-
#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
1896
-
1897
-
#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
1898
-
1899
-
#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
1900
-
1901
-
#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
1902
-
1903
-
#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
1904
-
1905
-
#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
1906
-
1907
-
#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
1908
-
1909
-
#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
1910
-
1911
-
#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
1912
-
1913
-
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
1914
-
1915
-
#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
1916
-
1917
-
#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
1918
-
1919
-
#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
1920
-
1921
-
#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
1922
-
1923
-
#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
1924
-
1925
-
#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
1926
-
1927
-
#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
1928
-
1929
-
#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
1930
-
1931
-
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
1932
-
1933
-
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
1934
-
1935
-
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
1936
-
1937
-
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
1938
-
1939
-
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
1940
-
1941
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
1942
-
1943
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
1944
-
1945
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
1946
-
1947
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
1948
-
1949
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
1950
-
1951
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
1952
-
1953
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
1954
-
1955
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
1956
-
1957
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
1958
-
1959
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
1960
-
1961
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
1962
-
1963
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
1964
-
1965
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
1966
-
1967
-
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
1968
-
1969
-
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
1970
-
1971
-
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
1972
-
1973
-
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
1974
-
1975
-
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
1976
-
1977
-
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
1978
-
1979
-
#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
1980
-
1981
-
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
1982
-
1983
-
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
1984
-
1985
-
#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
1986
-
1987
-
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
1988
-
1989
-
#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
1990
-
1991
-
#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
1992
-
1993
-
#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
1994
-
1995
-
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
1996
-
1997
-
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
1998
-
1999
-
static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
2000
-
2001
-
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
2002
-
2003
-
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
2004
-
2005
-
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
2006
-
2007
-
static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
2008
-
2009
-
static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
2010
-
2011
-
static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
2012
-
2013
-
static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
2014
-
2015
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
2016
-
2017
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
2018
-
2019
-
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
2020
-
2021
-
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
2022
-
2023
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
2024
-
2025
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
2026
-
2027
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
2028
-
2029
-
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
2030
-
2031
-
#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
2032
-
2033
-
#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
2034
-
2035
-
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
2036
-
2037
-
#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
2038
-
2039
-
#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
2040
-
2041
-
#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
2042
-
2043
-
#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
2044
-
2045
-
#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
2046
-
2047
-
#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
2048
-
2049
-
#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
2050
-
2051
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
2052
-
2053
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
2054
-
2055
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
2056
-
2057
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
2058
-
2059
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
2060
-
2061
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
2062
-
2063
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
2064
-
2065
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
2066
-
2067
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
2068
-
2069
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
2070
-
2071
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
2072
-
2073
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
2074
-
2075
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
2076
-
2077
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
2078
-
2079
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
2080
-
2081
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
2082
-
2083
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
2084
-
2085
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
2086
-
2087
-
#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
2088
-
2089
-
#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
2090
-
2091
-
#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
2092
-
2093
-
#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
2094
-
2095
-
#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
2096
-
2097
-
#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
2098
-
2099
-
#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
2100
-
2101
-
#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
2102
-
2103
-
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
2104
-
2105
-
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
2106
-
2107
-
#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
2108
-
2109
-
#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
2110
-
2111
-
#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
2112
-
2113
-
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
2114
-
2115
-
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
2116
-
2117
-
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
2118
-
2119
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
2120
-
2121
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
2122
-
2123
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
2124
-
2125
-
#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
2126
-
2127
-
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
2128
-
2129
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
2130
-
2131
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
2132
-
2133
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
2134
-
2135
-
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
2136
-
2137
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
2138
-
2139
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
2140
-
2141
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
2142
-
2143
-
#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
2144
-
2145
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
2146
-
2147
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
2148
-
2149
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
2150
-
2151
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
2152
-
2153
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
2154
-
2155
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
2156
-
2157
-
#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
2158
-
2159
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
2160
-
2161
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
2162
-
2163
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
2164
-
2165
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
2166
-
2167
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
2168
-
2169
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
2170
-
2171
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
2172
-
2173
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
2174
-
2175
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
2176
-
2177
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
2178
-
2179
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
2180
-
2181
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
2182
-
2183
-
#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
2184
-
2185
-
#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
2186
-
2187
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
2188
-
2189
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
2190
-
2191
-
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
2192
-
2193
-
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
2194
-
2195
-
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
2196
-
2197
-
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
2198
-
2199
-
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
2200
-
2201
-
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
2202
-
2203
-
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
2204
-
2205
-
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
2206
-
2207
-
#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
2208
-
2209
-
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
2210
-
2211
-
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
2212
-
2213
-
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
2214
-
2215
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
2216
-
2217
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
2218
-
2219
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
2220
-
2221
-
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
2222
-
2223
-
#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
2224
-
2225
-
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
2226
-
2227
-
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
2228
-
2229
-
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
2230
-
2231
-
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
2232
-
2233
-
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
2234
-
2235
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
2236
-
2237
-
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
2238
-
2239
-
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
2240
-
2241
-
#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
2242
-
2243
-
#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
2244
-
2245
-
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
2246
-
2247
-
#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
2248
-
2249
-
#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
2250
-
2251
-
#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
2252
-
2253
-
#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
2254
-
2255
-
#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
2256
-
2257
-
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
2258
-
2259
-
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
2260
-
2261
-
#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
2262
-
2263
-
#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
2264
-
2265
-
#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
2266
-
2267
-
#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
2268
-
2269
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
2270
-
2271
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
2272
-
2273
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
2274
-
2275
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
2276
-
2277
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
2278
-
2279
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
2280
-
2281
-
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
2282
-
2283
-
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
2284
-
2285
-
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
2286
-
2287
-
#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
2288
-
2289
-
#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
2290
-
2291
-
#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
2292
-
2293
-
#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
2294
-
2295
-
#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
2296
-
2297
-
#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
2298
-
2299
-
#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
2300
-
2301
-
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
2302
-
2303
-
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
2304
-
2305
-
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
2306
-
2307
-
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
2308
-
2309
-
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
2310
-
2311
-
#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
2312
-
2313
-
#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
2314
-
2315
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
2316
-
2317
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
2318
-
2319
-
#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
2320
626
2321
627
#endif /* DSI_XML */
+19
-11
drivers/gpu/drm/msm/dsi/dsi_host.c
+19
-11
drivers/gpu/drm/msm/dsi/dsi_host.c
···
102
102
int id;
103
103
104
104
void __iomem *ctrl_base;
105
+
phys_addr_t ctrl_size;
105
106
struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
106
107
107
108
struct clk *bus_clks[DSI_BUS_CLK_MAX];
···
113
112
struct clk *byte_clk_src;
114
113
struct clk *pixel_clk_src;
115
114
struct clk *byte_intf_clk;
116
-
117
-
struct opp_table *opp_table;
118
115
119
116
u32 byte_clk_rate;
120
117
u32 pixel_clk_rate;
···
1091
1092
uint64_t iova;
1092
1093
u8 *data;
1093
1094
1094
-
data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
1095
+
data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1095
1096
priv->kms->aspace,
1096
1097
&msm_host->tx_gem_obj, &iova);
1097
1098
···
1838
1839
goto fail;
1839
1840
}
1840
1841
1841
-
msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1842
+
msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size);
1842
1843
if (IS_ERR(msm_host->ctrl_base)) {
1843
1844
pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1844
1845
ret = PTR_ERR(msm_host->ctrl_base);
···
1883
1884
goto fail;
1884
1885
}
1885
1886
1886
-
msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte");
1887
-
if (IS_ERR(msm_host->opp_table))
1888
-
return PTR_ERR(msm_host->opp_table);
1887
+
ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1888
+
if (ret)
1889
+
return ret;
1889
1890
/* OPP table is optional */
1890
-
ret = dev_pm_opp_of_add_table(&pdev->dev);
1891
+
ret = devm_pm_opp_of_add_table(&pdev->dev);
1891
1892
if (ret && ret != -ENODEV) {
1892
1893
dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1893
-
dev_pm_opp_put_clkname(msm_host->opp_table);
1894
1894
return ret;
1895
1895
}
1896
1896
···
1928
1930
mutex_destroy(&msm_host->cmd_mutex);
1929
1931
mutex_destroy(&msm_host->dev_mutex);
1930
1932
1931
-
dev_pm_opp_of_remove_table(&msm_host->pdev->dev);
1932
-
dev_pm_opp_put_clkname(msm_host->opp_table);
1933
1933
pm_runtime_disable(&msm_host->pdev->dev);
1934
1934
}
1935
1935
···
2482
2486
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2483
2487
2484
2488
return of_drm_find_bridge(msm_host->device_node);
2489
+
}
2490
+
2491
+
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2492
+
{
2493
+
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2494
+
2495
+
pm_runtime_get_sync(&msm_host->pdev->dev);
2496
+
2497
+
msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2498
+
msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2499
+
2500
+
pm_runtime_put_sync(&msm_host->pdev->dev);
2485
2501
}
+6
-6
drivers/gpu/drm/msm/dsi/dsi_manager.c
+6
-6
drivers/gpu/drm/msm/dsi/dsi_manager.c
···
373
373
if (!msm_dsi_device_connected(msm_dsi))
374
374
return;
375
375
376
-
ret = dsi_mgr_phy_enable(id, phy_shared_timings);
377
-
if (ret)
378
-
goto phy_en_fail;
379
-
380
376
/* Do nothing with the host if it is slave-DSI in case of dual DSI */
381
377
if (is_dual_dsi && !IS_MASTER_DSI_LINK(id))
382
378
return;
379
+
380
+
ret = dsi_mgr_phy_enable(id, phy_shared_timings);
381
+
if (ret)
382
+
goto phy_en_fail;
383
383
384
384
ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi);
385
385
if (ret) {
···
817
817
818
818
ret = dsi_mgr_setup_components(id);
819
819
if (ret) {
820
-
pr_err("%s: failed to register mipi dsi host for DSI %d\n",
821
-
__func__, id);
820
+
pr_err("%s: failed to register mipi dsi host for DSI %d: %d\n",
821
+
__func__, id, ret);
822
822
goto fail;
823
823
}
824
824
+228
drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
+228
drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
···
1
+
#ifndef DSI_PHY_10NM_XML
2
+
#define DSI_PHY_10NM_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
58
+
59
+
#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
60
+
61
+
#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
62
+
63
+
#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
64
+
65
+
#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
66
+
67
+
#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
68
+
69
+
#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
70
+
71
+
#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
72
+
73
+
#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
74
+
75
+
#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
76
+
77
+
#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
78
+
79
+
#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
80
+
81
+
#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
82
+
83
+
#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
84
+
85
+
#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
86
+
87
+
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
88
+
89
+
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
90
+
91
+
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
92
+
93
+
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
94
+
95
+
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
96
+
97
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
98
+
99
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
100
+
101
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
102
+
103
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
104
+
105
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
106
+
107
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
108
+
109
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
110
+
111
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
112
+
113
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
114
+
115
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
116
+
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+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
118
+
119
+
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
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+
121
+
#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
122
+
123
+
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
124
+
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+
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
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+
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+
static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
128
+
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+
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
130
+
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+
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
132
+
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+
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
134
+
135
+
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
136
+
137
+
static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
138
+
139
+
static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
140
+
141
+
static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
142
+
143
+
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
144
+
145
+
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
146
+
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+
static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
148
+
149
+
static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
150
+
151
+
static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
152
+
153
+
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
154
+
155
+
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
156
+
157
+
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
158
+
159
+
#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
160
+
161
+
#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
162
+
163
+
#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
164
+
165
+
#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
166
+
167
+
#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
168
+
169
+
#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
170
+
171
+
#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
172
+
173
+
#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
174
+
175
+
#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
176
+
177
+
#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
178
+
179
+
#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
180
+
181
+
#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
182
+
183
+
#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
184
+
185
+
#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
186
+
187
+
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
188
+
189
+
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
190
+
191
+
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
192
+
193
+
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
194
+
195
+
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
196
+
197
+
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
198
+
199
+
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
200
+
201
+
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
202
+
203
+
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
204
+
205
+
#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
206
+
207
+
#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
208
+
209
+
#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
210
+
211
+
#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
212
+
213
+
#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
214
+
215
+
#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
216
+
217
+
#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
218
+
219
+
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
220
+
221
+
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
222
+
223
+
#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
224
+
225
+
#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
226
+
227
+
228
+
#endif /* DSI_PHY_10NM_XML */
+310
drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
+310
drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
···
1
+
#ifndef DSI_PHY_14NM_XML
2
+
#define DSI_PHY_14NM_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58
+
59
+
#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60
+
61
+
#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62
+
63
+
#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64
+
65
+
#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
66
+
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
67
+
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
68
+
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
69
+
{
70
+
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
71
+
}
72
+
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
73
+
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
74
+
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
75
+
{
76
+
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
77
+
}
78
+
79
+
#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
80
+
#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81
+
82
+
#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
83
+
#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
84
+
85
+
#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
86
+
87
+
#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
88
+
89
+
#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
90
+
91
+
#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
92
+
93
+
#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
94
+
95
+
#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
96
+
97
+
#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
98
+
99
+
#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
100
+
101
+
#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
102
+
103
+
#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
104
+
105
+
#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
106
+
107
+
#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
108
+
#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
109
+
110
+
#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
111
+
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
112
+
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
113
+
static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
114
+
{
115
+
return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
116
+
}
117
+
118
+
static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
119
+
120
+
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
121
+
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
122
+
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
123
+
static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
124
+
{
125
+
return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
126
+
}
127
+
128
+
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
129
+
#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
130
+
131
+
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
132
+
133
+
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
134
+
135
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
136
+
137
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
138
+
139
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
140
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
141
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
142
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
143
+
{
144
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
145
+
}
146
+
147
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
148
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
149
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
150
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
151
+
{
152
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
153
+
}
154
+
155
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
156
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
157
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
158
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
159
+
{
160
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
161
+
}
162
+
163
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
164
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
165
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
166
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
167
+
{
168
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
169
+
}
170
+
171
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
172
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
173
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
174
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
175
+
{
176
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
177
+
}
178
+
179
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
180
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
181
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
182
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
183
+
{
184
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
185
+
}
186
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
187
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
188
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
189
+
{
190
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
191
+
}
192
+
193
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
194
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
195
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
196
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
197
+
{
198
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
199
+
}
200
+
201
+
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
202
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
203
+
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
204
+
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
205
+
{
206
+
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
207
+
}
208
+
209
+
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
210
+
211
+
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
212
+
213
+
static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
214
+
215
+
#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
216
+
217
+
#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
218
+
219
+
#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
220
+
221
+
#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
222
+
223
+
#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
224
+
225
+
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
226
+
227
+
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
228
+
229
+
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
230
+
231
+
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
232
+
233
+
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
234
+
235
+
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
236
+
237
+
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
238
+
239
+
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
240
+
241
+
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
242
+
243
+
#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
244
+
245
+
#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
246
+
247
+
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
248
+
249
+
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
250
+
251
+
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
252
+
253
+
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
254
+
255
+
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
256
+
257
+
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
258
+
259
+
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
260
+
261
+
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
262
+
263
+
#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
264
+
265
+
#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
266
+
267
+
#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
268
+
269
+
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
270
+
271
+
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
272
+
273
+
#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
274
+
275
+
#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
276
+
277
+
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
278
+
279
+
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
280
+
281
+
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
282
+
283
+
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
284
+
285
+
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
286
+
287
+
#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
288
+
289
+
#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
290
+
291
+
#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
292
+
293
+
#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
294
+
295
+
#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
296
+
297
+
#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
298
+
299
+
#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
300
+
301
+
#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
302
+
303
+
#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
304
+
305
+
#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
306
+
307
+
#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
308
+
309
+
310
+
#endif /* DSI_PHY_14NM_XML */
+238
drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
+238
drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
···
1
+
#ifndef DSI_PHY_20NM_XML
2
+
#define DSI_PHY_20NM_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58
+
59
+
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60
+
61
+
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62
+
63
+
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64
+
65
+
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
66
+
67
+
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
68
+
69
+
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
70
+
71
+
static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
72
+
73
+
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
74
+
75
+
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
76
+
77
+
#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
78
+
79
+
#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
80
+
81
+
#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
82
+
83
+
#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
84
+
85
+
#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
86
+
87
+
#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
88
+
89
+
#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
90
+
91
+
#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
92
+
93
+
#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
94
+
95
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
96
+
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
97
+
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
98
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
99
+
{
100
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
101
+
}
102
+
103
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
104
+
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
105
+
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
106
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
107
+
{
108
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
109
+
}
110
+
111
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
112
+
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
113
+
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
114
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
115
+
{
116
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
117
+
}
118
+
119
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
120
+
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
121
+
122
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
123
+
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
124
+
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
125
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
126
+
{
127
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
128
+
}
129
+
130
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
131
+
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
132
+
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
133
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
134
+
{
135
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
136
+
}
137
+
138
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
139
+
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
140
+
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
141
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
142
+
{
143
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
144
+
}
145
+
146
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
147
+
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
148
+
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
149
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
150
+
{
151
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
152
+
}
153
+
154
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
155
+
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
156
+
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
157
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
158
+
{
159
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
160
+
}
161
+
162
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
163
+
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
164
+
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
165
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
166
+
{
167
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
168
+
}
169
+
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
170
+
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
171
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
172
+
{
173
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
174
+
}
175
+
176
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
177
+
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
178
+
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
179
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
180
+
{
181
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
182
+
}
183
+
184
+
#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
185
+
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
186
+
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
187
+
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
188
+
{
189
+
return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
190
+
}
191
+
192
+
#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
193
+
194
+
#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
195
+
196
+
#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
197
+
198
+
#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
199
+
200
+
#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
201
+
202
+
#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
203
+
204
+
#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
205
+
206
+
#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
207
+
208
+
#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
209
+
210
+
#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
211
+
212
+
#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
213
+
214
+
#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
215
+
216
+
#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
217
+
218
+
#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
219
+
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
220
+
221
+
#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
222
+
223
+
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
224
+
225
+
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
226
+
227
+
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
228
+
229
+
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
230
+
231
+
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
232
+
233
+
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
234
+
235
+
#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
236
+
237
+
238
+
#endif /* DSI_PHY_20NM_XML */
+385
drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
+385
drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
···
1
+
#ifndef DSI_PHY_28NM_XML
2
+
#define DSI_PHY_28NM_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58
+
59
+
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60
+
61
+
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62
+
63
+
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64
+
65
+
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
66
+
67
+
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
68
+
69
+
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
70
+
71
+
static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
72
+
73
+
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
74
+
75
+
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
76
+
77
+
#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
78
+
79
+
#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
80
+
81
+
#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
82
+
83
+
#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
84
+
85
+
#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
86
+
87
+
#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
88
+
89
+
#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
90
+
91
+
#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
92
+
93
+
#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
94
+
95
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
96
+
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
97
+
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
98
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
99
+
{
100
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
101
+
}
102
+
103
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
104
+
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
105
+
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
106
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
107
+
{
108
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
109
+
}
110
+
111
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
112
+
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
113
+
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
114
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
115
+
{
116
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
117
+
}
118
+
119
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
120
+
#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
121
+
122
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
123
+
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
124
+
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
125
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
126
+
{
127
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
128
+
}
129
+
130
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
131
+
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
132
+
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
133
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
134
+
{
135
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
136
+
}
137
+
138
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
139
+
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
140
+
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
141
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
142
+
{
143
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
144
+
}
145
+
146
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
147
+
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
148
+
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
149
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
150
+
{
151
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
152
+
}
153
+
154
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
155
+
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
156
+
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
157
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
158
+
{
159
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
160
+
}
161
+
162
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
163
+
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
164
+
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
165
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
166
+
{
167
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
168
+
}
169
+
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
170
+
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
171
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
172
+
{
173
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
174
+
}
175
+
176
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
177
+
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
178
+
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
179
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
180
+
{
181
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
182
+
}
183
+
184
+
#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
185
+
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
186
+
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
187
+
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
188
+
{
189
+
return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
190
+
}
191
+
192
+
#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
193
+
194
+
#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
195
+
196
+
#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
197
+
198
+
#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
199
+
200
+
#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
201
+
202
+
#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
203
+
204
+
#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
205
+
206
+
#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
207
+
208
+
#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
209
+
210
+
#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
211
+
212
+
#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
213
+
214
+
#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
215
+
216
+
#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
217
+
218
+
#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
219
+
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
220
+
221
+
#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
222
+
223
+
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
224
+
225
+
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
226
+
227
+
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
228
+
229
+
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
230
+
231
+
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
232
+
233
+
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
234
+
235
+
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
236
+
237
+
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
238
+
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
239
+
240
+
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
241
+
242
+
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
243
+
244
+
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
245
+
246
+
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
247
+
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
248
+
249
+
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
250
+
251
+
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
252
+
253
+
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
254
+
255
+
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
256
+
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
257
+
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
258
+
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
259
+
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
260
+
261
+
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
262
+
263
+
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
264
+
265
+
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
266
+
267
+
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
268
+
269
+
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
270
+
271
+
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
272
+
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
273
+
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
274
+
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
275
+
{
276
+
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
277
+
}
278
+
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
279
+
280
+
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
281
+
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
282
+
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
283
+
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
284
+
{
285
+
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
286
+
}
287
+
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
288
+
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
289
+
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
290
+
{
291
+
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
292
+
}
293
+
294
+
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
295
+
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
296
+
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
297
+
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
298
+
{
299
+
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
300
+
}
301
+
302
+
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
303
+
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
304
+
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
305
+
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
306
+
{
307
+
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
308
+
}
309
+
310
+
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
311
+
312
+
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
313
+
314
+
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
315
+
316
+
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
317
+
318
+
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
319
+
320
+
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
321
+
322
+
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
323
+
324
+
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
325
+
326
+
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
327
+
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
328
+
329
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
330
+
331
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
332
+
333
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
334
+
335
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
336
+
337
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
338
+
339
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
340
+
341
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
342
+
343
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
344
+
345
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
346
+
347
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
348
+
349
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
350
+
351
+
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
352
+
353
+
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
354
+
355
+
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
356
+
357
+
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
358
+
359
+
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
360
+
361
+
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
362
+
363
+
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
364
+
365
+
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
366
+
367
+
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
368
+
369
+
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
370
+
371
+
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
372
+
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
373
+
374
+
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
375
+
376
+
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
377
+
378
+
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
379
+
380
+
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
381
+
382
+
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
383
+
384
+
385
+
#endif /* DSI_PHY_28NM_XML */
+287
drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
+287
drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
···
1
+
#ifndef DSI_PHY_28NM_8960_XML
2
+
#define DSI_PHY_28NM_8960_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58
+
59
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60
+
61
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62
+
63
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64
+
65
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
66
+
67
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
68
+
69
+
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
70
+
71
+
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72
+
73
+
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74
+
75
+
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
76
+
77
+
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
78
+
79
+
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
80
+
81
+
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
82
+
83
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
84
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
85
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
86
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
87
+
{
88
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
89
+
}
90
+
91
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
92
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
93
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
94
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
95
+
{
96
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
97
+
}
98
+
99
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
100
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
101
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
102
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
103
+
{
104
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
105
+
}
106
+
107
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
108
+
109
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
110
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
111
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
112
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
113
+
{
114
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
115
+
}
116
+
117
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
118
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
119
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
120
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
121
+
{
122
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
123
+
}
124
+
125
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
126
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
127
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
128
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
129
+
{
130
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
131
+
}
132
+
133
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
134
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
135
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
136
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
137
+
{
138
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
139
+
}
140
+
141
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
142
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
143
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
144
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
145
+
{
146
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
147
+
}
148
+
149
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
150
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
151
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
152
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
153
+
{
154
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
155
+
}
156
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
157
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
158
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
159
+
{
160
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
161
+
}
162
+
163
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
164
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
165
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
166
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
167
+
{
168
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
169
+
}
170
+
171
+
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
172
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
173
+
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
174
+
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
175
+
{
176
+
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
177
+
}
178
+
179
+
#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
180
+
181
+
#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
182
+
183
+
#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
184
+
185
+
#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
186
+
187
+
#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
188
+
189
+
#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
190
+
191
+
#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
192
+
193
+
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
194
+
195
+
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
196
+
197
+
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
198
+
199
+
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
200
+
201
+
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
202
+
203
+
#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
204
+
205
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
206
+
207
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
208
+
209
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
210
+
211
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
212
+
213
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
214
+
215
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
216
+
217
+
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
218
+
219
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
220
+
221
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
222
+
223
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
224
+
225
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
226
+
227
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
228
+
229
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
230
+
231
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
232
+
233
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
234
+
235
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
236
+
237
+
#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
238
+
#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
239
+
240
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
241
+
#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
242
+
243
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
244
+
245
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
246
+
247
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
248
+
249
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
250
+
251
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
252
+
253
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
254
+
255
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
256
+
257
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
258
+
259
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
260
+
261
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
262
+
263
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
264
+
265
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
266
+
267
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
268
+
269
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
270
+
271
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
272
+
273
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
274
+
275
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
276
+
277
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
278
+
279
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
280
+
281
+
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
282
+
283
+
#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
284
+
#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
285
+
286
+
287
+
#endif /* DSI_PHY_28NM_8960_XML */
+480
drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h
+480
drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h
···
1
+
#ifndef DSI_PHY_5NM_XML
2
+
#define DSI_PHY_5NM_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
#define REG_DSI_5nm_PHY_CMN_REVISION_ID0 0x00000000
58
+
59
+
#define REG_DSI_5nm_PHY_CMN_REVISION_ID1 0x00000004
60
+
61
+
#define REG_DSI_5nm_PHY_CMN_REVISION_ID2 0x00000008
62
+
63
+
#define REG_DSI_5nm_PHY_CMN_REVISION_ID3 0x0000000c
64
+
65
+
#define REG_DSI_5nm_PHY_CMN_CLK_CFG0 0x00000010
66
+
67
+
#define REG_DSI_5nm_PHY_CMN_CLK_CFG1 0x00000014
68
+
69
+
#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL 0x00000018
70
+
71
+
#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL 0x0000001c
72
+
73
+
#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0 0x00000020
74
+
75
+
#define REG_DSI_5nm_PHY_CMN_CTRL_0 0x00000024
76
+
77
+
#define REG_DSI_5nm_PHY_CMN_CTRL_1 0x00000028
78
+
79
+
#define REG_DSI_5nm_PHY_CMN_CTRL_2 0x0000002c
80
+
81
+
#define REG_DSI_5nm_PHY_CMN_CTRL_3 0x00000030
82
+
83
+
#define REG_DSI_5nm_PHY_CMN_LANE_CFG0 0x00000034
84
+
85
+
#define REG_DSI_5nm_PHY_CMN_LANE_CFG1 0x00000038
86
+
87
+
#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL 0x0000003c
88
+
89
+
#define REG_DSI_5nm_PHY_CMN_DPHY_SOT 0x00000040
90
+
91
+
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0 0x000000a0
92
+
93
+
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1 0x000000a4
94
+
95
+
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2 0x000000a8
96
+
97
+
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3 0x000000ac
98
+
99
+
#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4 0x000000b0
100
+
101
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
102
+
103
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
104
+
105
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
106
+
107
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
108
+
109
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
110
+
111
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
112
+
113
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
114
+
115
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
116
+
117
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
118
+
119
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
120
+
121
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
122
+
123
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
124
+
125
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
126
+
127
+
#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
128
+
129
+
#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
130
+
131
+
#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
132
+
133
+
#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
134
+
135
+
#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
136
+
137
+
#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
138
+
139
+
#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
140
+
141
+
#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
142
+
143
+
#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
144
+
145
+
#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
146
+
147
+
#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1 0x00000110
148
+
149
+
#define REG_DSI_5nm_PHY_CMN_CTRL_4 0x00000114
150
+
151
+
#define REG_DSI_5nm_PHY_CMN_PHY_STATUS 0x00000140
152
+
153
+
#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0 0x00000148
154
+
155
+
#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1 0x0000014c
156
+
157
+
static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
158
+
159
+
static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
160
+
161
+
static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
162
+
163
+
static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
164
+
165
+
static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
166
+
167
+
static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
168
+
169
+
static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
170
+
171
+
static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
172
+
173
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
174
+
175
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
176
+
177
+
#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
178
+
179
+
#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
180
+
181
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
182
+
183
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
184
+
185
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
186
+
187
+
#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
188
+
189
+
#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER 0x00000020
190
+
191
+
#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
192
+
193
+
#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES 0x00000028
194
+
195
+
#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
196
+
197
+
#define REG_DSI_5nm_PHY_PLL_CMODE 0x00000030
198
+
199
+
#define REG_DSI_5nm_PHY_PLL_PSM_CTRL 0x00000034
200
+
201
+
#define REG_DSI_5nm_PHY_PLL_RSM_CTRL 0x00000038
202
+
203
+
#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
204
+
205
+
#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL 0x00000040
206
+
207
+
#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
208
+
209
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
210
+
211
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
212
+
213
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
214
+
215
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN 0x00000054
216
+
217
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX 0x00000058
218
+
219
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
220
+
221
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
222
+
223
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
224
+
225
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
226
+
227
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
228
+
229
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
230
+
231
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
232
+
233
+
#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
234
+
235
+
#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
236
+
237
+
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
238
+
239
+
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
240
+
241
+
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
242
+
243
+
#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
244
+
245
+
#define REG_DSI_5nm_PHY_PLL_PFILT 0x00000090
246
+
247
+
#define REG_DSI_5nm_PHY_PLL_IFILT 0x00000094
248
+
249
+
#define REG_DSI_5nm_PHY_PLL_PLL_GAIN 0x00000098
250
+
251
+
#define REG_DSI_5nm_PHY_PLL_ICODE_LOW 0x0000009c
252
+
253
+
#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH 0x000000a0
254
+
255
+
#define REG_DSI_5nm_PHY_PLL_LOCKDET 0x000000a4
256
+
257
+
#define REG_DSI_5nm_PHY_PLL_OUTDIV 0x000000a8
258
+
259
+
#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
260
+
261
+
#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
262
+
263
+
#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
264
+
265
+
#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
266
+
267
+
#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
268
+
269
+
#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE 0x000000c0
270
+
271
+
#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
272
+
273
+
#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
274
+
275
+
#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
276
+
277
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
278
+
279
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
280
+
281
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
282
+
283
+
#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
284
+
285
+
#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
286
+
287
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
288
+
289
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
290
+
291
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
292
+
293
+
#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
294
+
295
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
296
+
297
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
298
+
299
+
#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
300
+
301
+
#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL 0x00000100
302
+
303
+
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
304
+
305
+
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
306
+
307
+
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
308
+
309
+
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
310
+
311
+
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
312
+
313
+
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
314
+
315
+
#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
316
+
317
+
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
318
+
319
+
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
320
+
321
+
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
322
+
323
+
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
324
+
325
+
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
326
+
327
+
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
328
+
329
+
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
330
+
331
+
#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
332
+
333
+
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
334
+
335
+
#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
336
+
337
+
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
338
+
339
+
#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
340
+
341
+
#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL 0x00000150
342
+
343
+
#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
344
+
345
+
#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
346
+
347
+
#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
348
+
349
+
#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
350
+
351
+
#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
352
+
353
+
#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
354
+
355
+
#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
356
+
357
+
#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
358
+
359
+
#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
360
+
361
+
#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
362
+
363
+
#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
364
+
365
+
#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
366
+
367
+
#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
368
+
369
+
#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
370
+
371
+
#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
372
+
373
+
#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
374
+
375
+
#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
376
+
377
+
#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
378
+
379
+
#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
380
+
381
+
#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
382
+
383
+
#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
384
+
385
+
#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
386
+
387
+
#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
388
+
389
+
#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
390
+
391
+
#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
392
+
393
+
#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
394
+
395
+
#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
396
+
397
+
#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
398
+
399
+
#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW 0x000001c4
400
+
401
+
#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
402
+
403
+
#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
404
+
405
+
#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
406
+
407
+
#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG 0x000001d4
408
+
409
+
#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
410
+
411
+
#define REG_DSI_5nm_PHY_PLL_FLL_CODE0 0x000001dc
412
+
413
+
#define REG_DSI_5nm_PHY_PLL_FLL_CODE1 0x000001e0
414
+
415
+
#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0 0x000001e4
416
+
417
+
#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1 0x000001e8
418
+
419
+
#define REG_DSI_5nm_PHY_PLL_SW_RESET 0x000001ec
420
+
421
+
#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP 0x000001f0
422
+
423
+
#define REG_DSI_5nm_PHY_PLL_LOCKTIME0 0x000001f4
424
+
425
+
#define REG_DSI_5nm_PHY_PLL_LOCKTIME1 0x000001f8
426
+
427
+
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
428
+
429
+
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0 0x00000200
430
+
431
+
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1 0x00000204
432
+
433
+
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2 0x00000208
434
+
435
+
#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3 0x0000020c
436
+
437
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
438
+
439
+
#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG 0x00000214
440
+
441
+
#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
442
+
443
+
#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
444
+
445
+
#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS 0x00000220
446
+
447
+
#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET 0x00000224
448
+
449
+
#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
450
+
451
+
#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
452
+
453
+
#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
454
+
455
+
#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
456
+
457
+
#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
458
+
459
+
#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
460
+
461
+
#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1 0x00000240
462
+
463
+
#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2 0x00000244
464
+
465
+
#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
466
+
467
+
#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
468
+
469
+
#define REG_DSI_5nm_PHY_PLL_CMODE_1 0x00000250
470
+
471
+
#define REG_DSI_5nm_PHY_PLL_CMODE_2 0x00000254
472
+
473
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
474
+
475
+
#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
476
+
477
+
#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
478
+
479
+
480
+
#endif /* DSI_PHY_5NM_XML */
+482
drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
+482
drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
···
1
+
#ifndef DSI_PHY_7NM_XML
2
+
#define DSI_PHY_7NM_XML
3
+
4
+
/* Autogenerated file, DO NOT EDIT manually!
5
+
6
+
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
+
http://github.com/freedreno/envytools/
8
+
git clone https://github.com/freedreno/envytools.git
9
+
10
+
The rules-ng-ng source files this header was generated from are:
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
+
31
+
Copyright (C) 2013-2021 by the following authors:
32
+
- Rob Clark <robdclark@gmail.com> (robclark)
33
+
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
+
35
+
Permission is hereby granted, free of charge, to any person obtaining
36
+
a copy of this software and associated documentation files (the
37
+
"Software"), to deal in the Software without restriction, including
38
+
without limitation the rights to use, copy, modify, merge, publish,
39
+
distribute, sublicense, and/or sell copies of the Software, and to
40
+
permit persons to whom the Software is furnished to do so, subject to
41
+
the following conditions:
42
+
43
+
The above copyright notice and this permission notice (including the
44
+
next paragraph) shall be included in all copies or substantial
45
+
portions of the Software.
46
+
47
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48
+
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50
+
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51
+
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52
+
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53
+
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54
+
*/
55
+
56
+
57
+
#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58
+
59
+
#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60
+
61
+
#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62
+
63
+
#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64
+
65
+
#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66
+
67
+
#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68
+
69
+
#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70
+
71
+
#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72
+
73
+
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74
+
75
+
#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
76
+
77
+
#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
78
+
79
+
#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
80
+
81
+
#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
82
+
83
+
#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
84
+
85
+
#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
86
+
87
+
#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
88
+
89
+
#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
90
+
91
+
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
92
+
93
+
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
94
+
95
+
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
96
+
97
+
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
98
+
99
+
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
100
+
101
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
102
+
103
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
104
+
105
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
106
+
107
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
108
+
109
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
110
+
111
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
112
+
113
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
114
+
115
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
116
+
117
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
118
+
119
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
120
+
121
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
122
+
123
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
124
+
125
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
126
+
127
+
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
128
+
129
+
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
130
+
131
+
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
132
+
133
+
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
134
+
135
+
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
136
+
137
+
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
138
+
139
+
#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
140
+
141
+
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
142
+
143
+
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
144
+
145
+
#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
146
+
147
+
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
148
+
149
+
#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
150
+
151
+
#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
152
+
153
+
#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
154
+
155
+
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
156
+
157
+
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
158
+
159
+
static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
160
+
161
+
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
162
+
163
+
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
164
+
165
+
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
166
+
167
+
static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
168
+
169
+
static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
170
+
171
+
static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
172
+
173
+
static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
174
+
175
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
176
+
177
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
178
+
179
+
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
180
+
181
+
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
182
+
183
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
184
+
185
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
186
+
187
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
188
+
189
+
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
190
+
191
+
#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
192
+
193
+
#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
194
+
195
+
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
196
+
197
+
#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
198
+
199
+
#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
200
+
201
+
#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
202
+
203
+
#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
204
+
205
+
#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
206
+
207
+
#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
208
+
209
+
#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
210
+
211
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
212
+
213
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
214
+
215
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
216
+
217
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
218
+
219
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
220
+
221
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
222
+
223
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
224
+
225
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
226
+
227
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
228
+
229
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
230
+
231
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
232
+
233
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
234
+
235
+
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
236
+
237
+
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
238
+
239
+
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
240
+
241
+
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
242
+
243
+
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
244
+
245
+
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
246
+
247
+
#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
248
+
249
+
#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
250
+
251
+
#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
252
+
253
+
#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
254
+
255
+
#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
256
+
257
+
#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
258
+
259
+
#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
260
+
261
+
#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
262
+
263
+
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
264
+
265
+
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
266
+
267
+
#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
268
+
269
+
#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
270
+
271
+
#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
272
+
273
+
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
274
+
275
+
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
276
+
277
+
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
278
+
279
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
280
+
281
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
282
+
283
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
284
+
285
+
#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
286
+
287
+
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
288
+
289
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
290
+
291
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
292
+
293
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
294
+
295
+
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
296
+
297
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
298
+
299
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
300
+
301
+
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
302
+
303
+
#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
304
+
305
+
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
306
+
307
+
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
308
+
309
+
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
310
+
311
+
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
312
+
313
+
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
314
+
315
+
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
316
+
317
+
#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
318
+
319
+
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
320
+
321
+
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
322
+
323
+
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
324
+
325
+
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
326
+
327
+
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
328
+
329
+
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
330
+
331
+
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
332
+
333
+
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
334
+
335
+
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
336
+
337
+
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
338
+
339
+
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
340
+
341
+
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
342
+
343
+
#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
344
+
345
+
#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
346
+
347
+
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
348
+
349
+
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
350
+
351
+
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
352
+
353
+
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
354
+
355
+
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
356
+
357
+
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
358
+
359
+
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
360
+
361
+
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
362
+
363
+
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
364
+
365
+
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
366
+
367
+
#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
368
+
369
+
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
370
+
371
+
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
372
+
373
+
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
374
+
375
+
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
376
+
377
+
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
378
+
379
+
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
380
+
381
+
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
382
+
383
+
#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
384
+
385
+
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
386
+
387
+
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
388
+
389
+
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
390
+
391
+
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
392
+
393
+
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
394
+
395
+
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
396
+
397
+
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
398
+
399
+
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
400
+
401
+
#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
402
+
403
+
#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
404
+
405
+
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
406
+
407
+
#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
408
+
409
+
#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
410
+
411
+
#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
412
+
413
+
#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
414
+
415
+
#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
416
+
417
+
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
418
+
419
+
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
420
+
421
+
#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
422
+
423
+
#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
424
+
425
+
#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
426
+
427
+
#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
428
+
429
+
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
430
+
431
+
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
432
+
433
+
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
434
+
435
+
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
436
+
437
+
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
438
+
439
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
440
+
441
+
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
442
+
443
+
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
444
+
445
+
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
446
+
447
+
#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
448
+
449
+
#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
450
+
451
+
#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
452
+
453
+
#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
454
+
455
+
#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
456
+
457
+
#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
458
+
459
+
#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
460
+
461
+
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
462
+
463
+
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
464
+
465
+
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
466
+
467
+
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
468
+
469
+
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
470
+
471
+
#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
472
+
473
+
#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
474
+
475
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
476
+
477
+
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
478
+
479
+
#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
480
+
481
+
482
+
#endif /* DSI_PHY_7NM_XML */
+20
-12
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+20
-12
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+27
-4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+27
-4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
···
658
658
phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
659
659
"qcom,dsi-phy-regulator-ldo-mode");
660
660
661
-
phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
661
+
phy->base = msm_ioremap_size(pdev, "dsi_phy", "DSI_PHY", &phy->base_size);
662
662
if (IS_ERR(phy->base)) {
663
663
DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
664
664
ret = -ENOMEM;
665
665
goto fail;
666
666
}
667
667
668
-
phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
668
+
phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", "DSI_PLL", &phy->pll_size);
669
669
if (IS_ERR(phy->pll_base)) {
670
670
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
671
671
ret = -ENOMEM;
···
673
673
}
674
674
675
675
if (phy->cfg->has_phy_lane) {
676
-
phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
676
+
phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", "DSI_PHY_LANE", &phy->lane_size);
677
677
if (IS_ERR(phy->lane_base)) {
678
678
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__);
679
679
ret = -ENOMEM;
···
682
682
}
683
683
684
684
if (phy->cfg->has_phy_regulator) {
685
-
phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
685
+
phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", "DSI_PHY_REG", &phy->reg_size);
686
686
if (IS_ERR(phy->reg_base)) {
687
687
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__);
688
688
ret = -ENOMEM;
···
867
867
}
868
868
869
869
return 0;
870
+
}
871
+
872
+
void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy)
873
+
{
874
+
msm_disp_snapshot_add_block(disp_state,
875
+
phy->base_size, phy->base,
876
+
"dsi%d_phy", phy->id);
877
+
878
+
/* Do not try accessing PLL registers if it is switched off */
879
+
if (phy->pll_on)
880
+
msm_disp_snapshot_add_block(disp_state,
881
+
phy->pll_size, phy->pll_base,
882
+
"dsi%d_pll", phy->id);
883
+
884
+
if (phy->lane_base)
885
+
msm_disp_snapshot_add_block(disp_state,
886
+
phy->lane_size, phy->lane_base,
887
+
"dsi%d_lane", phy->id);
888
+
889
+
if (phy->reg_base)
890
+
msm_disp_snapshot_add_block(disp_state,
891
+
phy->reg_size, phy->reg_base,
892
+
"dsi%d_reg", phy->id);
870
893
}
+4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+6
-1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+6
-1
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
···
9
9
10
10
#include "dsi_phy.h"
11
11
#include "dsi.xml.h"
12
+
#include "dsi_phy_7nm.xml.h"
12
13
13
14
/*
14
15
* DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
···
974
973
.restore_pll_state = dsi_7nm_pll_restore_state,
975
974
},
976
975
.min_pll_rate = 600000000UL,
977
-
.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
976
+
#ifdef CONFIG_64BIT
977
+
.max_pll_rate = 5000000000UL,
978
+
#else
979
+
.max_pll_rate = ULONG_MAX,
980
+
#endif
978
981
.io_start = { 0xae94400, 0xae96400 },
979
982
.num_dsi_phy = 2,
980
983
.quirks = DSI_PHY_7NM_QUIRK_V4_1,
+20
-12
drivers/gpu/drm/msm/dsi/sfpb.xml.h
+20
-12
drivers/gpu/drm/msm/dsi/sfpb.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+20
-12
drivers/gpu/drm/msm/edp/edp.xml.h
+20
-12
drivers/gpu/drm/msm/edp/edp.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+20
-12
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+20
-12
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+20
-12
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+20
-12
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
···
8
8
git clone https://github.com/freedreno/envytools.git
9
9
10
10
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
12
-
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13
-
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
14
-
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
15
-
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
16
-
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
17
-
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
18
-
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
19
-
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
20
-
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
21
-
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
11
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29
+
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
22
30
23
-
Copyright (C) 2013-2020 by the following authors:
31
+
Copyright (C) 2013-2021 by the following authors:
24
32
- Rob Clark <robdclark@gmail.com> (robclark)
25
33
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
34
+31
drivers/gpu/drm/msm/msm_debugfs.c
+31
drivers/gpu/drm/msm/msm_debugfs.c
···
108
108
.release = msm_gpu_release,
109
109
};
110
110
111
+
static unsigned long last_shrink_freed;
112
+
113
+
static int
114
+
shrink_get(void *data, u64 *val)
115
+
{
116
+
*val = last_shrink_freed;
117
+
118
+
return 0;
119
+
}
120
+
121
+
static int
122
+
shrink_set(void *data, u64 val)
123
+
{
124
+
struct drm_device *dev = data;
125
+
126
+
last_shrink_freed = msm_gem_shrinker_shrink(dev, val);
127
+
128
+
return 0;
129
+
}
130
+
131
+
DEFINE_SIMPLE_ATTRIBUTE(shrink_fops,
132
+
shrink_get, shrink_set,
133
+
"0x%08llx\n");
134
+
135
+
111
136
static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
112
137
{
113
138
struct msm_drm_private *priv = dev->dev_private;
···
250
225
251
226
debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root,
252
227
dev, &msm_gpu_fops);
228
+
229
+
debugfs_create_u32("hangcheck_period_ms", 0600, minor->debugfs_root,
230
+
&priv->hangcheck_period);
231
+
232
+
debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root,
233
+
dev, &shrink_fops);
253
234
254
235
if (priv->kms && priv->kms->funcs->debugfs_init)
255
236
priv->kms->funcs->debugfs_init(priv->kms, minor);
+26
-7
drivers/gpu/drm/msm/msm_drv.c
+26
-7
drivers/gpu/drm/msm/msm_drv.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3
+
* Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4
4
* Copyright (C) 2013 Red Hat
5
5
* Author: Rob Clark <robdclark@gmail.com>
6
6
*/
···
19
19
#include <drm/drm_of.h>
20
20
#include <drm/drm_vblank.h>
21
21
22
+
#include "disp/msm_disp_snapshot.h"
22
23
#include "msm_drv.h"
23
24
#include "msm_debugfs.h"
24
25
#include "msm_fence.h"
···
41
40
* - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
42
41
* - 1.6.0 - Syncobj support
43
42
* - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
43
+
* - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
44
44
*/
45
45
#define MSM_VERSION_MAJOR 1
46
-
#define MSM_VERSION_MINOR 7
46
+
#define MSM_VERSION_MINOR 8
47
47
#define MSM_VERSION_PATCHLEVEL 0
48
48
49
49
static const struct drm_mode_config_funcs mode_config_funcs = {
···
125
123
}
126
124
127
125
static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
128
-
const char *dbgname, bool quiet)
126
+
const char *dbgname, bool quiet, phys_addr_t *psize)
129
127
{
130
128
struct resource *res;
131
129
unsigned long size;
···
154
152
if (reglog)
155
153
printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
156
154
155
+
if (psize)
156
+
*psize = size;
157
+
157
158
return ptr;
158
159
}
159
160
160
161
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
161
162
const char *dbgname)
162
163
{
163
-
return _msm_ioremap(pdev, name, dbgname, false);
164
+
return _msm_ioremap(pdev, name, dbgname, false, NULL);
164
165
}
165
166
166
167
void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
167
168
const char *dbgname)
168
169
{
169
-
return _msm_ioremap(pdev, name, dbgname, true);
170
+
return _msm_ioremap(pdev, name, dbgname, true, NULL);
171
+
}
172
+
173
+
void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
174
+
const char *dbgname, phys_addr_t *psize)
175
+
{
176
+
return _msm_ioremap(pdev, name, dbgname, false, psize);
170
177
}
171
178
172
179
void msm_writel(u32 data, void __iomem *addr)
···
288
277
if (fbdev && priv->fbdev)
289
278
msm_fbdev_free(ddev);
290
279
#endif
280
+
281
+
msm_disp_snapshot_destroy(ddev);
291
282
292
283
drm_mode_config_cleanup(ddev);
293
284
···
459
446
mdss = priv->mdss;
460
447
461
448
priv->wq = alloc_ordered_workqueue("msm", 0);
449
+
priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
462
450
463
451
INIT_LIST_HEAD(&priv->objects);
464
452
mutex_init(&priv->obj_lock);
···
537
523
priv->event_thread[i].worker = kthread_create_worker(0,
538
524
"crtc_event:%d", priv->event_thread[i].crtc_id);
539
525
if (IS_ERR(priv->event_thread[i].worker)) {
526
+
ret = PTR_ERR(priv->event_thread[i].worker);
540
527
DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
541
528
goto err_msm_uninit;
542
529
}
···
564
549
ret = drm_dev_register(ddev, 0);
565
550
if (ret)
566
551
goto err_msm_uninit;
552
+
553
+
ret = msm_disp_snapshot_init(ddev);
554
+
if (ret)
555
+
DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
567
556
568
557
drm_mode_config_reset(ddev);
569
558
···
707
688
struct msm_kms *kms = priv->kms;
708
689
if (!kms)
709
690
return -ENXIO;
710
-
DBG("dev=%p, crtc=%u", dev, pipe);
691
+
drm_dbg_vbl(dev, "crtc=%u", pipe);
711
692
return vblank_ctrl_queue_work(priv, pipe, true);
712
693
}
713
694
···
719
700
struct msm_kms *kms = priv->kms;
720
701
if (!kms)
721
702
return;
722
-
DBG("dev=%p, crtc=%u", dev, pipe);
703
+
drm_dbg_vbl(dev, "crtc=%u", pipe);
723
704
vblank_ctrl_queue_work(priv, pipe, false);
724
705
}
725
706
+23
-1
drivers/gpu/drm/msm/msm_drv.h
+23
-1
drivers/gpu/drm/msm/msm_drv.h
···
43
43
struct msm_fence_context;
44
44
struct msm_gem_address_space;
45
45
struct msm_gem_vma;
46
+
struct msm_disp_state;
46
47
47
48
#define MAX_CRTCS 8
48
49
#define MAX_PLANES 20
···
168
167
struct msm_file_private *lastctx;
169
168
/* gpu is only set on open(), but we need this info earlier */
170
169
bool is_a2xx;
170
+
bool has_cached_coherent;
171
171
172
172
struct drm_fb_helper *fbdev;
173
173
···
244
242
struct shrinker shrinker;
245
243
246
244
struct drm_atomic_state *pm_state;
245
+
246
+
/* For hang detection, in ms */
247
+
unsigned int hangcheck_period;
247
248
};
248
249
249
250
struct msm_format {
···
299
294
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
300
295
struct drm_file *file);
301
296
297
+
#ifdef CONFIG_DEBUG_FS
298
+
unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
299
+
#endif
300
+
302
301
void msm_gem_shrinker_init(struct drm_device *dev);
303
302
void msm_gem_shrinker_cleanup(struct drm_device *dev);
304
303
···
349
340
void __exit msm_dsi_unregister(void);
350
341
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
351
342
struct drm_encoder *encoder);
343
+
void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
344
+
352
345
#else
353
346
static inline void __init msm_dsi_register(void)
354
347
{
···
364
353
{
365
354
return -EINVAL;
366
355
}
356
+
static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
357
+
{
358
+
}
359
+
367
360
#endif
368
361
369
362
#ifdef CONFIG_DRM_MSM_DP
···
382
367
struct drm_display_mode *mode,
383
368
struct drm_display_mode *adjusted_mode);
384
369
void msm_dp_irq_postinstall(struct msm_dp *dp_display);
370
+
void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
385
371
386
372
void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
387
373
···
426
410
{
427
411
}
428
412
413
+
static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
414
+
{
415
+
}
416
+
429
417
static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
430
418
struct drm_minor *minor)
431
419
{
···
468
448
const char *name);
469
449
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
470
450
const char *dbgname);
451
+
void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
452
+
const char *dbgname, phys_addr_t *size);
471
453
void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
472
454
const char *dbgname);
473
455
void msm_writel(u32 data, void __iomem *addr);
···
524
502
/* for the generated headers: */
525
503
#define INVALID_IDX(idx) ({BUG(); 0;})
526
504
#define fui(x) ({BUG(); 0;})
527
-
#define util_float_to_half(x) ({BUG(); 0;})
505
+
#define _mesa_float_to_half(x) ({BUG(); 0;})
528
506
529
507
530
508
#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
+4
-4
drivers/gpu/drm/msm/msm_fb.c
+4
-4
drivers/gpu/drm/msm/msm_fb.c
···
61
61
62
62
for (i = 0; i < n; i++) {
63
63
ret = msm_gem_get_and_pin_iova(fb->obj[i], aspace, &iova);
64
-
DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);
64
+
drm_dbg_state(fb->dev, "FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);
65
65
if (ret)
66
66
return ret;
67
67
}
···
140
140
const struct msm_format *format;
141
141
int ret, i, n;
142
142
143
-
DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)",
144
-
dev, mode_cmd, mode_cmd->width, mode_cmd->height,
143
+
drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%4.4s)",
144
+
mode_cmd, mode_cmd->width, mode_cmd->height,
145
145
(char *)&mode_cmd->pixel_format);
146
146
147
147
n = info->num_planes;
···
194
194
goto fail;
195
195
}
196
196
197
-
DBG("create: FB ID: %d (%p)", fb->base.id, fb);
197
+
drm_dbg_state(dev, "create: FB ID: %d (%p)", fb->base.id, fb);
198
198
199
199
return fb;
200
200
+19
-19
drivers/gpu/drm/msm/msm_gem.c
+19
-19
drivers/gpu/drm/msm/msm_gem.c
···
211
211
msm_gem_unlock(obj);
212
212
}
213
213
214
+
static pgprot_t msm_gem_pgprot(struct msm_gem_object *msm_obj, pgprot_t prot)
215
+
{
216
+
if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
217
+
return pgprot_writecombine(prot);
218
+
return prot;
219
+
}
220
+
214
221
int msm_gem_mmap_obj(struct drm_gem_object *obj,
215
222
struct vm_area_struct *vma)
216
223
{
···
225
218
226
219
vma->vm_flags &= ~VM_PFNMAP;
227
220
vma->vm_flags |= VM_MIXEDMAP;
228
-
229
-
if (msm_obj->flags & MSM_BO_WC) {
230
-
vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
231
-
} else if (msm_obj->flags & MSM_BO_UNCACHED) {
232
-
vma->vm_page_prot = pgprot_noncached(vm_get_page_prot(vma->vm_flags));
233
-
} else {
234
-
/*
235
-
* Shunt off cached objs to shmem file so they have their own
236
-
* address_space (so unmap_mapping_range does what we want,
237
-
* in particular in the case of mmap'd dmabufs)
238
-
*/
239
-
vma->vm_pgoff = 0;
240
-
vma_set_file(vma, obj->filp);
241
-
242
-
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
243
-
}
221
+
vma->vm_page_prot = msm_gem_pgprot(msm_obj, vm_get_page_prot(vma->vm_flags));
244
222
245
223
return 0;
246
224
}
···
364
372
kfree(vma);
365
373
}
366
374
367
-
/**
375
+
/*
368
376
* If close is true, this also closes the VMA (releasing the allocated
369
377
* iova range) in addition to removing the iommu mapping. In the eviction
370
378
* case (!close), we keep the iova allocated, but only remove the iommu
···
442
450
443
451
if (msm_obj->flags & MSM_BO_MAP_PRIV)
444
452
prot |= IOMMU_PRIV;
453
+
454
+
if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
455
+
prot |= IOMMU_CACHE;
445
456
446
457
GEM_WARN_ON(!msm_gem_is_locked(obj));
447
458
···
648
653
goto fail;
649
654
}
650
655
msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
651
-
VM_MAP, pgprot_writecombine(PAGE_KERNEL));
656
+
VM_MAP, msm_gem_pgprot(msm_obj, PAGE_KERNEL));
652
657
if (msm_obj->vaddr == NULL) {
653
658
ret = -ENOMEM;
654
659
goto fail;
···
768
773
0, (loff_t)-1);
769
774
}
770
775
771
-
/**
776
+
/*
772
777
* Unpin the backing pages and make them available to be swapped out.
773
778
*/
774
779
void msm_gem_evict(struct drm_gem_object *obj)
···
1158
1163
uint32_t size, uint32_t flags,
1159
1164
struct drm_gem_object **obj)
1160
1165
{
1166
+
struct msm_drm_private *priv = dev->dev_private;
1161
1167
struct msm_gem_object *msm_obj;
1162
1168
1163
1169
switch (flags & MSM_BO_CACHE_MASK) {
···
1166
1170
case MSM_BO_CACHED:
1167
1171
case MSM_BO_WC:
1168
1172
break;
1173
+
case MSM_BO_CACHED_COHERENT:
1174
+
if (priv->has_cached_coherent)
1175
+
break;
1176
+
/* fallthrough */
1169
1177
default:
1170
1178
DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
1171
1179
(flags & MSM_BO_CACHE_MASK));
+1
drivers/gpu/drm/msm/msm_gem.h
+1
drivers/gpu/drm/msm/msm_gem.h
···
328
328
struct dma_fence *fence;
329
329
struct msm_gpu_submitqueue *queue;
330
330
struct pid *pid; /* submitting process */
331
+
bool fault_dumped; /* Limit devcoredump dumping to one per submit */
331
332
bool valid; /* true if no cmdstream patching needed */
332
333
bool in_rb; /* "sudo" mode, copy cmds into RB */
333
334
struct msm_ringbuffer *ring;
+18
drivers/gpu/drm/msm/msm_gem_shrinker.c
+18
drivers/gpu/drm/msm/msm_gem_shrinker.c
···
145
145
return (freed > 0) ? freed : SHRINK_STOP;
146
146
}
147
147
148
+
#ifdef CONFIG_DEBUG_FS
149
+
unsigned long
150
+
msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan)
151
+
{
152
+
struct msm_drm_private *priv = dev->dev_private;
153
+
struct shrink_control sc = {
154
+
.nr_to_scan = nr_to_scan,
155
+
};
156
+
int ret;
157
+
158
+
fs_reclaim_acquire(GFP_KERNEL);
159
+
ret = msm_gem_shrinker_scan(&priv->shrinker, &sc);
160
+
fs_reclaim_release(GFP_KERNEL);
161
+
162
+
return ret;
163
+
}
164
+
#endif
165
+
148
166
/* since we don't know any better, lets bail after a few
149
167
* and if necessary the shrinker will be invoked again.
150
168
* Seems better than unmapping *everything*
+1
drivers/gpu/drm/msm/msm_gem_submit.c
+1
drivers/gpu/drm/msm/msm_gem_submit.c
+50
-1
drivers/gpu/drm/msm/msm_gpu.c
+50
-1
drivers/gpu/drm/msm/msm_gpu.c
···
387
387
/* Fill in the additional crash state information */
388
388
state->comm = kstrdup(comm, GFP_KERNEL);
389
389
state->cmd = kstrdup(cmd, GFP_KERNEL);
390
+
state->fault_info = gpu->fault_info;
390
391
391
392
if (submit) {
392
393
int i, nr = 0;
···
560
559
msm_gpu_retire(gpu);
561
560
}
562
561
562
+
static void fault_worker(struct kthread_work *work)
563
+
{
564
+
struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
565
+
struct drm_device *dev = gpu->dev;
566
+
struct msm_gem_submit *submit;
567
+
struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
568
+
char *comm = NULL, *cmd = NULL;
569
+
570
+
mutex_lock(&dev->struct_mutex);
571
+
572
+
submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
573
+
if (submit && submit->fault_dumped)
574
+
goto resume_smmu;
575
+
576
+
if (submit) {
577
+
struct task_struct *task;
578
+
579
+
task = get_pid_task(submit->pid, PIDTYPE_PID);
580
+
if (task) {
581
+
comm = kstrdup(task->comm, GFP_KERNEL);
582
+
cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
583
+
put_task_struct(task);
584
+
}
585
+
586
+
/*
587
+
* When we get GPU iova faults, we can get 1000s of them,
588
+
* but we really only want to log the first one.
589
+
*/
590
+
submit->fault_dumped = true;
591
+
}
592
+
593
+
/* Record the crash state */
594
+
pm_runtime_get_sync(&gpu->pdev->dev);
595
+
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
596
+
pm_runtime_put_sync(&gpu->pdev->dev);
597
+
598
+
kfree(cmd);
599
+
kfree(comm);
600
+
601
+
resume_smmu:
602
+
memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
603
+
gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
604
+
605
+
mutex_unlock(&dev->struct_mutex);
606
+
}
607
+
563
608
static void hangcheck_timer_reset(struct msm_gpu *gpu)
564
609
{
610
+
struct msm_drm_private *priv = gpu->dev->dev_private;
565
611
mod_timer(&gpu->hangcheck_timer,
566
-
round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
612
+
round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
567
613
}
568
614
569
615
static void hangcheck_handler(struct timer_list *t)
···
970
922
INIT_LIST_HEAD(&gpu->active_list);
971
923
kthread_init_work(&gpu->retire_work, retire_worker);
972
924
kthread_init_work(&gpu->recover_work, recover_worker);
925
+
kthread_init_work(&gpu->fault_work, fault_worker);
973
926
974
927
timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
975
928
+18
-11
drivers/gpu/drm/msm/msm_gpu.h
+18
-11
drivers/gpu/drm/msm/msm_gpu.h
···
71
71
uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
72
72
};
73
73
74
+
/* Additional state for iommu faults: */
75
+
struct msm_gpu_fault_info {
76
+
u64 ttbr0;
77
+
unsigned long iova;
78
+
int flags;
79
+
const char *type;
80
+
const char *block;
81
+
};
82
+
74
83
struct msm_gpu {
75
84
const char *name;
76
85
struct drm_device *dev;
···
127
118
struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
128
119
uint32_t fast_rate;
129
120
130
-
/* The gfx-mem interconnect path that's used by all GPU types. */
131
-
struct icc_path *icc_path;
132
-
133
-
/*
134
-
* Second interconnect path for some A3xx and all A4xx GPUs to the
135
-
* On Chip MEMory (OCMEM).
136
-
*/
137
-
struct icc_path *ocmem_icc_path;
138
-
139
121
/* Hang and Inactivity Detection:
140
122
*/
141
123
#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
142
124
143
-
#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
144
-
#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
125
+
#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
145
126
struct timer_list hangcheck_timer;
127
+
128
+
/* Fault info for most recent iova fault: */
129
+
struct msm_gpu_fault_info fault_info;
130
+
131
+
/* work for handling GPU ioval faults: */
132
+
struct kthread_work fault_work;
146
133
147
134
/* work for handling GPU recovery: */
148
135
struct kthread_work recover_work;
···
246
241
247
242
char *comm;
248
243
char *cmd;
244
+
245
+
struct msm_gpu_fault_info fault_info;
249
246
250
247
int nr_bos;
251
248
struct msm_gpu_state_bo *bos;
+5
drivers/gpu/drm/msm/msm_gpummu.c
+5
drivers/gpu/drm/msm/msm_gpummu.c
···
68
68
return 0;
69
69
}
70
70
71
+
static void msm_gpummu_resume_translation(struct msm_mmu *mmu)
72
+
{
73
+
}
74
+
71
75
static void msm_gpummu_destroy(struct msm_mmu *mmu)
72
76
{
73
77
struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
···
87
83
.map = msm_gpummu_map,
88
84
.unmap = msm_gpummu_unmap,
89
85
.destroy = msm_gpummu_destroy,
86
+
.resume_translation = msm_gpummu_resume_translation,
90
87
};
91
88
92
89
struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
+21
-1
drivers/gpu/drm/msm/msm_iommu.c
+21
-1
drivers/gpu/drm/msm/msm_iommu.c
···
184
184
* the arm-smmu driver as a trigger to set up TTBR0
185
185
*/
186
186
if (atomic_inc_return(&iommu->pagetables) == 1) {
187
+
/* Enable stall on iommu fault: */
188
+
adreno_smmu->set_stall(adreno_smmu->cookie, true);
189
+
187
190
ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg);
188
191
if (ret) {
189
192
free_io_pgtable_ops(pagetable->pgtbl_ops);
···
214
211
unsigned long iova, int flags, void *arg)
215
212
{
216
213
struct msm_iommu *iommu = arg;
214
+
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
215
+
struct adreno_smmu_fault_info info, *ptr = NULL;
216
+
217
+
if (adreno_smmu->get_fault_info) {
218
+
adreno_smmu->get_fault_info(adreno_smmu->cookie, &info);
219
+
ptr = &info;
220
+
}
221
+
217
222
if (iommu->base.handler)
218
-
return iommu->base.handler(iommu->base.arg, iova, flags);
223
+
return iommu->base.handler(iommu->base.arg, iova, flags, ptr);
224
+
219
225
pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
220
226
return 0;
227
+
}
228
+
229
+
static void msm_iommu_resume_translation(struct msm_mmu *mmu)
230
+
{
231
+
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
232
+
233
+
adreno_smmu->resume_translation(adreno_smmu->cookie, true);
221
234
}
222
235
223
236
static void msm_iommu_detach(struct msm_mmu *mmu)
···
283
264
.map = msm_iommu_map,
284
265
.unmap = msm_iommu_unmap,
285
266
.destroy = msm_iommu_destroy,
267
+
.resume_translation = msm_iommu_resume_translation,
286
268
};
287
269
288
270
struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
+9
drivers/gpu/drm/msm/msm_kms.h
+9
drivers/gpu/drm/msm/msm_kms.h
···
122
122
bool cmd_mode);
123
123
/* cleanup: */
124
124
void (*destroy)(struct msm_kms *kms);
125
+
126
+
/* snapshot: */
127
+
void (*snapshot)(struct msm_disp_state *disp_state, struct msm_kms *kms);
128
+
125
129
#ifdef CONFIG_DEBUG_FS
126
130
/* debugfs: */
127
131
int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
···
155
151
156
152
/* mapper-id used to request GEM buffer mapped for scanout: */
157
153
struct msm_gem_address_space *aspace;
154
+
155
+
/* disp snapshot support */
156
+
struct kthread_worker *dump_worker;
157
+
struct kthread_work dump_work;
158
+
struct mutex dump_mutex;
158
159
159
160
/*
160
161
* For async commit, where ->flush_commit() and later happens
+3
-2
drivers/gpu/drm/msm/msm_mmu.h
+3
-2
drivers/gpu/drm/msm/msm_mmu.h
···
15
15
size_t len, int prot);
16
16
int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len);
17
17
void (*destroy)(struct msm_mmu *mmu);
18
+
void (*resume_translation)(struct msm_mmu *mmu);
18
19
};
19
20
20
21
enum msm_mmu_type {
···
27
26
struct msm_mmu {
28
27
const struct msm_mmu_funcs *funcs;
29
28
struct device *dev;
30
-
int (*handler)(void *arg, unsigned long iova, int flags);
29
+
int (*handler)(void *arg, unsigned long iova, int flags, void *data);
31
30
void *arg;
32
31
enum msm_mmu_type type;
33
32
};
···
44
43
struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
45
44
46
45
static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
47
-
int (*handler)(void *arg, unsigned long iova, int flags))
46
+
int (*handler)(void *arg, unsigned long iova, int flags, void *data))
48
47
{
49
48
mmu->arg = arg;
50
49
mmu->handler = handler;
+1
drivers/gpu/drm/selftests/test-drm_framebuffer.c
+1
drivers/gpu/drm/selftests/test-drm_framebuffer.c
+50
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+50
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
···
13
13
struct arm_smmu_device smmu;
14
14
bool bypass_quirk;
15
15
u8 bypass_cbndx;
16
+
u32 stall_enabled;
16
17
};
17
18
18
19
static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
···
24
23
static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
25
24
u32 reg)
26
25
{
26
+
struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
27
+
27
28
/*
28
29
* On the GPU device we want to process subsequent transactions after a
29
30
* fault to keep the GPU from hanging
30
31
*/
31
32
reg |= ARM_SMMU_SCTLR_HUPCF;
32
33
34
+
if (qsmmu->stall_enabled & BIT(idx))
35
+
reg |= ARM_SMMU_SCTLR_CFCFG;
36
+
33
37
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
38
+
}
39
+
40
+
static void qcom_adreno_smmu_get_fault_info(const void *cookie,
41
+
struct adreno_smmu_fault_info *info)
42
+
{
43
+
struct arm_smmu_domain *smmu_domain = (void *)cookie;
44
+
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
45
+
struct arm_smmu_device *smmu = smmu_domain->smmu;
46
+
47
+
info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
48
+
info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
49
+
info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
50
+
info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
51
+
info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
52
+
info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
53
+
info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
54
+
}
55
+
56
+
static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
57
+
{
58
+
struct arm_smmu_domain *smmu_domain = (void *)cookie;
59
+
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
60
+
struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
61
+
62
+
if (enabled)
63
+
qsmmu->stall_enabled |= BIT(cfg->cbndx);
64
+
else
65
+
qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
66
+
}
67
+
68
+
static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate)
69
+
{
70
+
struct arm_smmu_domain *smmu_domain = (void *)cookie;
71
+
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
72
+
struct arm_smmu_device *smmu = smmu_domain->smmu;
73
+
u32 reg = 0;
74
+
75
+
if (terminate)
76
+
reg |= ARM_SMMU_RESUME_TERMINATE;
77
+
78
+
arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
34
79
}
35
80
36
81
#define QCOM_ADRENO_SMMU_GPU_SID 0
···
203
156
priv->cookie = smmu_domain;
204
157
priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
205
158
priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
159
+
priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
160
+
priv->set_stall = qcom_adreno_smmu_set_stall;
161
+
priv->resume_translation = qcom_adreno_smmu_resume_translation;
206
162
207
163
return 0;
208
164
}
+7
-2
drivers/iommu/arm/arm-smmu/arm-smmu.c
+7
-2
drivers/iommu/arm/arm-smmu/arm-smmu.c
···
408
408
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
409
409
struct arm_smmu_device *smmu = smmu_domain->smmu;
410
410
int idx = smmu_domain->cfg.cbndx;
411
+
int ret;
411
412
412
413
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
413
414
if (!(fsr & ARM_SMMU_FSR_FAULT))
···
418
417
iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
419
418
cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
420
419
421
-
dev_err_ratelimited(smmu->dev,
422
-
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
420
+
ret = report_iommu_fault(domain, NULL, iova,
421
+
fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
422
+
423
+
if (ret == -ENOSYS)
424
+
dev_err_ratelimited(smmu->dev,
425
+
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
423
426
fsr, iova, fsynr, cbfrsynra, idx);
424
427
425
428
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
+2
drivers/iommu/arm/arm-smmu/arm-smmu.h
+2
drivers/iommu/arm/arm-smmu/arm-smmu.h
+36
include/linux/adreno-smmu-priv.h
+36
include/linux/adreno-smmu-priv.h
···
9
9
#include <linux/io-pgtable.h>
10
10
11
11
/**
12
+
* struct adreno_smmu_fault_info - container for key fault information
13
+
*
14
+
* @far: The faulting IOVA from ARM_SMMU_CB_FAR
15
+
* @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
16
+
* @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
17
+
* @fsr: The fault status from ARM_SMMU_CB_FSR
18
+
* @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
19
+
* @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
20
+
* @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
21
+
*
22
+
* This struct passes back key page fault information to the GPU driver
23
+
* through the get_fault_info function pointer.
24
+
* The GPU driver can use this information to print informative
25
+
* log messages and provide deeper GPU specific insight into the fault.
26
+
*/
27
+
struct adreno_smmu_fault_info {
28
+
u64 far;
29
+
u64 ttbr0;
30
+
u32 contextidr;
31
+
u32 fsr;
32
+
u32 fsynr0;
33
+
u32 fsynr1;
34
+
u32 cbfrsynra;
35
+
};
36
+
37
+
/**
12
38
* struct adreno_smmu_priv - private interface between adreno-smmu and GPU
13
39
*
14
40
* @cookie: An opque token provided by adreno-smmu and passed
···
43
17
* @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
44
18
* NULL config disables TTBR0 translation, otherwise
45
19
* TTBR0 translation is enabled with the specified cfg
20
+
* @get_fault_info: Called by the GPU fault handler to get information about
21
+
* the fault
22
+
* @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call
23
+
* before set_ttbr0_cfg(). If stalling on fault is enabled,
24
+
* the GPU driver must call resume_translation()
25
+
* @resume_translation: Resume translation after a fault
26
+
*
46
27
*
47
28
* The GPU driver (drm/msm) and adreno-smmu work together for controlling
48
29
* the GPU's SMMU instance. This is by necessity, as the GPU is directly
···
64
31
const void *cookie;
65
32
const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
66
33
int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
34
+
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
35
+
void (*set_stall)(const void *cookie, bool enabled);
36
+
void (*resume_translation)(const void *cookie, bool terminate);
67
37
};
68
38
69
39
#endif /* __ADRENO_SMMU_PRIV_H */
+3
-4
include/uapi/drm/msm_drm.h
+3
-4
include/uapi/drm/msm_drm.h
···
94
94
/* cache modes */
95
95
#define MSM_BO_CACHED 0x00010000
96
96
#define MSM_BO_WC 0x00020000
97
-
#define MSM_BO_UNCACHED 0x00040000
97
+
#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
98
+
#define MSM_BO_CACHED_COHERENT 0x080000
98
99
99
100
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
100
101
MSM_BO_GPU_READONLY | \
101
-
MSM_BO_CACHED | \
102
-
MSM_BO_WC | \
103
-
MSM_BO_UNCACHED)
102
+
MSM_BO_CACHE_MASK)
104
103
105
104
struct drm_msm_gem_new {
106
105
__u64 size; /* in */