Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
x86: Work around mmio config space quirk on AMD Fam10h
Some broken devices have been discovered to require %al/%ax/%eax registers
for MMIO config space accesses. Modify mmconfig.c to use these registers
explicitly (rather than modify the global readb/writeb/etc inlines).
AK: also changed i386 to always use eax
AK: moved change to extended space probing to different patch
AK: reworked with inlines according to Linus' requirements.
AK: improve comments.
Signed-off-by: dean gaudet <dean@arctic.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
authored by dean gaudet and committed by Linus Torvalds 3320ad99 9535239f
+6
-8
arch/i386/pci/mmconfig.c
+6
-8
arch/i386/pci/mmconfig.c
···
82
83
switch (len) {
84
case 1:
85
-
*value = readb(mmcfg_virt_addr + reg);
86
break;
87
case 2:
88
-
*value = readw(mmcfg_virt_addr + reg);
89
break;
90
case 4:
91
-
*value = readl(mmcfg_virt_addr + reg);
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break;
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}
94
-
95
spin_unlock_irqrestore(&pci_config_lock, flags);
96
97
return 0;
···
115
116
switch (len) {
117
case 1:
118
-
writeb(value, mmcfg_virt_addr + reg);
119
break;
120
case 2:
121
-
writew(value, mmcfg_virt_addr + reg);
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break;
123
case 4:
124
-
writel(value, mmcfg_virt_addr + reg);
125
break;
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}
127
-
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
···
82
83
switch (len) {
84
case 1:
85
+
*value = mmio_config_readb(mmcfg_virt_addr + reg);
86
break;
87
case 2:
88
+
*value = mmio_config_readw(mmcfg_virt_addr + reg);
89
break;
90
case 4:
91
+
*value = mmio_config_readl(mmcfg_virt_addr + reg);
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break;
93
}
94
spin_unlock_irqrestore(&pci_config_lock, flags);
95
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return 0;
···
116
117
switch (len) {
118
case 1:
119
+
mmio_config_writeb(mmcfg_virt_addr, value);
120
break;
121
case 2:
122
+
mmio_config_writew(mmcfg_virt_addr, value);
123
break;
124
case 4:
125
+
mmio_config_writel(mmcfg_virt_addr, value);
126
break;
127
}
128
spin_unlock_irqrestore(&pci_config_lock, flags);
129
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return 0;
+43
arch/i386/pci/pci.h
+43
arch/i386/pci/pci.h
···
104
extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
105
unsigned int devfn);
106
extern int __init pci_mmcfg_arch_init(void);
107
+
108
+
/*
109
+
* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
110
+
* on their northbrige except through the * %eax register. As such, you MUST
111
+
* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
112
+
* accessor functions.
113
+
* In fact just use pci_config_*, nothing else please.
114
+
*/
115
+
static inline unsigned char mmio_config_readb(void __iomem *pos)
116
+
{
117
+
u8 val;
118
+
asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
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+
return val;
120
+
}
121
+
122
+
static inline unsigned short mmio_config_readw(void __iomem *pos)
123
+
{
124
+
u16 val;
125
+
asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
126
+
return val;
127
+
}
128
+
129
+
static inline unsigned int mmio_config_readl(void __iomem *pos)
130
+
{
131
+
u32 val;
132
+
asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
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+
return val;
134
+
}
135
+
136
+
static inline void mmio_config_writeb(void __iomem *pos, u8 val)
137
+
{
138
+
asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
139
+
}
140
+
141
+
static inline void mmio_config_writew(void __iomem *pos, u16 val)
142
+
{
143
+
asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
144
+
}
145
+
146
+
static inline void mmio_config_writel(void __iomem *pos, u32 val)
147
+
{
148
+
asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
149
+
}
+6
-6
arch/x86_64/pci/mmconfig.c
+6
-6
arch/x86_64/pci/mmconfig.c
···
66
67
switch (len) {
68
case 1:
69
-
*value = readb(addr + reg);
70
break;
71
case 2:
72
-
*value = readw(addr + reg);
73
break;
74
case 4:
75
-
*value = readl(addr + reg);
76
break;
77
}
78
···
94
95
switch (len) {
96
case 1:
97
-
writeb(value, addr + reg);
98
break;
99
case 2:
100
-
writew(value, addr + reg);
101
break;
102
case 4:
103
-
writel(value, addr + reg);
104
break;
105
}
106
···
66
67
switch (len) {
68
case 1:
69
+
*value = mmio_config_readb(addr + reg);
70
break;
71
case 2:
72
+
*value = mmio_config_readw(addr + reg);
73
break;
74
case 4:
75
+
*value = mmio_config_readl(addr + reg);
76
break;
77
}
78
···
94
95
switch (len) {
96
case 1:
97
+
mmio_config_writeb(addr + reg, value);
98
break;
99
case 2:
100
+
mmio_config_writew(addr + reg, value);
101
break;
102
case 4:
103
+
mmio_config_writel(addr + reg, value);
104
break;
105
}
106