tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/panel: himax-hx83112a: transition to mipi_dsi wrapped functions

Changes the himax-hx83112a panel to use multi style functions for
improved error handling.

Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240904141521.554451-1-tejasvipin76@gmail.com

authored by

Tejas Vipin and committed by
Douglas Anderson 32e5666b d2194256

+133 -158
+133 -158
drivers/gpu/drm/panel/panel-himax-hx83112a.c
··· 56 56 msleep(50); 57 57 } 58 58 59 - static int hx83112a_on(struct hx83112a_panel *ctx) 59 + static int hx83112a_on(struct mipi_dsi_device *dsi) 60 60 { 61 - struct mipi_dsi_device *dsi = ctx->dsi; 62 - struct device *dev = &dsi->dev; 63 - int ret; 61 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 64 62 65 63 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 66 64 67 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETEXTC, 0x83, 0x11, 0x2a); 68 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETPOWER1, 69 - 0x08, 0x28, 0x28, 0x83, 0x83, 0x4c, 0x4f, 0x33); 70 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDISP, 71 - 0x00, 0x02, 0x00, 0x90, 0x24, 0x00, 0x08, 0x19, 72 - 0xea, 0x11, 0x11, 0x00, 0x11, 0xa3); 73 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDRV, 74 - 0x58, 0x68, 0x58, 0x68, 0x0f, 0xef, 0x0b, 0xc0, 75 - 0x0b, 0xc0, 0x0b, 0xc0, 0x00, 0xff, 0x00, 0xff, 76 - 0x00, 0x00, 0x14, 0x15, 0x00, 0x29, 0x11, 0x07, 77 - 0x12, 0x00, 0x29); 78 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x02); 79 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDRV, 80 - 0x00, 0x12, 0x12, 0x11, 0x88, 0x12, 0x12, 0x00, 81 - 0x53); 82 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x00); 83 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x03); 84 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDGCLUT, 85 - 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, 86 - 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, 87 - 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, 88 - 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, 89 - 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, 90 - 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, 91 - 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, 92 - 0x40); 93 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x02); 94 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDGCLUT, 95 - 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, 96 - 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, 97 - 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, 98 - 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, 99 - 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, 100 - 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, 101 - 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, 102 - 0x40); 103 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x01); 104 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDGCLUT, 105 - 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, 106 - 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, 107 - 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, 108 - 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, 109 - 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, 110 - 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, 111 - 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, 112 - 0x40); 113 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x00); 114 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDGCLUT, 0x01); 115 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTCON, 116 - 0x70, 0x00, 0x04, 0xe0, 0x33, 0x00); 117 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETPANEL, 0x08); 118 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETPOWER2, 0x2b, 0x2b); 119 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP0, 120 - 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 121 - 0x08, 0x03, 0x03, 0x22, 0x18, 0x07, 0x07, 0x07, 122 - 0x07, 0x32, 0x10, 0x06, 0x00, 0x06, 0x32, 0x10, 123 - 0x07, 0x00, 0x07, 0x32, 0x19, 0x31, 0x09, 0x31, 124 - 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 125 - 0x09, 0x30, 0x00, 0x00, 0x00, 0x06, 0x0d, 0x00, 126 - 0x0f); 127 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x01); 128 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP0, 129 - 0x00, 0x00, 0x19, 0x10, 0x00, 0x0a, 0x00, 0x81); 130 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x00); 131 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP1, 132 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 133 - 0xc0, 0xc0, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 134 - 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, 135 - 0x28, 0x28, 0x24, 0x24, 0x02, 0x03, 0x02, 0x03, 136 - 0x00, 0x01, 0x00, 0x01, 0x31, 0x31, 0x31, 0x31, 137 - 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); 138 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP2, 139 - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 140 - 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 141 - 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, 142 - 0x24, 0x24, 0x28, 0x28, 0x01, 0x00, 0x01, 0x00, 143 - 0x03, 0x02, 0x03, 0x02, 0x31, 0x31, 0x31, 0x31, 144 - 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); 145 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP3, 146 - 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, 147 - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, 148 - 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, 0xaa, 0xaa); 149 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x01); 150 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP3, 151 - 0xaa, 0x2e, 0x28, 0x00, 0x00, 0x00, 0xaa, 0x2e, 152 - 0x28, 0x00, 0x00, 0x00, 0xaa, 0xee, 0xaa, 0xaa, 153 - 0xaa, 0xaa, 0xaa, 0xee, 0xaa, 0xaa, 0xaa, 0xaa); 154 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x02); 155 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP3, 156 - 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xff, 157 - 0xff, 0xff, 0xff, 0xff); 158 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x03); 159 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP3, 160 - 0xaa, 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 161 - 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 162 - 0xff, 0xff, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff); 163 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x00); 164 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTP1, 165 - 0x0e, 0x0e, 0x1e, 0x65, 0x1c, 0x65, 0x00, 0x50, 166 - 0x20, 0x20, 0x00, 0x00, 0x02, 0x02, 0x02, 0x05, 167 - 0x14, 0x14, 0x32, 0xb9, 0x23, 0xb9, 0x08); 168 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x01); 169 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTP1, 170 - 0x02, 0x00, 0xa8, 0x01, 0xa8, 0x0d, 0xa4, 0x0e); 171 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x02); 172 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTP1, 173 - 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 174 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 175 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 176 - 0x00, 0x00, 0x00, 0x02, 0x00); 177 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETBANK, 0x00); 178 - mipi_dsi_dcs_write_seq(dsi, HX83112A_UNKNOWN1, 0xc3); 179 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETCLOCK, 0xd1, 0xd6); 180 - mipi_dsi_dcs_write_seq(dsi, HX83112A_UNKNOWN1, 0x3f); 181 - mipi_dsi_dcs_write_seq(dsi, HX83112A_UNKNOWN1, 0xc6); 182 - mipi_dsi_dcs_write_seq(dsi, HX83112A_SETPTBA, 0x37); 183 - mipi_dsi_dcs_write_seq(dsi, HX83112A_UNKNOWN1, 0x3f); 65 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETEXTC, 0x83, 0x11, 0x2a); 66 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPOWER1, 67 + 0x08, 0x28, 0x28, 0x83, 0x83, 0x4c, 0x4f, 0x33); 68 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDISP, 69 + 0x00, 0x02, 0x00, 0x90, 0x24, 0x00, 0x08, 0x19, 70 + 0xea, 0x11, 0x11, 0x00, 0x11, 0xa3); 71 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV, 72 + 0x58, 0x68, 0x58, 0x68, 0x0f, 0xef, 0x0b, 0xc0, 73 + 0x0b, 0xc0, 0x0b, 0xc0, 0x00, 0xff, 0x00, 0xff, 74 + 0x00, 0x00, 0x14, 0x15, 0x00, 0x29, 0x11, 0x07, 75 + 0x12, 0x00, 0x29); 76 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02); 77 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV, 78 + 0x00, 0x12, 0x12, 0x11, 0x88, 0x12, 0x12, 0x00, 79 + 0x53); 80 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00); 81 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x03); 82 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT, 83 + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, 84 + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, 85 + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, 86 + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, 87 + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, 88 + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, 89 + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, 90 + 0x40); 91 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02); 92 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT, 93 + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, 94 + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, 95 + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, 96 + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, 97 + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, 98 + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, 99 + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, 100 + 0x40); 101 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x01); 102 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT, 103 + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, 104 + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, 105 + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, 106 + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, 107 + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, 108 + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, 109 + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, 110 + 0x40); 111 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00); 112 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT, 0x01); 113 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTCON, 114 + 0x70, 0x00, 0x04, 0xe0, 0x33, 0x00); 115 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPANEL, 0x08); 116 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPOWER2, 0x2b, 0x2b); 117 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP0, 118 + 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 119 + 0x08, 0x03, 0x03, 0x22, 0x18, 0x07, 0x07, 0x07, 120 + 0x07, 0x32, 0x10, 0x06, 0x00, 0x06, 0x32, 0x10, 121 + 0x07, 0x00, 0x07, 0x32, 0x19, 0x31, 0x09, 0x31, 122 + 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, 123 + 0x09, 0x30, 0x00, 0x00, 0x00, 0x06, 0x0d, 0x00, 124 + 0x0f); 125 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x01); 126 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP0, 127 + 0x00, 0x00, 0x19, 0x10, 0x00, 0x0a, 0x00, 0x81); 128 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00); 129 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP1, 130 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 131 + 0xc0, 0xc0, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 132 + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, 133 + 0x28, 0x28, 0x24, 0x24, 0x02, 0x03, 0x02, 0x03, 134 + 0x00, 0x01, 0x00, 0x01, 0x31, 0x31, 0x31, 0x31, 135 + 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); 136 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP2, 137 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 138 + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 139 + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, 140 + 0x24, 0x24, 0x28, 0x28, 0x01, 0x00, 0x01, 0x00, 141 + 0x03, 0x02, 0x03, 0x02, 0x31, 0x31, 0x31, 0x31, 142 + 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); 143 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP3, 144 + 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, 145 + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, 146 + 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, 0xaa, 0xaa); 147 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x01); 148 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP3, 149 + 0xaa, 0x2e, 0x28, 0x00, 0x00, 0x00, 0xaa, 0x2e, 150 + 0x28, 0x00, 0x00, 0x00, 0xaa, 0xee, 0xaa, 0xaa, 151 + 0xaa, 0xaa, 0xaa, 0xee, 0xaa, 0xaa, 0xaa, 0xaa); 152 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02); 153 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP3, 154 + 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xff, 155 + 0xff, 0xff, 0xff, 0xff); 156 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x03); 157 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP3, 158 + 0xaa, 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 159 + 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 160 + 0xff, 0xff, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff); 161 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00); 162 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTP1, 163 + 0x0e, 0x0e, 0x1e, 0x65, 0x1c, 0x65, 0x00, 0x50, 164 + 0x20, 0x20, 0x00, 0x00, 0x02, 0x02, 0x02, 0x05, 165 + 0x14, 0x14, 0x32, 0xb9, 0x23, 0xb9, 0x08); 166 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x01); 167 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTP1, 168 + 0x02, 0x00, 0xa8, 0x01, 0xa8, 0x0d, 0xa4, 0x0e); 169 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02); 170 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTP1, 171 + 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 172 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 173 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 174 + 0x00, 0x00, 0x00, 0x02, 0x00); 175 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00); 176 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_UNKNOWN1, 0xc3); 177 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETCLOCK, 0xd1, 0xd6); 178 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_UNKNOWN1, 0x3f); 179 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_UNKNOWN1, 0xc6); 180 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPTBA, 0x37); 181 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_UNKNOWN1, 0x3f); 184 182 185 - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 186 - if (ret < 0) { 187 - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); 188 - return ret; 189 - } 190 - msleep(150); 183 + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 184 + mipi_dsi_msleep(&dsi_ctx, 150); 191 185 192 - ret = mipi_dsi_dcs_set_display_on(dsi); 193 - if (ret < 0) { 194 - dev_err(dev, "Failed to set display on: %d\n", ret); 195 - return ret; 196 - } 197 - msleep(50); 186 + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 187 + mipi_dsi_msleep(&dsi_ctx, 50); 198 188 199 - return 0; 189 + return dsi_ctx.accum_err; 200 190 } 201 191 202 192 static int hx83112a_disable(struct drm_panel *panel) 203 193 { 204 194 struct hx83112a_panel *ctx = to_hx83112a_panel(panel); 205 195 struct mipi_dsi_device *dsi = ctx->dsi; 206 - struct device *dev = &dsi->dev; 207 - int ret; 196 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 208 197 209 198 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 210 199 211 - ret = mipi_dsi_dcs_set_display_off(dsi); 212 - if (ret < 0) { 213 - dev_err(dev, "Failed to set display off: %d\n", ret); 214 - return ret; 215 - } 216 - msleep(20); 200 + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 201 + mipi_dsi_msleep(&dsi_ctx, 20); 202 + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 203 + mipi_dsi_msleep(&dsi_ctx, 120); 217 204 218 - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 219 - if (ret < 0) { 220 - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); 221 - return ret; 222 - } 223 - msleep(120); 224 - 225 - return 0; 205 + return dsi_ctx.accum_err; 226 206 } 227 207 228 208 static int hx83112a_prepare(struct drm_panel *panel) 229 209 { 230 210 struct hx83112a_panel *ctx = to_hx83112a_panel(panel); 231 - struct device *dev = &ctx->dsi->dev; 232 211 int ret; 233 212 234 213 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 235 - if (ret < 0) { 236 - dev_err(dev, "Failed to enable regulators: %d\n", ret); 214 + if (ret < 0) 237 215 return ret; 238 - } 239 216 240 217 hx83112a_reset(ctx); 241 218 242 - ret = hx83112a_on(ctx); 219 + ret = hx83112a_on(ctx->dsi); 243 220 if (ret < 0) { 244 - dev_err(dev, "Failed to initialize panel: %d\n", ret); 245 221 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 246 222 regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 247 - return ret; 248 223 } 249 224 250 - return 0; 225 + return ret; 251 226 } 252 227 253 228 static int hx83112a_unprepare(struct drm_panel *panel)